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Hello build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57943
to look at the new patch set (#5).
Change subject: soc/intel/common: round PM Timer emulation frequency multiplier
......................................................................
soc/intel/common: round PM Timer emulation frequency multiplier
Round the PM Timer emulation frequency multiplier to the closest value
to increase precision.
Test: compared hexdumps of CML binaries for the expected result:
before: 0x262E8B51, after: 0x262E8B52
Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/cpu/pm_timer_emulation.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/57943/5
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
> I think it would have been better to simply enable everything. The […]
`src/southbridge/intel/bd82x6x/early_pch.c` is probably not a bad
place to look at. It shows that with some strategy all the convo-
luted code boils down to two lines.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
I think it would have been better to simply enable everything. The
current situation where we enable random things by default leads
to incomplete board ports. Looking at the code for boards already
in the tree, we can neither tell what bits they need to be set nor
what bits would conflict if we'd set them all.
Which led to the bad situation, I guess, that somebody needs an
additional bit set but doesn't know if it's safe to do so for all
boards.
It seems too late to fix for older platforms without looking into
a lot of boards or risking regressions. But maybe it's not too
late for Tiger Lake?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
Well, calling `lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F)` on board level would have been enough
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 )
Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
Patch Set 32:
(1 comment)
File payloads/libpayload/include/sysinfo.h:
https://review.coreboot.org/c/coreboot/+/57069/comment/d10f5582_b2333c19
PS32, Line 152: uintptr_t
> I think it would be better to keep this as `struct type_c_info *`, else each payload user will have […]
There's an easy-to-miss comment above the struct. We had pointers here
before and it was constantly breaking payloads that support relocation
(might just be FILO).
Actually one shouldn't cast but use phys_to_virt(). But that doesn't
matter in payload-specific code.
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Change subject: mb/google/brask: Correct SSD power sequence
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58045/comment/c95bbb6c_e3aeb707
PS3, Line 7: brask
> Done
Hmm, but it’s under variants (altough there is a baseboard directory). Very confusing.
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Change subject: util/cbfstool: Add support for ARM64 UefiPayload
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58055/comment/faa39585_0556c230
PS8, Line 10: ARM SystemReady
What is ARM SystemReady?
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Change subject: payloads: Add UefiPayload support to ARM64 platforms
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58054/comment/adec5f02_55d79232
PS6, Line 12:
Tested on what device?
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Change subject: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h
......................................................................
Patch Set 2: Code-Review+2
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Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
Patch Set 32:
(2 comments)
File payloads/libpayload/include/sysinfo.h:
https://review.coreboot.org/c/coreboot/+/57069/comment/d76bf4af_8f36bccd
PS32, Line 152: uintptr_t
I think it would be better to keep this as `struct type_c_info *`, else each payload user will have to typecast this member when using it.
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/57069/comment/c18f15d7_8b6e51c2
PS27, Line 431: enum type_c_orientation {
> I like the idea of adding the enum in a follow-up. […]
Ack
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