coreboot-gerrit September 2020

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Change in coreboot[master]: drivers/i2c/at24rf08c: Log number of failed writes
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38393 ) Change subject: drivers/i2c/at24rf08c: Log number of failed writes ...................................................................... drivers/i2c/at24rf08c: Log number of failed writes Change-Id: I1f786043557b11824d4efbde0689d1feb73de6e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/i2c/at24rf08c/at24rf08c.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38393/1 diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 11a6fd2..50501ba 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -35,8 +35,10 @@ /* After a register write AT24RF08C sometimes stops responding. Retry several times in case of failure. */ for (j = 0; j < 100; j++) - if (smbus_write_byte(dev, i, 0x0f) >= 0) + if (smbus_write_byte(dev, i, 0x0f) >= 0) { + printk(BIOS_DEBUG, "j = %d", j); break; + } } printk(BIOS_DEBUG, "init EEPROM done\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/38393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f786043557b11824d4efbde0689d1feb73de6e1 Gerrit-Change-Number: 38393 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Measure execution time of `get_smbios_strings()`
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38314 ) Change subject: arch/x86/smbios: Measure execution time of `get_smbios_strings()` ...................................................................... arch/x86/smbios: Measure execution time of `get_smbios_strings()` Change-Id: I97cfcd0849665b039920083bccfad8349d5de2c1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/arch/x86/smbios.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38314/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cd4518..7de9acb 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -28,6 +28,7 @@ #include <device/pci_ids.h> #include <device/pci_def.h> #include <device/pci.h> +#include <timer.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -942,6 +943,7 @@ struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; struct device *dev; + struct stopwatch sw; memset(t, 0, sizeof(*t)); t->type = SMBIOS_OEM_STRINGS; @@ -949,8 +951,12 @@ t->length = len = sizeof(*t) - 2; for (dev = all_devices; dev; dev = dev->next) { - if (dev->ops && dev->ops->get_smbios_strings) + if (dev->ops && dev->ops->get_smbios_strings) { + stopwatch_init_msecs(&sw); dev->ops->get_smbios_strings(dev, t); + printk(BIOS_SPEW, "%s get_smbios_strings took %lu ms\n", + dev_path(dev), stopwatch_duration_msecs(&sw)); + } } if (t->count == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97cfcd0849665b039920083bccfad8349d5de2c1 Gerrit-Change-Number: 38314 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/at24rf08c: Tighten count variable type to unsigned integers
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38394 ) Change subject: drivers/i2c/at24rf08c: Tighten count variable type to unsigned integers ...................................................................... drivers/i2c/at24rf08c: Tighten count variable type to unsigned integers Change-Id: I225d0177b78984783d4f2506873ed220863b0467 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/i2c/at24rf08c/at24rf08c.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38394/1 diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 50501ba..624df7d 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -19,7 +19,7 @@ static void at24rf08c_init(struct device *dev) { - int i, j; + unsigned int i, j; if (!dev->enabled) return; @@ -36,7 +36,7 @@ Retry several times in case of failure. */ for (j = 0; j < 100; j++) if (smbus_write_byte(dev, i, 0x0f) >= 0) { - printk(BIOS_DEBUG, "j = %d", j); + printk(BIOS_DEBUG, "i= = %u, j = %u\n", j); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I225d0177b78984783d4f2506873ed220863b0467 Gerrit-Change-Number: 38394 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: [under test]mb/google/hatch: Program gpio clk power gating settings i...
by Kane Chen (Code Review) 10 Jun '23

10 Jun '23

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37865 ) Change subject: [under test]mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0 ...................................................................... [under test]mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0 With PchPmSlpS0Vm075VSupport FSP UPD set, SoC requires gpio clk to be power gated. But when gpio clk is power gated, it requires longer interrupt assertion from device. This commit provides a way to set gpio clk power gating settings in SPIO PS0/PS3 so that cr50 doesn't need longer interrupt assertion and SoC can still enter runtime s0ix with PchPmSlpS0Vm075VSupport set. BUG=:141831197 Change-Id: I33a3d5897ec40afee29759160963363c322d5ad0 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/hatch/mainboard.asl 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37865/1 diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl index dff1a75..db3c7ff 100644 --- a/src/mainboard/google/hatch/mainboard.asl +++ b/src/mainboard/google/hatch/mainboard.asl @@ -55,3 +55,17 @@ LOCL (0) } } + +Scope (\_SB.PCI0.SPI0) +{ + Method (_PS0, 0) + { + LOCL (0) + } + + Method(_PS3, 0) + { + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33a3d5897ec40afee29759160963363c322d5ad0 Gerrit-Change-Number: 37865 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security: Move TS_{START,END}_TPMINIT out of vboot
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38057 ) Change subject: security: Move TS_{START,END}_TPMINIT out of vboot ...................................................................... security: Move TS_{START,END}_TPMINIT out of vboot These are generic timestamps, and not vboot specific. Therefore, move them to `tpm_setup()`, so that these timestamps are added in all cases. (vboot timestamps should be namespaced with VBOOT anyway.) Change-Id: Ib1048f7b7a5903d186cdd750822b4bc8ea7dc665 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/security/tpm/tspi/tspi.c M src/security/vboot/vboot_logic.c 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/38057/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 5fcf92d..9ca9f98 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> +#include <timestamp.h> #if CONFIG(VBOOT) #include <vb2_api.h> #include <vb2_sha.h> @@ -127,6 +128,8 @@ { uint32_t result; + timestamp_add_now(TS_START_TPMINIT); + result = tlcl_lib_init(); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Can't initialize.\n"); @@ -174,6 +177,8 @@ result = tpm1_invoke_state_machine(); #endif + timestamp_add_now(TS_END_TPMINIT); + return tpm_setup_epilogue(result); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 1d17a17..c65ea3a 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -320,10 +320,8 @@ /* Read secdata from TPM. Initialize TPM if secdata not found. We don't * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ - timestamp_add_now(TS_START_TPMINIT); if (vboot_setup_tpm(ctx) == TPM_SUCCESS) antirollback_read_space_firmware(ctx); - timestamp_add_now(TS_END_TPMINIT); /* Enable measured boot mode */ if (CONFIG(VBOOT_MEASURED_BOOT) && -- To view, visit https://review.coreboot.org/c/coreboot/+/38057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1048f7b7a5903d186cdd750822b4bc8ea7dc665 Gerrit-Change-Number: 38057 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST-ONLY] mb/google/octopus/variants/phaser: for 5030 cpu
by Peichao Li (Code Review) 10 Jun '23

10 Jun '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38453 ) Change subject: [TEST-ONLY] mb/google/octopus/variants/phaser: for 5030 cpu ...................................................................... [TEST-ONLY] mb/google/octopus/variants/phaser: for 5030 cpu test new thermal solution BUG=None TEST=None Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I470642fe5a6aee6b37dddd748ee620c09289f327 --- M src/mainboard/google/octopus/variants/phaser/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38453/1 diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 625c2a6..2bc84aa 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -54,6 +54,9 @@ #| I2C6 | Trackpad | #| I2C7 | Touchscreen | #+-------------------+---------------------------+ + + register "tcc_offset" = "15" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/38453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I470642fe5a6aee6b37dddd748ee620c09289f327 Gerrit-Change-Number: 38453 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/f16kb/Proc/CPU: Avoid out-of-bounds read
by Name of user not set (Code Review) 10 Jun '23

10 Jun '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38466 ) Change subject: vc/amd/agesa/f16kb/Proc/CPU: Avoid out-of-bounds read ...................................................................... vc/amd/agesa/f16kb/Proc/CPU: Avoid out-of-bounds read In an edge case where the cpuF16AddingMmioMap function is called with a fully populated MmioRange array, MmioPair could be incremented to its maximum value of 11, causing an out-of-bounds read in cpuF16MmioMap.c:228 with the comparison to MmioRange[MmioPair + i]. Add logic to avoid this case, and similar as i is incremented. Change-Id: I781bee51a57602f3d73f43ad0ad8466a01ef8736 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1376955 --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c 1 file changed, 20 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38466/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c index 714f970..1023215 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c @@ -223,29 +223,36 @@ // | | // new base new limit + if (MmioPair >= (MMIO_REG_PAIR_NUM - 1)) { + IDS_HDT_CONSOLE (MAIN_FLOW, " [ERROR] Not enough MMIO register pairs to hold the request.\n"); + return AGESA_ERROR; + } MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; MmioRange[MmioPair].Modified = TRUE; - for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { - if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && - (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && - (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && - (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair + i].Attribute.MmioSecuredRange)) { - MmioRange[MmioPair].Limit = MmioRange[MmioPair + i].Limit; - MmioRange[MmioPair + i].Base = 0; - MmioRange[MmioPair + i].Limit = F16_MMIO_ALIGN; - MmioRange[MmioPair + i].Attribute.MmioReadableRange = 0; - MmioRange[MmioPair + i].Attribute.MmioWritableRange = 0; - MmioRange[MmioPair + i].Modified = TRUE; + for (i = MmioPair + 1; i < (MMIO_REG_PAIR_NUM - 1); i++) { + if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[i].Attribute.MmioPostedRange) && + (NewMmioRange.Attribute.MmioReadableRange == MmioRange[i].Attribute.MmioReadableRange) && + (NewMmioRange.Attribute.MmioWritableRange == MmioRange[i].Attribute.MmioWritableRange) && + (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[i].Attribute.MmioSecuredRange) && + (NewMmioRange.Limit >= MmioRange[i + 1].Base)) { + MmioRange[MmioPair].Limit = MmioRange[i].Limit; + MmioRange[i].Base = 0; + MmioRange[i].Limit = F16_MMIO_ALIGN; + MmioRange[i].Attribute.MmioReadableRange = 0; + MmioRange[i].Attribute.MmioWritableRange = 0; + MmioRange[i].Modified = TRUE; UnusedMmioPair++; - } else if (MmioRange[MmioPair + i].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair + i].Attribute.MmioWritableRange != 0) { + } else if (MmioRange[i].Attribute.MmioReadableRange != 0 || MmioRange[i].Attribute.MmioWritableRange != 0) { // Overlapped MMIO regions with different attributes MmioRange[MmioPair].Limit = (MmioRange[MmioPair].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair].Limit : NewMmioRange.Limit; NewMmioIncluded = TRUE; Overlap = TRUE; break; + } else if (NewMmioRange.Limit < MmioRange[i + 1].Base) { + break; } } - MmioRange[MmioPair].Limit = (MmioRange[MmioPair + i - 1].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair + i - 1].Limit : NewMmioRange.Limit; + MmioRange[MmioPair].Limit = (MmioRange[i].Limit >= NewMmioRange.Limit) ? MmioRange[i].Limit : NewMmioRange.Limit; break; } else { // Overlapped MMIO regions with different attributes -- To view, visit https://review.coreboot.org/c/coreboot/+/38466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781bee51a57602f3d73f43ad0ad8466a01ef8736 Gerrit-Change-Number: 38466 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/tables: Measure table creation times
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38316 ) Change subject: arch/x86/tables: Measure table creation times ...................................................................... arch/x86/tables: Measure table creation times Change-Id: I99382c5e10c4158a53aa30bd224f3d6bbfc3ecdf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/arch/x86/tables.c 1 file changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38316/1 diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 8ecf86d..002728e 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -23,6 +23,7 @@ #include <string.h> #include <cbmem.h> #include <smbios.h> +#include <timer.h> static unsigned long write_pirq_table(unsigned long rom_table_end) { @@ -198,20 +199,37 @@ { size_t sz; unsigned long rom_table_end = 0xf0000; + struct stopwatch sw; /* This table must be between 0x0f0000 and 0x100000 */ - if (CONFIG(GENERATE_PIRQ_TABLE)) + if (CONFIG(GENERATE_PIRQ_TABLE)) { + stopwatch_init_msecs(&sw); rom_table_end = write_pirq_table(rom_table_end); + printk(BIOS_SPEW, "write_pirq_table() took %lu ms\n", + stopwatch_duration_msecs(&sw)); + } /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ - if (CONFIG(GENERATE_MP_TABLE)) + if (CONFIG(GENERATE_MP_TABLE)) { + stopwatch_init_msecs(&sw); rom_table_end = write_mptable(rom_table_end); + printk(BIOS_SPEW, "write_mptable() took %lu ms\n", + stopwatch_duration_msecs(&sw)); + } - if (CONFIG(HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) { + stopwatch_init_msecs(&sw); rom_table_end = write_acpi_table(rom_table_end); + printk(BIOS_SPEW, "write_acpi_table() took %lu ms\n", + stopwatch_duration_msecs(&sw)); + } - if (CONFIG(GENERATE_SMBIOS_TABLES)) + if (CONFIG(GENERATE_SMBIOS_TABLES)) { + stopwatch_init_msecs(&sw); rom_table_end = write_smbios_table(rom_table_end); + printk(BIOS_SPEW, "write_smbios_table() took %lu ms\n", + stopwatch_duration_msecs(&sw)); + } sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); -- To view, visit https://review.coreboot.org/c/coreboot/+/38316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99382c5e10c4158a53aa30bd224f3d6bbfc3ecdf Gerrit-Change-Number: 38316 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Clean up systemagent.asl code
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38478 ) Change subject: soc/intel/skylake: Clean up systemagent.asl code ...................................................................... soc/intel/skylake: Clean up systemagent.asl code This patch performs below operations 1. Remove unused ICH memory reference. 2. Update 64 bit SA DRAM bit fields as per SKL EDS. 3. Move pci_irqs.asl from SA to PCH as applicable. 4. Add _SEG/_UID name variables. 5. Reserve TPM area as applicable. TEST=Build and boot EVE and Soraka to OS. Change-Id: I44ce4866a83df40c38b69b07a71db3b81bca3981 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/systemagent.asl 2 files changed, 18 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38478/1 diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..ce1619a 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -23,6 +23,9 @@ #include <soc/gpe.h> #include <soc/pcr_ids.h> +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + /* GPIO Controller */ #include "gpio.asl" diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 89380aa..34922ac 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -17,8 +17,10 @@ #include <soc/iomap.h> -Name (_HID, EISAID ("PNP0A08")) /* PCIe */ -Name (_CID, EISAID ("PNP0A03")) /* PCI */ +Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID +Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID +Name (_SEG, Zero) // _SEG: PCI Segment +Name (_UID, Zero) // _UID: Unique ID Device (MCHC) { @@ -30,26 +32,27 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */ Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */ Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + , 25, + PXBR, 11, /* PCI Express BAR [38:28] */ Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */ Offset (0x70), /* ME Base Address */ MEBA, 64, + Offset (0xa0), TOM, 64, /* Top of Used Memory */ TUUD, 64, /* Top of Upper Used Memory */ @@ -182,12 +185,12 @@ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, 0x00000000, PCH_PRESERVED_BASE_SIZE) - /* TPM Area (0xfed40000-0xfed44fff) */ + /* TPM Area (0xfed40000-0xfed47fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000) -}) + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) + }) /* Find PCI resource area in MCRS */ CreateDwordField (MCRS, PM01._MIN, PMIN) @@ -244,7 +247,7 @@ /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 28, Local0) Return (Local0) } @@ -292,19 +295,9 @@ */ Memory32Fixed (ReadWrite, 0, 0, PCIX) - /* MISC ICH TTT base address reserved for the - * TxT module use. - */ - Memory32Fixed (ReadWrite, 0xFED20000, 0x20000) - /* VTD engine memory range. */ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - /* MISC ICH. Check if the hard code meets the - * real configuration. - */ - Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM) - /* FLASH range */ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) @@ -336,6 +329,3 @@ Return (BUF0) } } - -/* PCI IRQ assignment */ -#include "pci_irqs.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/38478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ce4866a83df40c38b69b07a71db3b81bca3981 Gerrit-Change-Number: 38478 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add proper Kconfig for chrome ec support
by Maulik V Vaghela (Code Review) 10 Jun '23

10 Jun '23

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38517 ) Change subject: mb/intel/jasperlake_rvp: Add proper Kconfig for chrome ec support ...................................................................... mb/intel/jasperlake_rvp: Add proper Kconfig for chrome ec support Jasperlake rvp external ec board can use chromeos-ec, so adding config option to select chromeos ec and TPM (when board also supports TPM2) BUG=NONE BRANCH=None TEST=Jasperlake RVP and Jasperlake ext ec board builds fine Change-Id: I0ca74f0beb7b31ba4b1915ef21773a4a1b4327b3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/chromeos.c 2 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/38517/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 97b038e..5660e52 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -31,6 +31,28 @@ string default "Intel_jasperlake_rvp" +config JSL_EXTERNAL_EC + bool "JSL External EC" + default y if BOARD_INTEL_JASPERLAKE_RVP_EXT_EC + default n + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_SWITCHES + +config JSL_INTEL_EC + bool "Internal EC" + default y if BOARD_INTEL_JASPERLAKE_RVP + default n + select MAINBOARD_USES_IFD_EC_REGION + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config JSL_HAS_TPM + bool "JSL TPM2 support" + default y if BOARD_INTEL_JASPERLAKE_RVP_EXT_EC + default n + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + config MAX_CPUS int default 8 @@ -44,8 +66,8 @@ default 512 config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA + select VBOOT_LID_SWITCH if !EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA if !JSL_HAS_TPM config UART_FOR_CONSOLE int diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 372f6ce..4b589f0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -30,6 +30,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) int get_lid_switch(void) { /* Lid always open */ @@ -40,6 +41,7 @@ { return 0; } +#endif int get_write_protect_state(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca74f0beb7b31ba4b1915ef21773a4a1b4327b3 Gerrit-Change-Number: 38517 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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