Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39969 )
Change subject: nb/intel/sandybridge: Read spds only once if measured boot is enabled
......................................................................
nb/intel/sandybridge: Read spds only once if measured boot is enabled
Without considering s3 resume, spd may be used various times depending
on various condition. If spd is stored in CBFS and read various times,
PCR value may become inconsistent.
As mentioned in CB:39906, in order to avoid this, we could read spd
exactly once, and use the data read out various times, when measured
boot is enabled.
Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M src/northbridge/intel/sandybridge/raminit.c
1 file changed, 27 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39969/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b096a11..f3c81a6 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -98,6 +98,17 @@
}
}
+static bool spd_is_available(const spd_raw_data spds[], size_t num_spd)
+{
+ /* An available spd should at least have an non-zero id */
+ size_t i, j, sum = 0;
+ for (i = 0; i < num_spd; i++) {
+ for (j = 117; j < 128; j++)
+ sum += spds[i][j];
+ }
+ return (sum > 0);
+}
+
static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
{
int dimms = 0, ch_dimms;
@@ -222,6 +233,8 @@
struct region_device rdev;
ramctr_timing *ctrl_cached = NULL;
+ if (CONFIG(TPM_MEASURED_BOOT))
+ memset(spds, 0, sizeof(spds));
MCHBAR32(SAPMCTL) |= 1;
/* Wait for ME to be ready */
@@ -271,8 +284,14 @@
/* Verify MRC cache for fast boot */
if (!s3resume && ctrl_cached) {
/* Load SPD unique information data. */
- memset(spds, 0, sizeof(spds));
- mainboard_get_spd(spds, 1);
+ if (CONFIG(TPM_MEASURED_BOOT)) {
+ /* if CONFIG(TPM_MEASURED_BOOT),
+ we manage to get spds only ONCE */
+ mainboard_get_spd(spds, 0);
+ } else {
+ memset(spds, 0, sizeof(spds));
+ mainboard_get_spd(spds, 1);
+ }
/* check SPD CRC16 to make sure the DIMMs haven't been replaced */
fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached);
@@ -307,8 +326,12 @@
ctrl.cpu = cpuid;
/* Get DDR3 SPD data */
- memset(spds, 0, sizeof(spds));
- mainboard_get_spd(spds, 0);
+ if (!CONFIG(TPM_MEASURED_BOOT) || !spd_is_available(spds, 4)) {
+ /* without CONFIG(TPM_MEASURED_BOOT), the previous read may
+ only contains id, so read it again */
+ memset(spds, 0, sizeof(spds));
+ mainboard_get_spd(spds, 0);
+ }
dram_find_spds_ddr3(spds, &ctrl);
err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233
Gerrit-Change-Number: 39969
Gerrit-PatchSet: 1
Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org>
Gerrit-MessageType: newchange
Branden Waldner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35530 )
Change subject: mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B
......................................................................
mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B
Squash add Asus P2-99 as clone of Asus P2B and convert clone to variant
Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8
---
M src/mainboard/asus/p2b/Kconfig
M src/mainboard/asus/p2b/Kconfig.name
2 files changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35530/1
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
index f34b4dd..0c77779 100644
--- a/src/mainboard/asus/p2b/Kconfig
+++ b/src/mainboard/asus/p2b/Kconfig
@@ -12,7 +12,7 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
-if BOARD_ASUS_P2B
+if BOARD_ASUS_P2B || BOARD_ASUS_P2_99
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -28,12 +28,18 @@
string
default asus/p2b
+config VARIANT_DIR
+ string
+ default "p2-99" if BOARD_ASUS_P2_99
+ default "p2b" if BOARD_ASUS_P2B
+
config MAINBOARD_PART_NUMBER
string
+ default "P2-99" if BOARD_ASUS_P2_99
default "P2B"
config IRQ_SLOT_COUNT
int
default 6
-endif # BOARD_ASUS_P2B
+endif # BOARD_ASUS_P2B || BOARD_ASUS_P2_99
diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name
index 60d6028..a299a35 100644
--- a/src/mainboard/asus/p2b/Kconfig.name
+++ b/src/mainboard/asus/p2b/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_ASUS_P2B
bool "P2B"
+
+config BOARD_ASUS_P2_99
+ bool "P2-99"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8
Gerrit-Change-Number: 35530
Gerrit-PatchSet: 1
Gerrit-Owner: Branden Waldner <scruffy99(a)gmail.com>
Gerrit-MessageType: newchange
Hello Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/41553
to review the following change.
Change subject: device/pci: Don't enabled unassigned resources
......................................................................
device/pci: Don't enabled unassigned resources
We only have a single bit in the PCI_COMMAND register to enable
or disable resources of one type. If any resource of a type is
unassigned, we have to disable all of them.
Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/pci_device.c
1 file changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/41553/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 5afbfa9..8df44df 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -506,7 +506,8 @@
}
}
-static void pci_set_resource(struct device *dev, struct resource *resource)
+static void pci_set_resource(struct device *const dev, struct resource *const resource,
+ uint16_t *const command_mask)
{
/* Make certain the resource has actually been assigned a value. */
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
@@ -518,6 +519,11 @@
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
"assigned\n", dev_path(dev), resource->index,
resource_type(resource), resource->size);
+ /* We'll have to disable all resources of this type. */
+ if (resource->flags & IORESOURCE_MEM)
+ *command_mask &= ~PCI_COMMAND_MEMORY;
+ if (resource->flags & IORESOURCE_IO)
+ *command_mask &= ~PCI_COMMAND_IO;
return;
}
}
@@ -561,12 +567,16 @@
void pci_dev_set_resources(struct device *dev)
{
+ uint16_t command_mask = 0xffff;
struct resource *res;
struct bus *bus;
u8 line;
for (res = dev->resource_list; res; res = res->next)
- pci_set_resource(dev, res);
+ pci_set_resource(dev, res, &command_mask);
+ /* If there are unassigned resources, we might
+ have to disable others of the same type. */
+ dev->command &= command_mask;
for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children)
--
To view, visit https://review.coreboot.org/c/coreboot/+/41553
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e
Gerrit-Change-Number: 41553
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange