coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: [WIP]framebuffer_info: Add new method to specify an exact pixel format
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40798 ) Change subject: [WIP]framebuffer_info: Add new method to specify an exact pixel format ...................................................................... [WIP]framebuffer_info: Add new method to specify an exact pixel format Add an enum for framebuffer pixel formats. This allows to get rid of the imprecise BPP argument used for now. Add a test pattern generator to easily test the framebuffer format. Tested on qemu cirrus and bochs VGA. Change-Id: Ice6f3fa73d5d40e5e35073b85c53a76e35cc93ad Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/include/framebuffer_info.h M src/lib/framebuffer_info.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/soc/nvidia/tegra124/display.c 9 files changed, 162 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/40798/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 951062c..7e3a60c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -467,6 +467,16 @@ image in the 'General' section or add it manually to CBFS, using, for example, cbfstool. +config FRAMEBUFFER_PATTERN + prompt "Show test pattern on screen" + bool + depends on LINEAR_FRAMEBUFFER + help + This option shows a red, green, blue, white test pattern on the screen + from the left to the right. + + Can be used for framebuffer debugging. + config LINEAR_FRAMEBUFFER_MAX_WIDTH int "Maximum width in pixels" depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index ad50a0b..bacc6c0 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -102,7 +102,7 @@ outb(0x20, 0x3c0); /* disable blanking */ /* Advertise new mode */ - fb_add_framebuffer_info(addr, width, height, 32, 1); + fb_add_framebuffer_info_pf(addr, width, height, PF_32BPP_XRGB8, 1); } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index bb24e77..d920c89 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -311,7 +311,7 @@ vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - fb_add_framebuffer_info(addr, width, height, 32, 8); + fb_add_framebuffer_info_pf(addr, width, height, PF_32BPP_XRGB8, 8); } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index 6b0d647..593e2d0 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -22,10 +22,10 @@ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - fb_add_framebuffer_info(vbt_gop->FrameBufferBase, + fb_add_framebuffer_info_pf(vbt_gop->FrameBufferBase, vbt_gop->GraphicsMode.HorizontalResolution, vbt_gop->GraphicsMode.VerticalResolution, - 32, + PF_32BPP_BGRX8, 64); } diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index b4bdad6..8c34d56 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -24,6 +24,22 @@ uint32_t y_resolution, uint8_t bits_per_pixel, uint32_t row_alignment); +enum fb_pixelformat { + PF_UNKNOWN = 0, + PF_16BPP_B5G6R5, + PF_24BPP_RGB8, + PF_24BPP_BGR8, + PF_32BPP_XRGB8, + PF_32BPP_XBGR8, + PF_32BPP_BGRX8, + PF_32BPP_RGBX8, +}; + +struct fb_info *fb_add_framebuffer_info_pf(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, enum fb_pixelformat pf, + uint32_t row_alignment); + + void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation); diff --git a/src/lib/framebuffer_info.c b/src/lib/framebuffer_info.c index b8a7bae..18a2e0b 100644 --- a/src/lib/framebuffer_info.c +++ b/src/lib/framebuffer_info.c @@ -51,6 +51,71 @@ return ret; } +static void fb_set_pixel(struct lb_framebuffer *fb, uint32_t x, uint32_t y, + uint8_t r, uint8_t g, uint8_t b) +{ + uint8_t *fb_ptr = (uint8_t *)(uintptr_t)fb->physical_address; + fb_ptr += fb->bytes_per_line * y; + fb_ptr += (fb->bits_per_pixel/8) * x; + uint32_t *tmp; + + if (fb->bits_per_pixel > 32) + return; + + if (fb->red_mask_size < sizeof(r) * 8) + r >>= sizeof(r) * 8 - fb->red_mask_size; + + if (fb->green_mask_size < sizeof(g) * 8) + g >>= sizeof(g) * 8 - fb->green_mask_size; + + if (fb->blue_mask_size < sizeof(b) * 8) + b >>= sizeof(b) * 8 - fb->blue_mask_size; + + tmp = (uint32_t *)fb_ptr; + for (uint8_t i = 0; i < sizeof(*tmp) * 8; i++) { + if (i >= fb->red_mask_pos && i < (fb->red_mask_pos + fb->red_mask_size)) { + if (r & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + r >>= 1; + } + if (i >= fb->green_mask_pos && i < (fb->green_mask_pos + fb->green_mask_size)) { + if (g & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + g >>= 1; + } + if (i >= fb->blue_mask_pos && i < (fb->blue_mask_pos + fb->blue_mask_size)) { + if (b & 1) + *tmp |= 1 << i; + else + *tmp &= ~(1 << i); + b >>= 1; + } + } +} + +/* Generate a red, green, blue, white test pattern from the left to the right */ +static void set_test_pattern(struct lb_framebuffer *fb) +{ + for (int y = fb->y_resolution / 4; y < fb->y_resolution / 4 * 3; y++) { + for (int x = 0; x < fb->x_resolution; x++) { + if (x < fb->x_resolution / 4) + fb_set_pixel(fb, x, y, 0xff, 0, 0); + else if ((x >= fb->x_resolution / 4) && + (x < fb->x_resolution / 2)) + fb_set_pixel(fb, x, y, 0, 0xff, 0); + else if ((x >= fb->x_resolution / 2) && + (x < fb->x_resolution / 4 * 3)) + fb_set_pixel(fb, x, y, 0, 0, 0xff); + else + fb_set_pixel(fb, x, y, 0xff, 0xff, 0xff); + } + } +} + /* * Fills a provided framebuffer info struct and adds it to the internal list if it's * valid. Returns NULL on error. @@ -131,6 +196,9 @@ { struct fb_info *info = NULL; + printk(BIOS_WARNING, "%s: The use of this function is deprecated." + "Please provide a meaningful pixel format.\n", __func__); + switch (bits_per_pixel) { case 32: case 24: /* FIXME: 24 BPP might be RGB8 or XRGB8 */ @@ -154,6 +222,65 @@ return info; } +struct fb_info *fb_add_framebuffer_info_pf(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, enum fb_pixelformat pf, + uint32_t row_alignment) +{ + struct fb_info *info = NULL; + + switch (pf) { + case PF_32BPP_XBGR8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 24, 8, 0, + 8, 8, 8, 16, 8); + break; + case PF_32BPP_XRGB8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 24, 8, 16, + 8, 8, 8, 0, 8); + break; + case PF_32BPP_BGRX8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 0, 8, 8, + 8, 16, 8, 24, 8); + break; + case PF_32BPP_RGBX8: + /* packed into 4-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 32, row_alignment, 0, 8, 24, + 8, 16, 8, 0, 8); + break; + case PF_24BPP_RGB8: + /* packed into 3-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 24, row_alignment, 0, 0, 16, + 8, 8, 8, 0, 8); + break; + case PF_24BPP_BGR8: + /* packed into 3-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 24, row_alignment, 0, 0, 0, + 8, 8, 8, 16, 8); + break; + case PF_16BPP_B5G6R5: + /* packed into 2-byte words */ + info = fb_add_framebuffer_info_ex(fb_addr, x_resolution, y_resolution, + 16, row_alignment, 0, 0, 11, + 5, 5, 6, 0, 5); + break; + default: + printk(BIOS_ERR, "%s: unsupported pixel format %d\n", __func__, pf); + } + if (!info) { + printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__); + } + return info; + +} + void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation) { if (!info) @@ -191,6 +318,8 @@ unsigned int depth = framebuffer->bits_per_pixel; //FIXME: Temporary cache the bootsplash outside of this loop set_bootsplash(fb_ptr, width, height, depth); + } else if (CONFIG(FRAMEBUFFER_PATTERN)) { + set_test_pattern(framebuffer); } } diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 7a51c7e..8f5f734 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -255,7 +255,7 @@ sdmmc_vdd(); - fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 16, 0); + fb_add_framebuffer_info_pf((uintptr_t)fb_addr, 1366, 768, PF_16BPP_B5G6R5, 0); lcd_vdd(); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1d60e3b..b5dd35f 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -394,7 +394,7 @@ sdmmc_vdd(); - fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 16, 0); + fb_add_framebuffer_info_pf((uintptr_t)fb_addr, 1366, 768, PF_16BPP_B5G6R5, 0); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index c64d19d..dd3a1ce 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -314,7 +314,7 @@ /* tell depthcharge ... */ - fb_add_framebuffer_info((uintptr_t)(framebuffer_base_mb*MiB), + fb_add_framebuffer_info_pf((uintptr_t)(framebuffer_base_mb*MiB), config->xres, config->yres, config->framebuffer_bits_per_pixel, -- To view, visit https://review.coreboot.org/c/coreboot/+/40798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f3fa73d5d40e5e35073b85c53a76e35cc93ad Gerrit-Change-Number: 40798 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Hello Usha P, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40379 to review the following change. Change subject: soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH ...................................................................... soc/intel/common/block/systemagent: Add choice option for PCIEX_LENGTH This patch adds choice option for PCIEX_LENGTH related Kconfig to avoid multiple selection from SoC Kconfig. Change-Id: Icb61e9a0263c058726cc07442af1985a96bf37c2 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/40379/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6dd1f3b..ea75d5b 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -18,14 +18,23 @@ help This option allows you to select length of PCIEX region. +choice + prompt "Length of PCI Express Base Address Region" + default PCIEX_LENGTH_256MB + help + This is to provide new kconfig option that can be used to + select PCI Express Base Address Length. + config PCIEX_LENGTH_256MB - bool + bool "256 MiB" config PCIEX_LENGTH_128MB - bool + bool "128 MiB" config PCIEX_LENGTH_64MB - bool + bool "64 MiB" + +endchoice config SA_ENABLE_IMR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/40379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb61e9a0263c058726cc07442af1985a96bf37c2 Gerrit-Change-Number: 40379 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

10 20

Change in coreboot[master]: soc/intel/tgl: Enable Tracehub (not to be merged)
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42397 ) Change subject: soc/intel/tgl: Enable Tracehub (not to be merged) ...................................................................... soc/intel/tgl: Enable Tracehub (not to be merged) Change-Id: I288c17c0a3258cd506cac23014aac5e7520143b2 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42397/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b9dbec8..7450c34 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -80,14 +80,19 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; + unsigned int *tracehub_mem; struct device *dev; struct soc_intel_tigerlake_config *config; config = config_of_soc(); + tracehub_mem = malloc(4*1024*sizeof(uint32_t)); + /* Parse device tree and enable/disable Serial I/O devices */ parse_devicetree(params); + params->TraceHubMemBase = (UINT32) tracehub_mem; + /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b58952f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -18,6 +18,9 @@ unsigned int i; uint32_t mask = 0; const struct device *dev; + //uint32_t *tracehub_mem; + + //tracehub_mem = malloc(4*1024*sizeof(uint32_t)); dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) { @@ -196,6 +199,16 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + //m_cfg->TraceHubMemBase = tracehub_mem; + m_cfg->DciEn = 1; + m_cfg->DciDbcMode = 0; + m_cfg->CpuTraceHubMode = 2; + m_cfg->CpuTraceHubMemReg0Size = 2; + m_cfg->CpuTraceHubMemReg1Size = 2; + m_cfg->PchTraceHubMode = 2; + m_cfg->PchTraceHubMemReg0Size = 2; + m_cfg->PchTraceHubMemReg1Size = 2; + m_cfg->PlatformDebugConsent = 2; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I288c17c0a3258cd506cac23014aac5e7520143b2 Gerrit-Change-Number: 42397 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/google/hatch: Make Nightfury variant alphabettically sorted
by Edward O'Callaghan (Code Review) 10 Jun '23

10 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40400 ) Change subject: mb/google/hatch: Make Nightfury variant alphabettically sorted ...................................................................... mb/google/hatch: Make Nightfury variant alphabettically sorted Change-Id: I21a710ee0df45188f1f43aad61967069faf88fdb Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40400/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2419722..6eff9070 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -103,8 +103,8 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU - default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY + default "Palkia" if BOARD_GOOGLE_PALKIA default "Puff" if BOARD_GOOGLE_PUFF default "Kaisa" if BOARD_GOOGLE_KAISA default "Stryke" if BOARD_GOOGLE_STRYKE @@ -131,8 +131,8 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU - default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY + default "palkia" if BOARD_GOOGLE_PALKIA default "puff" if BOARD_GOOGLE_PUFF default "kaisa" if BOARD_GOOGLE_KAISA default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ce34211..f3f944f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -60,6 +60,12 @@ select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PALKIA bool "-> Palkia" select BOARD_GOOGLE_BASEBOARD_HATCH @@ -68,12 +74,6 @@ select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 -config BOARD_GOOGLE_NIGHTFURY - bool "-> Nightfury" - select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP - select BOARD_ROMSIZE_KB_16384 - config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/40400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a710ee0df45188f1f43aad61967069faf88fdb Gerrit-Change-Number: 40400 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36564 ) Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ...................................................................... [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work? TEST: does it boot? is it faster? Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/1 diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889..ed89894 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -39,7 +39,7 @@ #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_DCACHE_ROMSTAGE_SIZE) #include EARLY_MEMLAYOUT #elif ENV_VERSTAGE diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e..fdb5ddc 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,9 +23,17 @@ .set ap_sipi_vector_in_rom, 0xff #endif -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_ROMSTAGE_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if (CACHE_AS_RAM_BASE & (CACHE_AS_RAM_SIZE - 1)) +#error "CONFIG_DCACHE_RAM_BASE is not aligned!" +#endif + +#if ((CACHE_AS_RAM_SIZE & (CACHE_AS_RAM_SIZE - 1)) != 0) +#error "Cache-as-Ram size must be a power of 2!" +#endif + #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0..5f9eb9c 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -15,6 +15,7 @@ select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select NO_XIP_EARLY_STAGES # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -25,7 +26,7 @@ config DCACHE_RAM_BASE hex - default 0xfefc0000 + default 0xfef0000 config DCACHE_RAM_SIZE hex @@ -35,4 +36,12 @@ hex default 0x2000 +config DCACHE_ROMSTAGE_SIZE + hex + default 0xc000 + +config ROMSTAGE_ADRR + hex + default 0xfef4000 + endif # CPU_INTEL_SOCKET_MPGA604 -- To view, visit https://review.coreboot.org/c/coreboot/+/36564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Gerrit-Change-Number: 36564 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: msrtool: Fix enum type declaration
by Peter Lemenkov (Code Review) 10 Jun '23

10 Jun '23

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39162 ) Change subject: msrtool: Fix enum type declaration ...................................................................... msrtool: Fix enum type declaration This patch fixes compilation and linking with GCC 10: * https://kojipkgs.fedoraproject.org//work/tasks/3541/41983541/build.log ``` gcc -o msrtool msrtool.o msrutils.o sys.o linux.o darwin.o freebsd.o geodegx2.o geodelx.o cs5536.o k8.o via_c7.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_pentium_d.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o -Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -L/lib64 -lpci /usr/bin/ld: msrutils.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:50: multiple definition of `PresentTypes'; msrtool.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:50: first defined here /usr/bin/ld: msrutils.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:40: multiple definition of `MsrTypes'; msrtool.o:/builddir/build/BUILD/coreboot-4.10/util/msrtool/msrtool.h:40: first defined here ``` Look at this expression: enum { ... } name; It declares a variable with type of anonymous enumeration. Before GCC 10 it wasn't an issue since compiler defines -fcommon. With GCC 10 this declaration is no longer permitted - see the following link for further details: * https://gcc.gnu.org/gcc-10/porting_to.html#common * https://wiki.gentoo.org/wiki/Gcc_10_porting_notes/fno_common Let's remove unnecessary variable declaration. Change-Id: Ie154375ad6e3c1845f7937dac0121f3b63b6dd63 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M util/msrtool/msrtool.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39162/1 diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 8cba4c7..192ebf2 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -32,14 +32,14 @@ #define HEXCHARS "0123456789abcdefABCDEF" -enum { +enum MsrTypes { MSRTYPE_RDONLY, MSRTYPE_RDWR, MSRTYPE_WRONLY, MSRTYPE_EOT -} MsrTypes; +}; -enum { +enum PresentTypes { PRESENT_RSVD, PRESENT_DEC, PRESENT_BIN, @@ -47,7 +47,7 @@ PRESENT_HEX, PRESENT_HEXDEC, PRESENT_STR, -} PresentTypes; +}; struct msr { uint32_t hi; -- To view, visit https://review.coreboot.org/c/coreboot/+/39162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie154375ad6e3c1845f7937dac0121f3b63b6dd63 Gerrit-Change-Number: 39162 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Michael Niewöhner, Duncan Laurie, David Wu, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36328 to review the following change. Change subject: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues ...................................................................... [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues To get some discussion started, list some heavy issues with FSP(-S). I've copy pasted some things together, and added a few words on top and bottom. Not sure yet, where this should lead. To convince Intel to contribute open-source code on their own, we might want to add a list of initialization steps, that should be open. Feel free to amend this commit in any way :) Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A Documentation/fsp/fsp-s_discussion.md 1 file changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36328/1 diff --git a/Documentation/fsp/fsp-s_discussion.md b/Documentation/fsp/fsp-s_discussion.md new file mode 100644 index 0000000..7ac649a --- /dev/null +++ b/Documentation/fsp/fsp-s_discussion.md @@ -0,0 +1,165 @@ +Introduction +============ + +*FSP* is an ABI that allows silicon vendors to provide pre-compiled +binaries of their silicon-initialization code for the integration +into firmware frameworks such as coreboot. Current, 2.x versions +of *FSP* describe three binaries with rough responsibilities: + +* `FSP-T`: Sets up a temporary RAM environment (usually some sort + of Cache as RAM, CAR) among other things. + +* `FSP-M`: Initializes the memory (DRAM) controller, among other + things. + +* `FSP-S`: Performs various silicon-initialization steps left. + +However, what operations these binaries perform exactly and what +operations are left to the firmware framework, is neither specified +nor documented. + +Historically, all these responsibilities were left to coreboot. +Later, pre-compiled reference code for the memory-controller +initialization was introduced, then for other silicon init, and +finally there are attempts to replace coreboot's CAR setup with +FSP-T. + +While the FSP-M integration saves coreboot developers time, because +of the complex nature of the memory-controller initialization, the +integration of FSP-S turns out to be harder than implementing the +necessary code natively in coreboot. We'll discuss why that is the +case and provide an incomplete list of issues with current FSP-S +binaries. + + +Bug Fixing +---------- + +Many companies rely on the pre-built FSP binaries. Yet, there is +no common procedure to get bugs fixed or even acknowledged. This +leads to an increase of workarounds in firmware frameworks, +especially for older hardware generations. + + +Lack of Documentation +--------------------- + +Many of the initialization steps performed by FSP-S are merely +translating mainboard-specific configuration into register settings. +This is reflected by a list of hundreds of configuration options of +FSP-S. While these steps are quite simple, the additional translation +from FSP options to register values heavily increases the integration +costs. Not only are the register settings usually much better documented +than their FSP counterparts, but FSP also uses different terms so that +the existing hardware documentation often can't assist developers when +dealing with FSP. + +FSP-S also performs locking of several registers so that they can't +be written anymore afterwards. It is not documented what locks are +set by FSP. This creates heavy security issues for multiple reasons: + +* One either has to assume that FSP doesn't perform any locking + and do it redundantly in the firmware framework, or expensively + test what is locked and keep doing so for every new FSP revision. + +* Some registers may be locked before they are configured in a + secure manner. This may result in workarounds in the firmware + framework to configure things early. Sometimes it's even + impossible to do so, because relevant information isn't + available yet. + +This shows that no matter the many options that are implemented in +FSP-S, there will always be things that must be controlled by the +firmware framework. Locking should either be a separate, last step +in FSP, or be left entirely to the firmware framework. And most of +all, the locking has to be documented. + + +Arbitrary Interface Changes +--------------------------- + +Within coreboot, we try to keep code-compatibility with older hardware +generations. The FSP ABI isn't stable, however. Even when the hardware +doesn't change between minor platform updates, the configuration +settings of FSP are sometimes adapted without backwards compatibility +in mind. This increases costs, just to translate configuration data +from one representation to another only to let FSP translate it again. +In such cases, directly configuring registers from coreboot, would +save two layers of indirection. + +Another problem is the disappearance of options in newer FSP releases. +See [SpiFlashCfgLockDown UPD vanished after KBL] +(https://github.com/IntelFsp/FSP/issues/25), for instance. Current +coreboot code seems to still rely on this option. It boots, though, +only security assumptions are broken. Which again shows, locking +shouldn't be part of FSP, or at least optional. + + +FSP Switches SAI +---------------- + +A problem that multiplies with the lack of documentation is that FSP-S +switches to `POSTBOOT_SAI` on newer platforms. While it probably tries +to achieve the opposite, this undermines firmware quality and security. + +* In some firmware frameworks FSP may run long before End-of-Post, this + means most of the framework runs with `POSTBOOT_SAI`. + +* In the EDS, implications of the SAI switch are _not_ documented. + Virtually for every register, it is unknown if it is still accessible + after the SAI switch. This seems to be a problem for developers both + inside and outside of Intel. + +* The SAI switch seems to force the firmware framework to do some things + in SMM. However, the use of SMM as a more privileged execution mode is + generally discouraged. This means FSP forces firmware development to + go backwards. + +Especially the lack of documentation leads to many bugs in firmware. +Even Intel developers working on coreboot don't seem to know the +implications of the SAI switch or lack the resources to re-evaluate +all code wrt. the SAI switch. + + +FSP Creates Legal Uncertainty +----------------------------- + +Many companies sell coreboot together with FSP as part of their products. +Especially, the function pointers to GPL code that were introduced with +FSP 2.1 seem unprecedented. However, they could be compared with runtime +linking which seems troubling. + + +Mitigations +----------- + +None of the listed issues would exist if FSP were open-source and the +initialization steps could be integrated into coreboot, like they were +before. An open-source approach would not only cut costs heavily but +might also decrease time-to-market if the whole coreboot community +could work together on new platforms. + +However, in the absence of such a firmware-development utopia, there +may be more realistic approaches. As mentioned earlier, not all of FSP +has a negative impact on development performance. FSP-M, for instance, +rarely causes trouble. And due to its complex nature, it is no surprise +if memory-controller initialization is kept secret. The configuration +done by FSP-S, on the other hand, overlaps with many of coreboot's +responsibilities. The few lines of code in FSP-S that help to get a +mainboard running, don't outweigh the damage it does. However, one +can't have the cherries without taking the whole menu, which takes +years to digest. + +One approach could be to split FSP-S further up and identify parts +that are necessarily closed source and parts that could as well be +reimplemented in coreboot. However, if parts that are left closed +source change the state of the execution environment (e.g. switch +SAI), finalize any settings or raise legal concerns, the ABI would +have to change to solve all aforementioned issues. + +Another approach could be to align older platforms with open-source +coreboot, step by step. Currently, everything from Skylake on relies +on FSP-S. However, it seems Intel has already abandoned development +for this platform (while the coreboot integration was never finished). +It would seem reasonable to release abandoned code to the public, or +at least clear existing documentation for older platforms from NDAs. -- To view, visit https://review.coreboot.org/c/coreboot/+/36328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Gerrit-Change-Number: 36328 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

15 60

Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 10 Jun '23

10 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: superio/*: Standardise config state entry/exit prototype in pnp_ops.h
by Keith Hui (Code Review) 10 Jun '23

10 Jun '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40962 ) Change subject: superio/*: Standardise config state entry/exit prototype in pnp_ops.h ...................................................................... superio/*: Standardise config state entry/exit prototype in pnp_ops.h pnp_{entry,exit}_conf_state() is declared and implemented under each super I/O with not that much variation. Place them to a central location along with other pre-RAM pnp functions. This provides a standard pre-RAM PNP API, with the eventual goal of consolidating all implementations, with only one implementation per actual known config state entry/exit sequence. Remove the prototype from winbond/common. All code that use pre-RAM pnp include pnp_ops.h and all basic functions will be brought in. The correct implementation is selected at compile time via Makefile.inc. Change-Id: If4e742edb17ca73c01ff7b552e00e18acc6779dd Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/include/device/pnp_ops.h M src/superio/fintek/common/fintek.h M src/superio/winbond/common/winbond.h 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40962/1 diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 93a5dc8..f43cb33 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -10,6 +10,9 @@ #if ENV_PNP_SIMPLE_DEVICE +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + static __always_inline void pnp_write_config( pnp_devfn_t dev, uint8_t reg, uint8_t value) { diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index 81e8e67..915c148 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -9,7 +9,4 @@ void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); -void pnp_enter_conf_state(pnp_devfn_t dev); -void pnp_exit_conf_state(pnp_devfn_t dev); - #endif /* SUPERIO_FINTEK_COMMON_PRE_RAM_H */ diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 58297e5..9816db0 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -11,7 +11,4 @@ void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); void winbond_set_clksel_48(pnp_devfn_t dev); -void pnp_enter_conf_state(pnp_devfn_t dev); -void pnp_exit_conf_state(pnp_devfn_t dev); - #endif /* SUPERIO_WINBOND_COMMON_PRE_RAM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4e742edb17ca73c01ff7b552e00e18acc6779dd Gerrit-Change-Number: 40962 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: postcodes: replaced postcode values with their respective defined con...
by Sindhoor Tilak (Code Review) 10 Jun '23

10 Jun '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42503 ) Change subject: postcodes: replaced postcode values with their respective defined constants ...................................................................... postcodes: replaced postcode values with their respective defined constants - Replaced existing post_code() call values with the defined constants - Reorganized certain post_code calls to match their defines - Added few post_code() calls which were missing - Deleted certain duplicate post_code() calls Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/bootblock.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/romstage.c 48 files changed, 160 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index dcacc70..0a3698c 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -30,6 +30,8 @@ display_mtrrs(); + post_code(POST_ENTRY_RAMSTAGE); /* Load and run ramstage. */ run_ramstage(); + post_code(POST_RAMSTAGE_DIE); } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 084384e..146a3b6 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -97,12 +97,14 @@ void prepare_and_run_postcar(struct postcar_frame *pcf) { if (postcar_frame_init(pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); fill_postcar_frame(pcf); postcar_frame_common_mtrrs(pcf); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(pcf); /* We do not return here. */ } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c..8783925 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,7 +17,7 @@ unsigned long high_table_pointer; #define MAX_PIRQ_TABLE_SIZE (4 * 1024) - post_code(0x9a); + post_code(POST_TABLE_IRQ_WRITE); /* This table must be between 0x0f0000 and 0x100000 */ rom_table_end = write_pirq_routing_table(rom_table_end); @@ -49,7 +49,7 @@ unsigned long high_table_pointer; #define MAX_MP_TABLE_SIZE (4 * 1024) - post_code(0x9b); + post_code(POST_TABLE_MP_WRITE); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ rom_table_end = write_smp_table(rom_table_end); @@ -78,7 +78,7 @@ unsigned long high_table_pointer; const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB; - post_code(0x9c); + post_code(POST_TABLE_ACPI_WRITE); /* Write ACPI tables to F segment and high tables area */ diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index dd9a772..1070a9b 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <arch/bootblock.h> #include <cpu/x86/bist.h> +#include <console/console.h> static uint32_t saved_bist; @@ -22,6 +23,7 @@ bootblock_early_northbridge_init(); bootblock_early_southbridge_init(); bootblock_early_cpu_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..2983257 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -25,7 +25,7 @@ bt $12, %eax jc wait_for_sipi - post_code(0x22) + post_code(POST_CAR_INIT_IPI) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -38,6 +38,8 @@ wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr @@ -54,7 +56,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x22) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -79,7 +81,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -87,7 +88,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -95,7 +96,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -115,6 +116,7 @@ invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -123,7 +125,7 @@ shr $2, %ecx rep stosl - post_code(0x26) + post_code(POST_CAR_CACHE_EVICTION) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -142,12 +144,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -165,7 +168,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d087365..94bfeaa 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -17,7 +17,7 @@ jmp check_mtrr /* Check if CPU properly reset */ cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -30,14 +30,13 @@ bt $12, %eax jc wait_for_sipi - post_code(0x21) + post_code(POST_CAR_INIT_IPI) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(0x22) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -49,6 +48,8 @@ wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) + /* Zero out all variable range MTRRs. */ movl $MTRR_CAP_MSR, %ecx rdmsr @@ -64,6 +65,7 @@ dec %edi jnz clear_var_mtrrs + post_code(POST_CAR_VARIABLE_MTRR) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $0x80000008, %eax cpuid @@ -84,7 +86,6 @@ wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -92,7 +93,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -113,7 +114,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -170,6 +171,7 @@ andl $~2, %eax wrmsr + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -178,13 +180,13 @@ shr $2, %ecx rep stosl + post_code(POST_CAR_CACHE_EVICTION) /* enable the 'no eviction run' state */ movl $NoEvictMod_MSR, %ecx rdmsr orl $3, %eax wrmsr - post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -195,12 +197,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -218,7 +221,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..260b90e 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -12,14 +12,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_ENTRY_POST_CAR) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_CAR_CACHE_EVICTION) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e3447..8e5e6e7 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -24,6 +24,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -40,7 +41,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -48,8 +49,6 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax cpuid @@ -66,8 +65,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -75,6 +72,8 @@ xorl %edx, %edx wrmsr + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -82,7 +81,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -90,14 +89,13 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_EVICTION) /* Read then clear the CAR region. This will also fill up the cache. * IMPORTANT: The read is mandatory. */ @@ -112,7 +110,6 @@ xorl %eax, %eax rep stosl - post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -131,12 +128,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -154,7 +152,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538..74ff544 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -16,7 +16,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -33,6 +33,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +50,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -57,8 +58,6 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. */ @@ -207,15 +206,14 @@ sipi_complete: - post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr - + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -223,7 +221,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -293,7 +291,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_CAR_CACHE_EVICTION) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -333,13 +331,14 @@ wrmsr fill_cache: - post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -348,6 +347,7 @@ shr $2, %ecx rep stosl + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -365,7 +365,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x2f) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..0dec603 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -10,7 +10,7 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_ENTRY_POST_CAR) /* Disable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b56301..04abdb2 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -19,7 +19,7 @@ int wake_from_s3; enable_lapic(); - + post_code(POST_ENTRY_ROMSTAGE); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); /* Perform some early chipset initialization required @@ -56,10 +56,11 @@ params->copy_spd(params->pei_data); sdram_initialize(params->pei_data); + post_code(POST_ROM_SDRAM_INIT); timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); + post_code(POST_RAM_INIT); intel_early_me_status(); @@ -80,5 +81,5 @@ romstage_handoff_init(wake_from_s3); - post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..3675e4a 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -6,11 +6,12 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05); + post_code(POST_ENTRY_C_BOOTBLOCK); /* Halt if there was a built in self test failure */ if (bist) { console_init(); + post_code(POST_CONSOLE_READY); report_bist_failure(bist); } diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 30f9f9c..ebe5de1 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -6,12 +6,13 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* * Nothing to do here on qemu, RAM works just fine without any * initialization. */ + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also clear CAR GLOBAL */ movl $_car_region_start, %edi movl $_car_region_end, %ecx @@ -20,7 +21,7 @@ xorl %eax, %eax rep stosl - post_code(0x21) + post_code(POST_ENTRY_BOOTBLOCK_STACK) movl $_ecar_stack, %esp @@ -47,7 +48,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Never returns */ .Lhlt: diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7..f961f41 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -826,7 +826,7 @@ printk(BIOS_DEBUG, "\n"); - post_code(0x93); + post_code(POST_BOOTBLOCK_MTRR_CHECK); } static bool put_back_original_solution; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 032e15c..0ecf86a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1237,7 +1237,7 @@ max_devfn=0xff; } - post_code(0x24); + post_code(POST_PCI_SCAN_BUS); /* * Probe all devices/functions on this bus with some optimization for @@ -1317,7 +1317,7 @@ * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - post_code(0x55); + post_code(POST_PCI_SCAN_EXIT); } typedef enum { diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29..8a39a2f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,7 @@ */ bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) AMD_ENABLE_STACK @@ -42,6 +42,7 @@ test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_entry + post_code(POST_ENTRY_BOOTBLOCK_STACK) mov $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ @@ -53,7 +54,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..be45463 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -75,6 +75,7 @@ cbmem_initted = !cbmem_recovery(cb->s3resume); if (cb->s3resume && !cbmem_initted) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_EMERG, "Unable to recover CBMEM\n"); halt(); } @@ -84,6 +85,7 @@ postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); /* We do not return. */ } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..7691033 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -32,10 +32,11 @@ movd %eax, %mm1 cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Cache the rom and update the microcode */ cache_rom: + POST_CAR_CACHE_EVICTION /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -62,6 +63,7 @@ rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr + post_code(POST_CAR_MTRR_ENABLE) /* The Google FSP release for Braswell has broken microcode update code and FSP needs the installed microcode revision to be non zero. @@ -132,6 +134,7 @@ cmp $0, %eax jne halt2 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootloader stack */ movl %edx, %esp @@ -167,7 +170,7 @@ pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK) /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d..1696df0 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -123,7 +123,7 @@ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ - post_code(0x4F); + post_code(POST_FSP_FAILURE); die("Can't find the FSP!\n"); } } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dfa3258..8ae4ff7 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -50,7 +50,7 @@ * set to NULL. This indicates that the FSP code will use the UPD * region in the FSP binary. */ - post_code(POST_MEM_PREINIT_PREP_START); + post_code(POST_RAM_INIT); fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); @@ -110,7 +110,7 @@ post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); mainboard_after_memory_init(); - post_code(0x37); + post_code(POST_MAINBOARD_SOC_INIT_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); @@ -146,6 +146,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 46df1c8..b8c8c76 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -25,7 +25,7 @@ bool s3wake; struct region_device rdev; - post_code(0x32); + post_code(POST_ENTRY_ROMSTAGE); timestamp_add_now(TS_BEFORE_INITRAM); @@ -35,7 +35,7 @@ /* Perform remaining SOC initialization */ soc_pre_ram_init(params); - post_code(0x33); + post_code(POST_SOC_RAM_PREINIT); /* Check recovery and MRC cache */ params->saved_data_size = 0; @@ -100,7 +100,7 @@ .chipset_context = fih, }; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE); @@ -126,13 +126,13 @@ /* Board initialization before and after RAM is enabled */ mainboard_pre_raminit(&params); - post_code(0x31); - + post_code(POST_MEM_PREINIT_EXIT); + post_code(POST_RAM_INIT); /* Initialize memory */ raminit_common(&params); soc_after_ram_init(&params); - post_code(0x38); + } /* Initialize the power state */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389..59f84d7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -72,6 +72,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (CONFIG(HAVE_ACPI_RESUME)) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4..b357dc0 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -108,7 +108,7 @@ } } if (failures) { - post_code(0xea); + post_code(POST_RAM_TEST_FAIL); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -126,6 +126,7 @@ */ printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); if (ram_bitset_nodie(start)) + post_code(POST_RAM_FAILURE); die("DRAM ERROR"); printk(BIOS_DEBUG, "Done.\n"); } @@ -198,7 +199,7 @@ write_phys(dst, backup); if (fail) { - post_code(0xea); + post_code(POST_RAM_FAILURE); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938..7411980 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -10,8 +10,7 @@ void bootblock_mainboard_early_init(void) { - post_code(0x30); - post_code(0x31); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); gpio_100_write8(0x1, 0x98); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..6883e13 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -10,7 +10,7 @@ { u8 byte; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); /* turn on secondary smbus at b20 */ pm_write8(0x28, pm_read8(0x28) | 1); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 6b116fd..1b4cf23 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -28,10 +28,10 @@ pm_io_write8(0xd2, 0); if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); console_init(); + post_code(POST_CONSOLE_READY); } } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 8a1cc03..67eae9f 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -4,5 +4,5 @@ void board_BeforeAgesa(struct sysinfo *cb) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 22ed952..7cade85 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -37,7 +37,7 @@ i82801gx_early_init(); pineview_early_init(); - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); s3resume = southbridge_detect_s3_resume(); @@ -58,7 +58,7 @@ timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n"); - post_code(0x31); + post_code(POST_MEM_PREINIT_EXIT); mb_pirq_setup(); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 72c284f..134bce4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -391,7 +391,7 @@ void perform_raminit(int s3resume) { - post_code(0x3a); + post_code(POST_RAM_INIT); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1ec54b3..41a92c8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -335,7 +335,7 @@ devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data); - post_code(0x3a); + post_code(POST_ROM_PEI_DATA_FILL); /* Fill after mainboard_fill_pei_data as it might provide spd_data */ pei_data.dimm_channel0_disabled = @@ -364,6 +364,7 @@ pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + post_code(POST_ROM_SDRAM_INIT); /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b9841b5..0dd7204 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,7 @@ { int s3resume = 0; + post_code(POST_ENTRY_ROMSTAGE); if (MCHBAR16(SSKPD_HI) == 0xCAFE) system_reset(); @@ -55,11 +56,11 @@ elog_boot_notify(s3resume); - post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT); mainboard_early_init(s3resume); - post_code(0x39); + post_code(POST_RAM_INIT); perform_raminit(s3resume); @@ -74,9 +75,9 @@ southbridge_rcba_config(); mainboard_late_rcba_config(); - post_code(0x3d); + post_code(POST_ROM_RCBA_CONFIG); northbridge_romstage_finalize(s3resume); - post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 5c186f1..7d21cfe 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -10,7 +10,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_ENTRY_BOOTBLOCK_STACK) movl $_eearlyram_stack, %esp @@ -23,7 +23,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 83243d3..bfe395a 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -75,10 +75,10 @@ { int s3_resume; - post_code(0x40); + post_code(POST_ENTRY_ROMSTAGE); console_init(); - post_code(0x41); + post_code(POST_CONSOLE_READY); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); @@ -87,14 +87,14 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - post_code(0x43); + post_code(POST_FSP_MEMORY_INIT); fsp_memory_init(s3_resume); soc_update_mrc_cache(); memmap_stash_early_dram_usage(); - post_code(0x44); + post_code(POST_ENTRY_RAMSTAGE); run_ramstage(); - post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 4025f80..ba2fe08 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -85,7 +85,7 @@ */ sb_reset_i2c_slaves(); bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 909b847..b49b3af 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -145,11 +145,11 @@ if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); - post_code(0x47); + post_code(POST_AGESA_INIT_ENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_S3_RESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..c3baf46 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -33,10 +33,10 @@ static void agesa_call(void) { - post_code(0x37); + post_code(POST_ROM_SOC_INIT_RESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -58,6 +58,7 @@ int i; console_init(); + post_code(POST_CONSOLE_READY); soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) @@ -111,8 +112,9 @@ post_code(0x42); psp_notify_dram(); - post_code(0x43); + post_code(POST_PSP_DRAM_NOTIFY); if (cbmem_recovery(s3_resume)) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); @@ -120,8 +122,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); + post_code(POST_ENTRY_POST_CAR); if (postcar_frame_init(&pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); /* @@ -139,10 +142,10 @@ /* Cache the TSEG region */ postcar_enable_tseg_cache(&pcf); - post_code(0x45); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); - post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ } void SetMemParams(AMD_POST_PARAMS *PostParams) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e49..6e57266 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <spi-generic.h> +#include <console/console.h> static const struct pad_config tpm_spi_configs[] = { #if CONFIG(SOC_INTEL_GLK) @@ -108,4 +109,5 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 1d1bd30..a2c005c 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -167,6 +167,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8c194fc..c6e2549 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -92,6 +92,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40..2d4a033 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -34,7 +34,7 @@ { struct romstage_params rp = { 0 }; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); /* System Agent Early Initialization */ systemagent_early_init(); @@ -59,7 +59,7 @@ /* Fill in mainboard pei_date. */ mainboard_pre_raminit(&rp); - post_code(0x32); + post_code(POST_MEM_PREINIT_EXIT); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 69ed174..ae2a306 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -12,13 +12,11 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0x20) - movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ no_reset: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -31,7 +29,7 @@ wrmsr jnz clear_fixed_mtrr - post_code(0x22) + post_code(POST_CAR_FIXED_MTRR) /* Figure put how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +47,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x23) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -76,7 +74,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - post_code(0x24) + post_code(POST_CAR_MTRR_ENABLE) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) /* Configure CAR region as write-back (WB) */ @@ -153,7 +151,7 @@ .global car_init_done car_init_done: - post_code(0x29) + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -170,7 +168,7 @@ pushl %eax /* tsc[31:0] */ before_carstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry /* Never reached */ @@ -203,7 +201,7 @@ or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -213,7 +211,7 @@ cld rep stosl - post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -221,8 +219,7 @@ or $0x2, %eax wrmsr - post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #elif CONFIG(INTEL_CAR_CQOS) @@ -300,7 +297,7 @@ and %ebx, %eax wrmsr - post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -325,19 +322,19 @@ and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: + post_code(POST_CAR_CACHE_EVICTION) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr - post_code(0x26) /* Create n-way set associativity of cache */ xorl %edi, %edi @@ -427,7 +424,7 @@ xorl %edx, %edx wrmsr - post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. @@ -438,7 +435,6 @@ orl $0x02, %eax wrmsr - post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08..1eb0751 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -17,7 +17,7 @@ .global cache_as_ram cache_as_ram: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* find fsp in cbfs */ lea fsp_name, %esi @@ -70,6 +70,7 @@ cmp $0, %eax jnz .halt_forever + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ mov %edx, %esp @@ -87,6 +88,7 @@ movd %mm1, %eax push %eax + post_code(POST_ENTRY_C_BOOTBLOCK) /* We can call into C functions now */ call bootblock_c_entry diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index fc1c7c9..10484545 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -473,11 +473,12 @@ * edi: High 32-bits of timestamp */ + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ movl $_ecar_stack, %esp before_carstage: - post_code(0x2b) + post_code(POST_ENTRY_C_BOOTBLOCK) /* Get the timestamp passed in bootblock_crt0.S */ push %edi diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index efe3c10..081eb14 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -17,8 +17,8 @@ { bool s3wake; - post_code(0x20); console_init(); + post_code(POST_CONSOLE_READY); if (CONFIG(STORAGE_TEST)) { uint32_t bar; diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 6380db2..bdc2d2e 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -21,6 +21,7 @@ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 54ad85a..e0ecc03 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <intelblocks/systemagent.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <console/console.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -19,6 +20,7 @@ pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2..bcb516d 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -48,6 +48,7 @@ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 3db9ca9..c675213 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -25,6 +25,7 @@ unlock_pam_regions(); if (postcar_frame_init(&pcf, 1 * KiB)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); /* @@ -40,6 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 Gerrit-Change-Number: 42503 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 27

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020