Hello Satya Priya Kakitapalli,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39807
to review the following change.
Change subject: sc7180: Fix for hang during DMA transfer in SPI-NOR flash driver
......................................................................
sc7180: Fix for hang during DMA transfer in SPI-NOR flash driver
Transfer sequence used by SPI-Flash application present in CB/DC.
1. Assert CS through GPIO
2. Data transfer through QSPI (involves construction of command
descriptor for multiple read/write transfers)
3. De-assert CS through GPIO.
With above sequence, in DMA mode we dont have the support for read
transfers that are not preceded by write transfer in QSPI controller.
Ex: "write read read read" sequence results in hang during DMA transfer,
where as "write read write read" sequence has no issue.
As we have application controlling CS through GPIO, we are making
fragment bit "set" for all transfers, which keeps CS in asserted
state although the ideal way to operate CS is through QSPI controller.
Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7
Signed-off-by: satya priya <skakit(a)codeaurora.org>
---
M src/soc/qualcomm/sc7180/qspi.c
1 file changed, 8 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/39807/1
diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c
index 30dc1c3..8ecc07f 100644
--- a/src/soc/qualcomm/sc7180/qspi.c
+++ b/src/soc/qualcomm/sc7180/qspi.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2019-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -131,17 +131,20 @@
next->direction = MASTER_READ;
next->multi_io_mode = 0;
next->reserved1 = 0;
- next->fragment = 0;
+ /*
+ * QSPI controller doesn't support transfer starts with read segment.
+ * So to support read transfers that are not preceded by write, set
+ * transfer fragment bit = 1
+ */
+ next->fragment = 1;
next->reserved2 = 0;
next->length = 0;
next->bounce_src = 0;
next->bounce_dst = 0;
next->bounce_length = 0;
- if (current) {
+ if (current)
current->next_descriptor = (uint32_t)(uintptr_t) next;
- current->fragment = 1;
- }
return next;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7
Gerrit-Change-Number: 39807
Gerrit-PatchSet: 1
Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org>
Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com>
Gerrit-MessageType: newchange
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41069 )
Change subject: soc/amd/common/block/lpc: Add config options for eSPI
......................................................................
soc/amd/common/block/lpc: Add config options for eSPI
eSPI on Picasso is configured using the LPC bridge configuration
registers. This change enables config options to allow SoC to select
if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to
select if it wants to use eSPI instead of LPC for talking to legacy
devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI).
BUG=b:154445472
Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/amd/common/block/lpc/Kconfig
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/41069/1
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index b0d59a5..9bc9010 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -3,3 +3,18 @@
default n
help
Select this option to use the traditional LPC-ISA bridge at D14F3.
+
+config SOC_AMD_COMMON_BLOCK_HAS_ESPI
+ bool
+ default n
+ help
+ Select this option if platform supports eSPI using D14F3 configuration
+ registers.
+
+config SOC_AMD_COMMON_BLOCK_USE_ESPI
+ bool
+ depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
+ default n
+ help
+ Select this option if mainboard uses eSPI instead of LPC (if supported
+ by platform).
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Gerrit-Change-Number: 41069
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-MessageType: newchange
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40625
to look at the new patch set (#8).
Change subject: [WIP] skl: PEG for Optimus
......................................................................
[WIP] skl: PEG for Optimus
Creates PEG ACPI device for Optimus.
Optimus is not working (dGPU does not appear in the OS; perhaps an issue
with optimus_mb.asl - implementation of dGPU power functions).
Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/soc/intel/skylake/acpi/pch.asl
A src/soc/intel/skylake/acpi/peg.asl
2 files changed, 171 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/8
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd
Gerrit-Change-Number: 40625
Gerrit-PatchSet: 8
Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newpatchset
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41231 )
Change subject: LICENSES: Fix up retained copyright lines
......................................................................
LICENSES: Fix up retained copyright lines
One author put their name on a separate line from the rest of the
Copyright statement, so copy it in.
Change-Id: I041bc60079a238f59bb23556a80398052744fd5c
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M LICENSES/retained-copyrights.txt
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41231/1
diff --git a/LICENSES/retained-copyrights.txt b/LICENSES/retained-copyrights.txt
index 8fe91fa..6775d2e 100644
--- a/LICENSES/retained-copyrights.txt
+++ b/LICENSES/retained-copyrights.txt
@@ -15,7 +15,7 @@
Copyright 2018 Generated Code
Copyright 2018-present Facebook, Inc.
Copyright 2019 9Elements Agency GmbH <patrick.rudolph(a)9elements.com>
-Copyright (C) 2002
+Copyright (C) 2002 David S. Peterson. All rights reserved.
Copyright (c) 2003-2016 Cavium Inc. (support(a)cavium.com). All rights
Copyright (c) 2003-2017 Cavium Inc. (support(a)cavium.com). All rights
Copyright (c) 2004, 2008 IBM Corporation
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I041bc60079a238f59bb23556a80398052744fd5c
Gerrit-Change-Number: 41231
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange