HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel
......................................................................
Patch Set 30:
> Patch Set 30:
>
> > Patch Set 30:
> >
> > > Patch Set 30:
> > >
> > > I've populated only channel 0 with 2 DIMMs
> > > as you can see, we have the message "C1ODT: Channel 1 has one DIMM."
> > > https://pastebin.com/9pxTYPQx
> > > The board boots but this patch does not what expected
> >
> > That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1
>
> Thx,
> but in posted log we can see
> "Setting up RAM controller.
> This mainboard supports Dual Channel Operation.
> Reading SPD using i2c block operation.
> DDR II Channel 0 Socket 0: x8DDS
> DIMM 0 side 0 = 1024 MB
> DIMM 0 side 1 = 1024 MB
> Reading SPD using i2c block operation.
> DDR II Channel 0 Socket 1: x8DDS
> DIMM 1 side 0 = 1024 MB
> DIMM 1 side 1 = 1024 MB
> DDR II Channel 1 Socket 0: N/A
> DDR II Channel 1 Socket 1: N/A
> Memory will be driven at 667MT with CAS=5 clocks
> tRAS = 15 cycles"
>
> and when I check using vendor bios with only channel 0 populated (dimm0 + dimm1), the SPD are: 0x50 and 0x51.
>
> NB (using vendor bios) : this board have 2 channels and 2 DIMMs per channel
> dimm0 at 0x50
> dimm1 at 0x51
> dimm2 at 0x52
> dimm3 at 0x53
even with
if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) {
printk(BIOS_DEBUG, "C0ODT: Channel 0 has one DIMM.\n");
reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28);
MCHBAR32(C0ODT) = reg32;
}
if (!(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) {
printk(BIOS_DEBUG, "C1ODT: Channel 1 has one DIMM.\n");
reg32 = MCHBAR32(C1ODT);
reg32 &= ~(7 << 28);
MCHBAR32(C1ODT) = reg32;
}
it will send a msg that channel 1 has one dimm 😞 (however it is not!)
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel
......................................................................
Patch Set 30:
> Patch Set 30:
>
> > Patch Set 30:
> >
> > I've populated only channel 0 with 2 DIMMs
> > as you can see, we have the message "C1ODT: Channel 1 has one DIMM."
> > https://pastebin.com/9pxTYPQx
> > The board boots but this patch does not what expected
>
> That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1
Thx,
but in posted log we can see
"Setting up RAM controller.
This mainboard supports Dual Channel Operation.
Reading SPD using i2c block operation.
DDR II Channel 0 Socket 0: x8DDS
DIMM 0 side 0 = 1024 MB
DIMM 0 side 1 = 1024 MB
Reading SPD using i2c block operation.
DDR II Channel 0 Socket 1: x8DDS
DIMM 1 side 0 = 1024 MB
DIMM 1 side 1 = 1024 MB
DDR II Channel 1 Socket 0: N/A
DDR II Channel 1 Socket 1: N/A
Memory will be driven at 667MT with CAS=5 clocks
tRAS = 15 cycles"
and when I check using vendor bios with only channel 0 populated (dimm0 + dimm1), the SPD are: 0x50 and 0x51.
NB (using vendor bios) : this board have 2 channels and 2 DIMMs per channel
dimm0 at 0x50
dimm1 at 0x51
dimm2 at 0x52
dimm3 at 0x53
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
......................................................................
Patch Set 3:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39515 )
Change subject: util/inteltool: gpio: drop dummy entry
......................................................................
Patch Set 2:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39505 )
Change subject: util/inteltool: ahci: add code for dumping config and SIR registers
......................................................................
Patch Set 4:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39524 )
Change subject: util/inteltool: add code for dumping IO registers
......................................................................
Uploaded patch set 5: Patch Set 4 was rebased.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39523 )
Change subject: util/inteltool: add code for dumping APIC registers
......................................................................
Uploaded patch set 5.
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Hello build bot (Jenkins), Patrick Georgi, Patrick Rudolph, Paul Menzel, Stefan Reinauer, Angel Pons, Mimoja, Aaron Durbin, Nico Huber, Maxim Polyakov, Idwer Vollering, Christian Walter, HAOUAS Elyes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39523
to look at the new patch set (#5).
Change subject: util/inteltool: add code for dumping APIC registers
......................................................................
util/inteltool: add code for dumping APIC registers
This adds the implementation for dumping APIC registers.
Change-Id: Ic35e4d1dcb77ae2246197befb8cccc5af52d20e3
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M util/inteltool/Makefile
A util/inteltool/apic.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
4 files changed, 134 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39523/5
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