coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/i945: Program CxODT value for each channel
by HAOUAS Elyes (Code Review) 14 Mar '20

14 Mar '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Program CxODT value for each channel ...................................................................... Patch Set 30: > Patch Set 30: > > > Patch Set 30: > > > > > Patch Set 30: > > > > > > I've populated only channel 0 with 2 DIMMs > > > as you can see, we have the message "C1ODT: Channel 1 has one DIMM." > > > https://pastebin.com/9pxTYPQx > > > The board boots but this patch does not what expected > > > > That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1 > > Thx, > but in posted log we can see > "Setting up RAM controller. > This mainboard supports Dual Channel Operation. > Reading SPD using i2c block operation. > DDR II Channel 0 Socket 0: x8DDS > DIMM 0 side 0 = 1024 MB > DIMM 0 side 1 = 1024 MB > Reading SPD using i2c block operation. > DDR II Channel 0 Socket 1: x8DDS > DIMM 1 side 0 = 1024 MB > DIMM 1 side 1 = 1024 MB > DDR II Channel 1 Socket 0: N/A > DDR II Channel 1 Socket 1: N/A > Memory will be driven at 667MT with CAS=5 clocks > tRAS = 15 cycles" > > and when I check using vendor bios with only channel 0 populated (dimm0 + dimm1), the SPD are: 0x50 and 0x51. > > NB (using vendor bios) : this board have 2 channels and 2 DIMMs per channel > dimm0 at 0x50 > dimm1 at 0x51 > dimm2 at 0x52 > dimm3 at 0x53 even with if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) { printk(BIOS_DEBUG, "C0ODT: Channel 0 has one DIMM.\n"); reg32 = MCHBAR32(C0ODT); reg32 &= ~(7 << 28); MCHBAR32(C0ODT) = reg32; } if (!(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { printk(BIOS_DEBUG, "C1ODT: Channel 1 has one DIMM.\n"); reg32 = MCHBAR32(C1ODT); reg32 &= ~(7 << 28); MCHBAR32(C1ODT) = reg32; } it will send a msg that channel 1 has one dimm 😞 (however it is not!) -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Mar 2020 09:07:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgierlake: Enable ISH
by Wonkyu Kim (Code Review) 14 Mar '20

14 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39531 ) Change subject: soc/intel/tgierlake: Enable ISH ...................................................................... soc/intel/tgierlake: Enable ISH Configure ISH based on devicetree Add ISH ACPI object name for SSDT Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I07d41558eaf1f6e047e402dbbafc62d0ddfec8c0 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39531/1 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 6f6e153..dc36da3 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -71,6 +71,7 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 072c99e..208dd6f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -77,6 +77,13 @@ else m_cfg->InternalGfx = 0x1; + /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + if (!dev || !dev->enabled) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = 1; + /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; -- To view, visit https://review.coreboot.org/c/coreboot/+/39531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d41558eaf1f6e047e402dbbafc62d0ddfec8c0 Gerrit-Change-Number: 39531 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Program CxODT value for each channel
by HAOUAS Elyes (Code Review) 14 Mar '20

14 Mar '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Program CxODT value for each channel ...................................................................... Patch Set 30: > Patch Set 30: > > > Patch Set 30: > > > > I've populated only channel 0 with 2 DIMMs > > as you can see, we have the message "C1ODT: Channel 1 has one DIMM." > > https://pastebin.com/9pxTYPQx > > The board boots but this patch does not what expected > > That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1 Thx, but in posted log we can see "Setting up RAM controller. This mainboard supports Dual Channel Operation. Reading SPD using i2c block operation. DDR II Channel 0 Socket 0: x8DDS DIMM 0 side 0 = 1024 MB DIMM 0 side 1 = 1024 MB Reading SPD using i2c block operation. DDR II Channel 0 Socket 1: x8DDS DIMM 1 side 0 = 1024 MB DIMM 1 side 1 = 1024 MB DDR II Channel 1 Socket 0: N/A DDR II Channel 1 Socket 1: N/A Memory will be driven at 667MT with CAS=5 clocks tRAS = 15 cycles" and when I check using vendor bios with only channel 0 populated (dimm0 + dimm1), the SPD are: 0x50 and 0x51. NB (using vendor bios) : this board have 2 channels and 2 DIMMs per channel dimm0 at 0x50 dimm1 at 0x51 dimm2 at 0x52 dimm3 at 0x53 -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Mar 2020 06:22:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/acpi: Move ECPD under CREC
by Prashant Malani (Code Review) 13 Mar '20

13 Mar '20

Prashant Malani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39469 ) Change subject: ec/google/chromeec/acpi: Move ECPD under CREC ...................................................................... ec/google/chromeec/acpi: Move ECPD under CREC Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP device drivers can access the parent EC device to communicate with the EC. Also, update the Notify() call to reflect the new location of the ECPD device. Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2 --- M src/ec/google/chromeec/acpi/cros_ec.asl M src/ec/google/chromeec/acpi/ec.asl 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39469/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index d41071e..bcf38d2 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -60,6 +60,10 @@ Name (_DDN, "EC Base Switch Device") } #endif + +#ifdef EC_ENABLE_PD_MCU_DEVICE + #include "pd.asl" +#endif Method(_STA, 0) { Return (0xB) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index bf792d3..fa5eca6 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -344,7 +344,7 @@ Method (_Q16, 0, NotSerialized) { Store ("EC: GOT PD EVENT", Debug) - Notify (ECPD, 0x80) + Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) } #endif @@ -558,10 +558,6 @@ #include "keyboard_backlight.asl" #endif -#ifdef EC_ENABLE_PD_MCU_DEVICE - #include "pd.asl" -#endif - #ifdef EC_ENABLE_TBMC_DEVICE #include "tbmc.asl" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2 Gerrit-Change-Number: 39469 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 13 Mar '20

13 Mar '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Mar 2020 02:07:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: gpio: drop dummy entry
by Michael Niewöhner (Code Review) 13 Mar '20

13 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39515 ) Change subject: util/inteltool: gpio: drop dummy entry ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I310d75f9fdb110f7a91fef3cfc516f559f2ce2f2 Gerrit-Change-Number: 39515 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Mar 2020 23:10:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: ahci: add code for dumping config and SIR registers
by Michael Niewöhner (Code Review) 13 Mar '20

13 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39505 ) Change subject: util/inteltool: ahci: add code for dumping config and SIR registers ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If158156456235de0886501639eec8493cc057dcb Gerrit-Change-Number: 39505 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Mar 2020 23:10:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping IO registers
by Michael Niewöhner (Code Review) 13 Mar '20

13 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39524 ) Change subject: util/inteltool: add code for dumping IO registers ...................................................................... Uploaded patch set 5: Patch Set 4 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I200e7a8fb85184fc954d6ae3cd71c6b5bdcb664a Gerrit-Change-Number: 39524 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Mar 2020 22:57:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping APIC registers
by Michael Niewöhner (Code Review) 13 Mar '20

13 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39523 ) Change subject: util/inteltool: add code for dumping APIC registers ...................................................................... Uploaded patch set 5. -- To view, visit https://review.coreboot.org/c/coreboot/+/39523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic35e4d1dcb77ae2246197befb8cccc5af52d20e3 Gerrit-Change-Number: 39523 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Mar 2020 22:57:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping APIC registers
by Michael Niewöhner (Code Review) 13 Mar '20

13 Mar '20

Hello build bot (Jenkins), Patrick Georgi, Patrick Rudolph, Paul Menzel, Stefan Reinauer, Angel Pons, Mimoja, Aaron Durbin, Nico Huber, Maxim Polyakov, Idwer Vollering, Christian Walter, HAOUAS Elyes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39523 to look at the new patch set (#5). Change subject: util/inteltool: add code for dumping APIC registers ...................................................................... util/inteltool: add code for dumping APIC registers This adds the implementation for dumping APIC registers. Change-Id: Ic35e4d1dcb77ae2246197befb8cccc5af52d20e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M util/inteltool/Makefile A util/inteltool/apic.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 4 files changed, 134 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39523/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic35e4d1dcb77ae2246197befb8cccc5af52d20e3 Gerrit-Change-Number: 39523 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2020