coreboot-gerrit February 2020

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Change in coreboot[master]: security/tpm/tss: Add ClearControl Function
by Christian Walter (Code Review) 04 Feb '20

04 Feb '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38617 ) Change subject: security/tpm/tss: Add ClearControl Function ...................................................................... security/tpm/tss: Add ClearControl Function Add ClearControl Function which is needed for a follow-up patch. Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/38617/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 336935d..5237387 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -171,6 +171,11 @@ uint32_t tlcl_force_clear(void); /** + * Set Clear Control. The TPM error code is returned. + */ +uint32_t tlcl_clear_control(bool disable); + +/** * Set the bGlobalLock flag, which only a reboot can clear. The TPM error * code is returned. */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 6bc3096..49a6cea 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -170,6 +170,23 @@ return TPM_SUCCESS; } +uint32_t tlcl_clear_control(bool disable) +{ + struct tpm2_response *response; + struct tpm2_clear_control_cmd cc = { + .disable = 0, + }; + + response = tpm_process_command(TPM2_ClearControl, &cc); + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + static uint8_t tlcl_init_done; /* This function is called directly by vboot, uses vboot return types. */ diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 1530613..ade9b27 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -84,6 +84,7 @@ /* TPM command codes. */ #define TPM2_Hierarchy_Control ((TPM_CC)0x00000121) #define TPM2_Clear ((TPM_CC)0x00000126) +#define TPM2_ClearControl ((TPM_CC)0x00000127) #define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) #define TPM2_NV_Write ((TPM_CC)0x00000137) #define TPM2_NV_WriteLock ((TPM_CC)0x00000138) @@ -417,6 +418,10 @@ TPML_DIGEST_VALUES digests; }; +struct tpm2_clear_control_cmd { + TPMI_YES_NO disable; +}; + struct tpm2_hierarchy_control_cmd { TPMI_RH_ENABLES enable; TPMI_YES_NO state; -- To view, visit https://review.coreboot.org/c/coreboot/+/38617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4 Gerrit-Change-Number: 38617 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Make MP init timeout configurable
by Jonathan Zhang (Code Review) 04 Feb '20

04 Feb '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38546 ) Change subject: Make MP init timeout configurable ...................................................................... Make MP init timeout configurable The current MP init timeout is hardcoded as 1s. To support Intel Xeon scalable processor, the timeout needs to be adjusted. This patch makes MP init timeout configurable. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38546/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 76446a0..eedd2e6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -184,3 +184,9 @@ help The SoC requires different access methods for reading and writing the MSRs. Use SoC specific routines to handle the MSR access. + +config FLIGHT_PLAN_TIMEOUT_US + int + default 1000000 + help + Time-out (in micro seconds) to wait for APs to check-in diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 45776f8..e874931 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -522,7 +522,7 @@ * could take a longer time for APs to check-in as the number of APs * increases (contention for resources like UART also increases). */ - const int timeout_us = 1000000; + const int timeout_us = CONFIG_FLIGHT_PLAN_TIMEOUT_US; const int step_us = 100; int num_aps = mp_params->num_cpus - 1; struct stopwatch sw; -- To view, visit https://review.coreboot.org/c/coreboot/+/38546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e Gerrit-Change-Number: 38546 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

9 31

Change in coreboot[master]: mb/google/hatch: Enable Audio DSP oscillator qualification for S0ix
by Aamir Bohra (Code Review) 04 Feb '20

04 Feb '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38680 ) Change subject: mb/google/hatch: Enable Audio DSP oscillator qualification for S0ix ...................................................................... mb/google/hatch: Enable Audio DSP oscillator qualification for S0ix Enable Audio DSP oscillator qualification for S0ix for Helios and Kohaku. BUG=b:139481313 Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38680/1 diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 94639dc..a8ed5ef 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -20,6 +20,9 @@ # No PCIe WiFi register "PcieRpEnable[13]" = "0" + # Enable Audio DSP oscillator qualification for S0ix + register "cppmvric2_adsposcdis" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index ce87469..916d12b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -20,6 +20,9 @@ # No PCIe WiFi register "PcieRpEnable[13]" = "0" + # Enable Audio DSP oscillator qualification for S0ix + register "cppmvric2_adsposcdis" = "1" + # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6 Gerrit-Change-Number: 38680 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel: Remove duplicate CPUID entry
by Subrata Banik (Code Review) 04 Feb '20

04 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38672 ) Change subject: soc/intel: Remove duplicate CPUID entry ...................................................................... soc/intel: Remove duplicate CPUID entry This patch removes duplicate CPUID entry between KBL and CFL. CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL CPUID (0x806EA) for CFL-D0. TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with CPUID 0x806EA. Change-Id: I078dd7860891896b512967dc8dec5dd94d069193 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38672/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 67dd452..b89c3b4 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -37,7 +37,7 @@ { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, - { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, + { CPUID_KABYLAKE_Y0, "Coffeelake D0" }, { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index f3c6c7d..66a358f 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -75,7 +75,6 @@ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, - { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e0b0d8c..c0c58af 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -40,7 +40,6 @@ #define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb -#define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea #define CPUID_COFFEELAKE_B0 0x906eb #define CPUID_COFFEELAKE_P0 0x906ec -- To view, visit https://review.coreboot.org/c/coreboot/+/38672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078dd7860891896b512967dc8dec5dd94d069193 Gerrit-Change-Number: 38672 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd: unify SMBus support
by Aaron Durbin (Code Review) 04 Feb '20

04 Feb '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38616 ) Change subject: soc/amd: unify SMBus support ...................................................................... soc/amd: unify SMBus support The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- R src/soc/amd/common/block/smbus/sm.c R src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/sm.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/smbus.c 8 files changed, 2 insertions(+), 305 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38616/1 diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/common/block/smbus/sm.c similarity index 100% rename from src/soc/amd/stoneyridge/sm.c rename to src/soc/amd/common/block/smbus/sm.c diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/common/block/smbus/smbus.c similarity index 100% rename from src/soc/amd/picasso/smbus.c rename to src/soc/amd/common/block/smbus/smbus.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 7561414..acceb00 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -47,6 +47,7 @@ select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f1e10c1..680f0fa 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -41,7 +41,6 @@ romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c -romstage-y += smbus.c romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c @@ -71,8 +70,6 @@ ramstage-y += pmutil.c ramstage-y += acp.c ramstage-y += sata.c -ramstage-y += sm.c -ramstage-y += smbus.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c deleted file mode 100644 index f0ba559..0000000 --- a/src/soc/amd/picasso/sm.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus.h> -#include <device/smbus_host.h> -#include <cpu/x86/lapic.h> -#include <arch/ioapic.h> -#include <soc/southbridge.h> - -/* -* The southbridge enables all USB controllers by default in SMBUS Control. -* The southbridge enables SATA by default in SMBUS Control. -*/ - -static void sm_init(struct device *dev) -{ - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); -} - -static u32 get_sm_mmio(struct device *dev) -{ - struct resource *res; - struct bus *pbus; - - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); - if (res->base == SMB_BASE_ADDR) - return ACPIMMIO_SMBUS_BASE; - - return ACPIMMIO_ASF_BASE; -} - -static int lsmbus_recv_byte(struct device *dev) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_recv_byte(get_sm_mmio(dev), device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_send_byte(get_sm_mmio(dev), device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_read_byte(get_sm_mmio(dev), device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_write_byte(get_sm_mmio(dev), device, address, val); -} -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; -static struct device_operations smbus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = pci_dev_enable_resources, - .init = sm_init, - .scan_bus = scan_smbus, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, -}; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a03b8f3..c3fcad9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -51,6 +51,7 @@ select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index e6cfa12..eb8af2d 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -56,7 +56,6 @@ romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c -romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -90,8 +89,6 @@ ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += sata.c -ramstage-y += sm.c -ramstage-y += smbus.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c deleted file mode 100644 index 5474c5c..0000000 --- a/src/soc/amd/stoneyridge/smbus.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <console/console.h> -#include <device/smbus_host.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> - -/* - * Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -static u8 controller_read8(uintptr_t base, u8 reg) -{ - switch (base) { - case ACPIMMIO_SMBUS_BASE: - return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: - return asf_read8(reg); - default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", - base); - } - return 0xff; -} - -static void controller_write8(uintptr_t base, u8 reg, u8 val) -{ - switch (base) { - case ACPIMMIO_SMBUS_BASE: - smbus_write8(reg, val); - break; - case ACPIMMIO_ASF_BASE: - asf_write8(reg, val); - break; - default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", - base); - } -} - -static int smbus_wait_until_ready(uintptr_t mmio) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = controller_read8(mmio, SMBHSTSTAT); - val &= SMBHST_STAT_VAL_BITS; - if (val == 0) { /* ready now */ - return 0; - } - controller_write8(mmio, SMBHSTSTAT, val); - } while (--loops); - return -2; /* time out */ -} - -static int smbus_wait_until_done(uintptr_t mmio) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = controller_read8(mmio, SMBHSTSTAT); - val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ - if (val & SMBHST_STAT_ERROR_BITS) - return -5; /* error */ - if (val == SMBHST_STAT_NOERROR) { - controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ - return 0; - } - } while (--loops); - return -3; /* timeout */ -} - -int do_smbus_recv_byte(uintptr_t mmio, u8 device) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - /* read results of transaction */ - byte = controller_read8(mmio, SMBHSTDAT0); - - return byte; -} - -int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command... */ - controller_write8(mmio, SMBHSTDAT0, val); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - return 0; -} - -int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command/address... */ - controller_write8(mmio, SMBHSTCMD, address & 0xff); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - /* read results of transaction */ - byte = controller_read8(mmio, SMBHSTDAT0); - - return byte; -} - -int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command/address... */ - controller_write8(mmio, SMBHSTCMD, address & 0xff); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - - /* output value */ - controller_write8(mmio, SMBHSTDAT0, val); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Gerrit-Change-Number: 38616 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/google/puff: Enable HECI communication
by Jamie Chen (Code Review) 04 Feb '20

04 Feb '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38676 ) Change subject: mb/google/puff: Enable HECI communication ...................................................................... mb/google/puff: Enable HECI communication Set HeciEnabled = 1 on puff device tree to turn on Intel ME communication interface. BUG=b:143232330 BRANCH=None TEST=Build puff and boot up OS. ran lspci and confirmed there is a HECI device. 00:16.0 Communication controller: Intel Corporation Device 02e0 Change-Id: I2debb885022ae31e395869d014a91824b5dd980c Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38676/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d84b369..4ffbfed 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/38676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2debb885022ae31e395869d014a91824b5dd980c Gerrit-Change-Number: 38676 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: commonlib/cbfs.h: Correct spelling error in comment
by Marshall Dawson (Code Review) 04 Feb '20

04 Feb '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38684 ) Change subject: commonlib/cbfs.h: Correct spelling error in comment ...................................................................... commonlib/cbfs.h: Correct spelling error in comment Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f --- M src/commonlib/include/commonlib/cbfs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/38684/1 diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 4701730..f5842d9 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -24,7 +24,7 @@ struct region_device data; }; -/* Locate file by name and optional type. Returns 0 on succcess else < 0 on +/* Locate file by name and optional type. Returns 0 on success else < 0 on * error.*/ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, const char *name, uint32_t *type); -- To view, visit https://review.coreboot.org/c/coreboot/+/38684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f Gerrit-Change-Number: 38684 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: coreinfo/coreinfo.c: Correct main function signature
by Jacob Garber (Code Review) 04 Feb '20

04 Feb '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38292 ) Change subject: coreinfo/coreinfo.c: Correct main function signature ...................................................................... coreinfo/coreinfo.c: Correct main function signature libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/coreinfo/coreinfo.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38292/1 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 53985b2..b1017f0 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -290,8 +290,11 @@ } } -int main(void) +int main(int argc, char **argv) { + (void)argc; + (void)argv; + int j; if (CONFIG(LP_USB)) -- To view, visit https://review.coreboot.org/c/coreboot/+/38292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Gerrit-Change-Number: 38292 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: sc7180: Add UART support
by Roja Rani Yarubandi (Code Review) 04 Feb '20

04 Feb '20

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 32: (1 comment) > Patch Set 26: > > (1 comment) https://review.coreboot.org/c/coreboot/+/35500/26/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_uart.c: https://review.coreboot.org/c/coreboot/+/35500/26/src/soc/qualcomm/sc7180/q… PS26, Line 65: #ifndef __VERSTAGE__ > I don't understand why this changed here. […] This change is made by considering the case, if firmware is updated and to load the updated firmware image -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 32 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Feb 2020 12:46:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Usha P (Code Review) 04 Feb '20

04 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 38: > Patch Set 38: > > (4 comments) Thank you for the comments Patrick. I will revisit the design and get back, by end of next week. -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 38 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Feb 2020 10:47:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020