coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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1797 discussions

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by caveh jalali (Code Review) 05 Feb '20

05 Feb '20

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 16: (2 comments) https://review.coreboot.org/c/coreboot/+/37870/16/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/16/src/soc/intel/tigerlake/e… PS16, Line 29: * Flags representing mux state */ : #define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ : #define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ : #define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ : #define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ : #define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ : we can get these from ec_commands.h, right? https://review.coreboot.org/c/coreboot/+/37870/16/src/soc/intel/tigerlake/e… PS16, Line 158: mux_data.polarity = mux_flags & USB_PD_MUX_POLARITY_INVERTED; i'm a bit confused about the polarity and muxing policy. if there is no external retimer/redriver/TCPC, then TCSS has to do the muxing and it makes sense to ask the EC what the cable orientation is in order to set the mux appropriately. what happens when the muxing is potentially done externally? should we disable/prevent this by system design? my guess is that if we do have a case where muxing is done externally for some reason, the EC will still report the observed orientation and we'll end up double flipping the lanes. has this aspect of the system design been captured somewhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 16 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Wed, 05 Feb 2020 03:39:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/xhci: Fix MPS handling in set_address
by Edward O'Callaghan (Code Review) 05 Feb '20

05 Feb '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38556 ) Change subject: libpayload/xhci: Fix MPS handling in set_address ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/38556/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38556/1//COMMIT_MSG@10 PS1, Line 10: compares > compare Done https://review.coreboot.org/c/coreboot/+/38556/1//COMMIT_MSG@12 PS1, Line 12: if we need to change settings here. > Please don't, it looks very good. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Gerrit-Change-Number: 38556 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Feb 2020 03:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by caveh jalali (Code Review) 05 Feb '20

05 Feb '20

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... Patch Set 13: (4 comments) https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 50: 16 sizeof(pmc_ipc_buffer)? https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 634: struct const... better yet, does cmd need to be passed by reference at all? https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 634: uint32_t const... https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 636: uintptr_t looks like pmcbase is being cast to (void *) everywhere it is used, might as well define it as such. -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 13 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 05 Feb 2020 03:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/xhci: Fix MPS handling in set_address
by Edward O'Callaghan (Code Review) 05 Feb '20

05 Feb '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38556 ) Change subject: libpayload/xhci: Fix MPS handling in set_address ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Gerrit-Change-Number: 38556 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Feb 2020 02:52:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Add IccMax limitation for CML U22
by Jamie Chen (Code Review) 05 Feb '20

05 Feb '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37189 ) Change subject: soc/intel/cannonlake: Add IccMax limitation for CML U22 ...................................................................... soc/intel/cannonlake: Add IccMax limitation for CML U22 IccMax[IA_CORE] for U22 is 35A. Add a limitation to avoid IccMax setting over 35A in fill_vr_domain_config function. BUG:b:145094963 BRANCH: None TEST: build coreboot and fsp with enabling fw_debug. Flashed to device and checked the log. IccMax of IA_CORE have been setted correctly. Change-Id: I2ae8feee3073884109e0d171511c5ac01064ffd7 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37189/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 25270d8..671d93d 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -14,6 +14,9 @@ * */ +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> @@ -74,6 +77,8 @@ { FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; const struct vr_config *cfg; + struct device *sa_root; + uint16_t did; if (domain < 0 || domain >= NUM_VR_DOMAINS) return; @@ -96,4 +101,15 @@ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; + + /* Limit IA_CORE IccMax if CPU SKU is U22 */ + if (domain == VR_IA_CORE) { + sa_root = pcidev_path_on_root(SA_DEVFN_ROOT); + did = pci_read_config16(sa_root, PCI_DEVICE_ID); + if (did == PCI_DEVICE_ID_INTEL_CML_ULT_2_2 && + cfg->icc_max > VR_CFG_AMP(35)) { + printk(BIOS_DEBUG, "VR_CONFIG: IccMax[IA_CORE] has been limited to 35A\n"); + vr_params->IccMax[domain] = VR_CFG_AMP(35); + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ae8feee3073884109e0d171511c5ac01064ffd7 Gerrit-Change-Number: 37189 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in gerrit-avatars[master]: Add avatar for sibradzic
by Samir Ibradžić (Code Review) 05 Feb '20

05 Feb '20

Samir Ibradžić has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/38712 ) Change subject: Add avatar for sibradzic ...................................................................... Add avatar for sibradzic Signed-off-by: Samir Ibradzic <sibradzic(a)gmail.com> Change-Id: Ia3e568db82f139b2ec9fd4432168b00ef65d21c4 --- A 1002781.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/12/38712/1 diff --git a/1002781.jpg b/1002781.jpg new file mode 100644 index 0000000..b80de18 --- /dev/null +++ b/1002781.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/38712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: Ia3e568db82f139b2ec9fd4432168b00ef65d21c4 Gerrit-Change-Number: 38712 Gerrit-PatchSet: 1 Gerrit-Owner: Samir Ibradžić <sibradzic(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by build bot (Jenkins) (Code Review) 05 Feb '20

05 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... Patch Set 13: (10 comments) https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 257: enum cb_err pmc_send_ipc_cmd(uint32_t *cmd, uint32_t inlen, struct pmc_ipc_buffer *wbuf, struct pmc_ipc_buffer *rbuf); line over 96 characters https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 634: enum cb_err pmc_send_ipc_cmd(uint32_t *cmd, uint32_t inlen, struct pmc_ipc_buffer *wbuf, struct pmc_ipc_buffer *rbuf) line over 96 characters https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 638: pmcbase= soc_read_pmc_base(); spaces required around that '=' (ctx:VxW) https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 650: write32((void*)pmcbase + PMC_IPC_CMD_OFFSET, *cmd); "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 654: return CB_ERR; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 654: return CB_ERR; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 658: rbuf->buf0 = read32((void*)pmcbase + PMC_IPC_RBUF0); "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 659: rbuf->buf1 = read32((void*)pmcbase + PMC_IPC_RBUF1); "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 660: rbuf->buf2 = read32((void*)pmcbase + PMC_IPC_RBUF2); "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/37871/13/src/soc/intel/common/bloc… PS13, Line 661: rbuf->buf3 = read32((void*)pmcbase + PMC_IPC_RBUF3); "(foo*)" should be "(foo *)" -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 13 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 05 Feb 2020 02:05:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 05 Feb '20

05 Feb '20

Brandon Breitenstein has uploaded a new patch set (#16) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/early_tcss.c 3 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 16 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by Brandon Breitenstein (Code Review) 05 Feb '20

05 Feb '20

Brandon Breitenstein has uploaded a new patch set (#13) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... soc/intel/common/block: Enable PMC IPC driver In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 102 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37871/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 13 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP: Move SA _CRS to runtime SSDT generator
by Duncan Laurie (Code Review) 05 Feb '20

05 Feb '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38608 ) Change subject: WIP: Move SA _CRS to runtime SSDT generator ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/38608/2/src/soc/intel/common/block… File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/38608/2/src/soc/intel/common/block… PS2, Line 285: 0xfee00000 LOCAL_APIC_ADDR -- To view, visit https://review.coreboot.org/c/coreboot/+/38608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fbc5c99dcdb9463da9f2ace3423294af614abf Gerrit-Change-Number: 38608 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 Feb 2020 00:35:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020