coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46376 ) Change subject: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ...................................................................... drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram Since we change the caching setup it is probably a good idea to make sure our saved MTRR setup hits dram. Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46376/1 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 563dc08..31f41ed 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -107,6 +107,7 @@ movl %cr0, %eax orl $(CR0_CD | CR0_NW), %eax movl %eax, %cr0 + wbinvd /* Disable fixed MTRRs */ movl $(MTRR_DEF_TYPE_MSR), %ecx -- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: emulation/riscv: Don't probe for total DRAM
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36445 ) Change subject: emulation/riscv: Don't probe for total DRAM ...................................................................... emulation/riscv: Don't probe for total DRAM Trying accessing memory that is not there causes an exception. Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/mainboard.c M src/soc/ucb/riscv/cbmem.c 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36445/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..c3136c1 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -55,8 +55,8 @@ default 1 config DRAM_SIZE_MB - int - default 32768 + int "size of DRAM. Run qemu with the argument -m ***M" + default 1024 config OPENSBI_PLATFORM string diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 88898087..eda43c9 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -27,7 +27,7 @@ die("No dev0; die\n"); } - dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + dram_mb_detected = CONFIG_DRAM_SIZE_MB - CONFIG_ROM_SIZE; ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB); cbmem_recovery(0); diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d..9872760 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,9 +13,8 @@ #include <cbmem.h> #include <symbols.h> -#include <ramdetect.h> void *cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return _dram + CONFIG_DRAM_SIZE_MB * MiB - CONFIG_ROM_SIZE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Gerrit-Change-Number: 36445 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/*/*: Don't guard serial setup
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36603 ) Change subject: mb/*/*: Don't guard serial setup ...................................................................... mb/*/*: Don't guard serial setup Even without using the console it might be useful to set up the console regardless, for instance with VBOOT or normal/fallback setups. This will be more meaningful once C_ENVIRONMENT_BOOTBLOCK is implemented. Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/ocp/wedge100s/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36603/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 258eac7..b0dd962 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 6c139ed..e07007c 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 108d7a1..c0d2ca0 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -42,8 +42,7 @@ pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); - if (CONFIG(CONSOLE_SERIAL)) - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/36603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Gerrit-Change-Number: 36603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: *.asl: Don't define Devices by absolute path
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36600 ) Change subject: *.asl: Don't define Devices by absolute path ...................................................................... *.asl: Don't define Devices by absolute path Be consistent with the rest tree and set the scope first when defining devices. In general make the resulting code more readable as it avoid '^' symbols. Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M util/autoport/main.go 7 files changed, 42 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36600/1 diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 0e1cc3a..a1a70c0 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -32,9 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 1c7a620..2c14e8f 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -34,10 +34,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index 7ee12a0..e54b01b 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 82358aa..fd37f9e 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index d3e3602..6df1394 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -32,10 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 6ed19ee..8649a95 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -24,10 +24,11 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> #include <cpu/intel/common/acpi/cpu.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/util/autoport/main.go b/util/autoport/main.go index 03523a2..51d10cf 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -876,17 +876,20 @@ } dsdt.WriteString(` - Device (\_SB.PCI0) + Scope (\_SB) { + Device (PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) } - fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + fmt.Fprintf(dsdt, "\t\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } + ` } + } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/36600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Gerrit-Change-Number: 36600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35884 ) Change subject: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place ...................................................................... soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place include/device/pci_mmio_cfg.h now has a compile time error if MMCONF_BASE_ADDRESS is not defined. This requires soc/intel target to explicitly set this in the SOC dir, instead of potentially using a possibly wrong common default. Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig 5 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35884/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07..24a4b7a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -128,6 +128,10 @@ TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xd0000000 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1fda95..aeef75c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -109,6 +109,10 @@ select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573..d7619a0 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,10 +3,6 @@ help Intel Processor common System Agent support -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config SA_PCIEX_LENGTH hex default 0x10000000 if (PCIEX_LENGTH_256MB) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae..d12e4e3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -91,6 +91,10 @@ int default 16 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9..a9b8aaa 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -120,6 +120,10 @@ hex default 0x200000 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Gerrit-Change-Number: 35884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

9 19

Change in coreboot[master]: soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE...
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35887 ) Change subject: soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE_LENGTH ...................................................................... soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE_LENGTH Change-Id: Ib9facecc4caa869e65f938a55508741dd48b09b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35887/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index d7619a0..81a7f9d 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -8,7 +8,6 @@ default 0x10000000 if (PCIEX_LENGTH_256MB) default 0x8000000 if (PCIEX_LENGTH_128MB) default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 help This option allows you to select length of PCIEX region. diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 8c89c07..5411238 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -26,6 +26,10 @@ #include "systemagent_def.h" +#if CONFIG_SA_PCIEX_LENGTH == 0 +#error "SA_PCIEX_LENGTH undefined!" +#endif + void bootblock_systemagent_early_init(void) { uint32_t reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/35887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9facecc4caa869e65f938a55508741dd48b09b0 Gerrit-Change-Number: 35887 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: arch/x86/car.ld: Use REGION macro
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36696 ) Change subject: arch/x86/car.ld: Use REGION macro ...................................................................... arch/x86/car.ld: Use REGION macro The advantages of using the REGION macro: - less boilerplate for defining start and end symbols - overlap between regions checking - automatic alignment Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 4 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36696/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 74fc74b..c601d2e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -18,9 +18,7 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ - _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; - _epagetables = . ; + REGION(pagetables, ., 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4096) #endif /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ @@ -37,9 +35,7 @@ * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) - _car_stack = .; - . += CONFIG_DCACHE_BSP_STACK_SIZE; - _ecar_stack = .; + REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 16) #endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that @@ -47,22 +43,17 @@ * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG(PAGING_IN_CACHE_AS_RAM) - . = ALIGN(32); /* Page directory pointer table resides here. There are 4 8-byte entries * totalling 32 bytes that need to be 32-byte aligned. The reason the * pdpt are not colocated with the rest of the page tables is to reduce * fragmentation of the CAR space that persists across stages. */ - _pdpt = .; - . += 32; - _epdpt = .; + REGION(pdpt, ., 32, 32) #endif TIMESTAMP(., 0x200) - _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + REGION(car_ehci_dbg_info, ., 80, ARCH_POINTER_ALIGN_SIZE) /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -114,9 +105,6 @@ } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -#if CONFIG(PAGING_IN_CACHE_AS_RAM) -_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); -#endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee Gerrit-Change-Number: 36696 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: src/soc/intel/fsp-car: Align stack before jumping to C code
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37279 ) Change subject: src/soc/intel/fsp-car: Align stack before jumping to C code ...................................................................... src/soc/intel/fsp-car: Align stack before jumping to C code GCC has had a 16 byte stack requirement since quite some time now... Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37279/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index d7ef834..4174f36 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -99,6 +99,10 @@ xorl %eax, %eax rep stosl + /* Need to align stack to 16 bytes at call instruction. Account for + the two pushes below. */ + andl $0xfffffff0, %esp + sub $8, %esp /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/37279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed Gerrit-Change-Number: 37279 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/fsp-car: Clear the whole usable CAR region
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37277 ) Change subject: soc/intel/fsp-car: Clear the whole usable CAR region ...................................................................... soc/intel/fsp-car: Clear the whole usable CAR region Other symbols in car.ld likely expect to be zero initialized. Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37277/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..ec43311 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -89,13 +89,14 @@ /* Setup bootblock stack */ mov %edx, %esp - /* clear .bss section as it is not shared */ + /* coreboot assumes CAR region will be zero */ cld - xor %eax, %eax - movl $(_ebss), %ecx - movl $(_bss), %edi - sub %edi, %ecx + movl %ecx, %edi + neg %ecx + /* Clear up to Temp Ram top. */ + add %edx, %ecx shrl $2, %ecx + xorl %eax, %eax rep stosl /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b Gerrit-Change-Number: 37277 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/intel/fsp1.1: Use the coreboot symbols for the stack
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37276 ) Change subject: drivers/intel/fsp1.1: Use the coreboot symbols for the stack ...................................................................... drivers/intel/fsp1.1: Use the coreboot symbols for the stack We want to know where the stack is, to make sure that it does not override other CAR symbols. Change-Id: I9edf615bff11aa38fc307b4e2e2c97f1757a05a1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37276/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fea7acb..fb39884 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,8 +143,8 @@ cmp $0, %eax jne halt2 - /* Setup bootloader stack */ - movl %edx, %esp + /* Setup BSP stack */ + movl _ecar_stack, %esp /* * ebp: FSP_INFO_HEADER address -- To view, visit https://review.coreboot.org/c/coreboot/+/37276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edf615bff11aa38fc307b4e2e2c97f1757a05a1 Gerrit-Change-Number: 37276 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020