coreboot-gerrit November 2020

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Change in coreboot[master]: sb/intel/lynxpoint: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47095 ) Change subject: sb/intel/lynxpoint: Use common AHCI library ...................................................................... sb/intel/lynxpoint: Use common AHCI library This avoids confusing and potentially dangerous pointer arithmetics. Behaviour before after this patch should be equivalent, too. Change-Id: I62a26d74fe78dc0158b383da9126c56746722c53 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 39 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47095/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d8eb2a8..e4aa083 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "iobp.h" #include "pch.h" @@ -37,8 +38,6 @@ { u32 reg32; - u32 *abar; - /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -51,7 +50,7 @@ /* SATA configuration */ - /* Enable memory space decoding for ABAR */ + /* Enable memory space decoding for AHCI BAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -107,31 +106,47 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* Should be configurable */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ + ahci_cap.ahci_mode_only = 1; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + if (config->sata_devslp_disable) { + ahci_cap_2.supports_device_sleep = 0; + } else { + ahci_cap_2.auto_partial_to_slumber = 1; + ahci_cap_2.supports_device_sleep = 1; + ahci_cap_2.aggressive_devslp_mgmt = 1; + ahci_cap_2.devslp_entry_slumber_only = 1; + } } else { - reg32 &= ~0x00000002; + ahci_cap_2.nvm_hci_present = 0; } - write32(abar + 0x09, reg32); + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) -- To view, visit https://review.coreboot.org/c/coreboot/+/47095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a26d74fe78dc0158b383da9126c56746722c53 Gerrit-Change-Number: 47095 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47100 ) Change subject: sb/intel/bd82x6x: Use common AHCI library ...................................................................... sb/intel/bd82x6x: Use common AHCI library Behaviour before after this patch should be equivalent. Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 34 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47100/1 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 875f3f7..87aa841 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <option.h> #include <acpi/acpi_sata.h> +#include <southbridge/intel/common/ahci.h> #include <types.h> #include "chip.h" @@ -113,8 +114,6 @@ /* AHCI */ if (sata_mode == 0) { - u8 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); @@ -130,32 +129,42 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* Should be configurable */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + + /* If configured, override ISS */ if (config->sata_interface_speed_support) - { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); - reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); + ahci_cap.interface_speed = config->sata_interface_speed_support; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + + ahci_cap_2.nvm_hci_present = 0; + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); + /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); + reg32 = ahci_read32(ahci_bar, 0xa0); reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + ahci_write32(ahci_bar, 0xa0, reg32); } else { /* IDE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Gerrit-Change-Number: 47100 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sb/intel/bd82x6x/sata.c: Simplify RMW operations
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47106 ) Change subject: sb/intel/bd82x6x/sata.c: Simplify RMW operations ...................................................................... sb/intel/bd82x6x/sata.c: Simplify RMW operations Introduce the `sir_unset_and_set_mask` helper and simplify a PCI register update to not use an intermediate variable. Change-Id: Ibb33aef755bba1ae48e6029fcab0687d9faf62b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 13 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47106/1 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2b46cfa..a83dd63 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -28,6 +28,14 @@ pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_read_resources(struct device *dev) { struct resource *res; @@ -90,7 +98,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -120,10 +127,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* Port enable + OOB retry mode */ + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); @@ -204,19 +209,10 @@ /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); - reg32 = sir_read(dev, 0x54); - reg32 &= 0xff000000; - reg32 |= 0x5555aa; - sir_write(dev, 0x54, reg32); + sir_unset_and_set_mask(dev, 0x54, 0xffffff, 0x5555aa); sir_write(dev, 0x64, 0xcccc8484); - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0xcccc; - sir_write(dev, 0x68, reg32); - reg32 = sir_read(dev, 0x78); - reg32 &= 0x0000ffff; - reg32 |= 0x88880000; - sir_write(dev, 0x78, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0xcccc); + sir_unset_and_set_mask(dev, 0x78, 0xffff0000, 0x88880000); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000); -- To view, visit https://review.coreboot.org/c/coreboot/+/47106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb33aef755bba1ae48e6029fcab0687d9faf62b4 Gerrit-Change-Number: 47106 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47865 ) Change subject: sb/intel/ibexpeak: Use common AHCI library ...................................................................... sb/intel/ibexpeak: Use common AHCI library Behaviour before after this patch should be equivalent. Change-Id: I9b636f093dfaa5954667fe0198e6602e8c1e4943 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/sata.c 1 file changed, 37 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47865/1 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2c6b0ca..20458f5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <option.h> #include <acpi/acpi_sata.h> +#include <southbridge/intel/common/ahci.h> #include <types.h> #include "chip.h" @@ -53,9 +54,6 @@ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (sata_mode == 0) { - /* AHCI */ - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -80,31 +78,43 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended) */ - reg32 = read32(abar + 0x09); - reg32 &= ~0x00000002; - write32(abar + 0x09, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0x28); + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* TODO: Make this configurable? */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + + /* If configured, override ISS */ + if (config->sata_interface_speed_support) + ahci_cap.interface_speed = config->sata_interface_speed_support; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + + ahci_cap_2.nvm_hci_present = 0; + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); + + /* VSP (Vendor Specific Register) */ + reg32 = ahci_read32(ahci_bar, 0xa0); reg32 &= ~0x00000005; - write32(abar + 0x28, reg32); + ahci_write32(ahci_bar, 0xa0, reg32); + } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b636f093dfaa5954667fe0198e6602e8c1e4943 Gerrit-Change-Number: 47865 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/ibexpeak: Simplify SATA RMW operations
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47888 ) Change subject: sb/intel/ibexpeak: Simplify SATA RMW operations ...................................................................... sb/intel/ibexpeak: Simplify SATA RMW operations Change-Id: I115cb45b7573c8c9057ad0b7951cd0b3a79a1200 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/sata.c 1 file changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47888/1 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 20458f5..2072730 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -65,10 +64,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8100 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* 6 ports SKU + ORM */ + pci_update_config16(dev, 0x92, ~0x3f, 0x8100 | config->sata_port_map); /* SATA Initialization register */ pci_write_config32(dev, 0x94, @@ -123,9 +120,7 @@ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -141,10 +136,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map); /* SATA Initialization register */ pci_write_config32(dev, 0x94, -- To view, visit https://review.coreboot.org/c/coreboot/+/47888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I115cb45b7573c8c9057ad0b7951cd0b3a79a1200 Gerrit-Change-Number: 47888 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: HACK: Enable PCIe refclk 100M
by Qizhong Cheng (Code Review) 07 Aug '23

07 Aug '23

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48138 ) Change subject: HACK: Enable PCIe refclk 100M ...................................................................... HACK: Enable PCIe refclk 100M Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#. Signed-off-by: mtk20626 <qizhong.cheng(a)mediatek.com> Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 37aa5f1..fca5b83 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += spm.c ramstage-y += sspm.c ramstage-y += ufs.c +ramstage-y += pcie.c ramstage-y += ../common/mtlib.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h new file mode 100644 index 0000000..dd8f7ab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pcie.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PCIE_H +#define SOC_MEDIATEK_MT8192_PCIE_H + +void mtk_pcie_prepare(void); + +#endif diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c new file mode 100644 index 0000000..d3e4213 --- /dev/null +++ b/src/soc/mediatek/mt8192/pcie.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pcie.h> + +#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380) + +void mtk_pcie_prepare(void) +{ + u32 vaule; + + /* set PCIe clkreq# for refclk 100M */ + vaule = read32(REG_PCIE_CLKREQ_EN); + write32(REG_PCIE_CLKREQ_EN, vaule | 0x33); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad Gerrit-Change-Number: 48138 Gerrit-PatchSet: 1 Gerrit-Owner: Qizhong Cheng <qizhong.cheng(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/mal10: Use explicit includes
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48145 ) Change subject: mb/kontron/mal10: Use explicit includes ...................................................................... mb/kontron/mal10: Use explicit includes Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I7b913da9ff085db7e6512d8714bfd2e5331e00bd --- M src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c M src/mainboard/kontron/mal10/include/variant/gpio.h M src/mainboard/kontron/mal10/variants/mal10/gpio.c 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48145/1 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index 674b209..0419f9d 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <carrier/gpio.h> +#include <gpio.h> static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/include/variant/gpio.h index ea942ca..ec53e4a 100644 --- a/src/mainboard/kontron/mal10/include/variant/gpio.h +++ b/src/mainboard/kontron/mal10/include/variant/gpio.h @@ -3,8 +3,6 @@ #ifndef MAL_10_CFG_GPIO_H #define MAL_10_CFG_GPIO_H -#include <gpio.h> - void variant_early_gpio_configure(void); #endif /* MAL_10_CFG_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 3986776..e81ba6b 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <variant/gpio.h> static const struct pad_config gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b913da9ff085db7e6512d8714bfd2e5331e00bd Gerrit-Change-Number: 48145 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication
by John Zhao (Code Review) 07 Aug '23

07 Aug '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47656 ) Change subject: soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication ...................................................................... soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication There is a ACPI error message about no handler or method for GPE73 while plugging a USB3 flash driver to a type-C-to-A dongle. The PMC_GPE0_DW2 is routed to GPP_E and GPP_E9/USB_OC0# is mapped to GPE73. This change adds a dummy GPE Method _L73 for USB overcurrent indication. Kernel driver suspends the bus and host controller which avoids the host halted in USB overcurrent state. BUG=b:155158498;173054070 TEST=Built images for Voxel and Delbin boards. Verified GPE73 is enabled and unmasked. There is no handler or method error message for GPE73 while plugging a USB3 flash driver to a type-C-to-A dongle. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I25fca6de44ce5c513fb6f7c4cfe46c5b7686fb20 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47656/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9893833..d888e86 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -311,6 +311,12 @@ \_SB.PCI0.TRP2.HPME() \_SB.PCI0.TRP3.HPME() } + + /* USB_OC0# */ + Method(_L73, 0 , serialized) + { + Printf("USB Overcurrent Indicator"); + } } Scope (\_SB.PCI0) -- To view, visit https://review.coreboot.org/c/coreboot/+/47656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25fca6de44ce5c513fb6f7c4cfe46c5b7686fb20 Gerrit-Change-Number: 47656 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/intel/tgl: Customize PCH VR settings for better Sx power sa...
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43992 to review the following change. Change subject: mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings ...................................................................... mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43992/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..1aa1f26 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -151,6 +151,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..169433b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -147,6 +147,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y -- To view, visit https://review.coreboot.org/c/coreboot/+/43992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Gerrit-Change-Number: 43992 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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