Hello Tim Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/47391
to review the following change.
Change subject: mb/google/dedede/var/metaknight: enable USB2 port for camera
......................................................................
mb/google/dedede/var/metaknight: enable USB2 port for camera
Enable USB2 port 5 for user facing camera.
Enable USB2 port 6 for world facing camera.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a
Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/metaknight/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47391/1
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 0bdcdc5..d95a7eb 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -1,5 +1,9 @@
chip soc/intel/jasperlake
+ # USB Port Configuration
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -43,6 +47,22 @@
}"
device domain 0 on
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""User Facing Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""World Facing Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ end
+ end
+ end # USB xHCI
device pci 15.0 on end
end
device pci 15.3 off end # I2C 3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a
Gerrit-Change-Number: 47391
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com>
Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com>
Gerrit-MessageType: newchange
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 )
Change subject: libpayload/usb: Fix printf format string mismatches in debug messages
......................................................................
Patch Set 4:
> > should we reflow the affected areas to fit within 96 columns
> > to keep buildbot happy? i'm not convinced that aggressively
> > splitting format strings improves this patch.
>
> It's either that or you can't get verified+1 the way things work right now
No, that's not how this works (unless something changed very recently that I'm not aware of). The line comments Jenkins adds from checkpatch are always purely informational and do not affect Verified+1. We know checkpatch has false positives and it's perfectly valid to ignore them if reviewers agree on that -- they're just there to make sure you don't miss something, basically. In this case I totally agree with Caveh that it's probably more readable the existing way (and there's a "long strings" exception in the coding style for this, which checkpatch doesn't account for).
Verified+1 is only affected by actual compiler failures, or by failures of linters that are marked as "stable" (which checkpatch is not). In this case, it looks like the PRIxPTR macro was not defined or the respective header not included somewhere.
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Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc
Gerrit-Change-Number: 45024
Gerrit-PatchSet: 4
Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Gerrit-Comment-Date: Fri, 13 Nov 2020 01:20:42 +0000
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47168 )
Change subject: soc/intel/xeon_sp: Follow the Integration Guide recommendations
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47168/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47168/4//COMMIT_MSG@7
PS4, Line 7: soc/intel/xeon_sp: Follow the Integration Guide recommendations
The subject and commit message can be more specific, as there are only two items.
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Gerrit-Change-Number: 47168
Gerrit-PatchSet: 4
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Comment-Date: Fri, 13 Nov 2020 01:11:49 +0000
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Hello build bot (Jenkins), Patrick Georgi, Tim Wawrzynczak, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45025
to look at the new patch set (#4).
Change subject: libpayload/usb: Add format string checking to usb_debug
......................................................................
libpayload/usb: Add format string checking to usb_debug
This turns on the compiler's printf style format string checker.
BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
compiler errors when USB_DEBUG is enabled.
Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
---
M payloads/libpayload/drivers/usb/ohci.c
M payloads/libpayload/include/usb/usb.h
2 files changed, 26 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45025/4
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47553 )
Change subject: another test
......................................................................
Set Ready For Review
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Gerrit-Comment-Date: Fri, 13 Nov 2020 00:45:15 +0000
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47552 )
Change subject: test
......................................................................
Set Ready For Review
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Gerrit-Comment-Date: Fri, 13 Nov 2020 00:44:23 +0000
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47551 )
Change subject: test
......................................................................
Set Ready For Review
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