Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33447
Change subject: Documentation: Explain SimpleELF
......................................................................
Documentation: Explain SimpleELF
Explain coreboot's SELF format.
Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/lib/payloads/index.md
A Documentation/lib/payloads/selfboot.md
M Documentation/payloads.md
3 files changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33447/1
diff --git a/Documentation/lib/payloads/index.md b/Documentation/lib/payloads/index.md
index 44daef1..b8eca8c 100644
--- a/Documentation/lib/payloads/index.md
+++ b/Documentation/lib/payloads/index.md
@@ -6,6 +6,10 @@
coreboot supports multiple payloads, depending on the architecture of the
selected mainboard.
+## SimpleELF
+
+- [SimpleELF format](selfboot.md)
+
## FIT
- [uImage.FIT support](fit.md)
diff --git a/Documentation/lib/payloads/selfboot.md b/Documentation/lib/payloads/selfboot.md
new file mode 100644
index 0000000..62a4393
--- /dev/null
+++ b/Documentation/lib/payloads/selfboot.md
@@ -0,0 +1,28 @@
+# Simple ELF standard
+
+coreboot is able to use static linked ELF binaries as payload.
+To reduce complexity the ELF binaries are converted to coreboot's SimpleELF
+(SELF) format.
+The payload is therefore split into multiple sections by `cbfstool` at
+build time, each having a unique loading address and possible compression.
+
+## SELF loader
+The SELF loader implementation can be found in `src/lib/selfboot.c`.
+It decompresses the SELF sections and places them in memory.
+
+If the payload overlaps with the loading stage (*RAMSTAGE*) and
+`CONFIG_RELOCATABLE_RAMSTAGE` is selected, the loading stage is moved to another
+location in RAM.
+
+SELF payloads are **never** relocatable and will always be placed at the
+address they specify. If it's not possible to load the payload at the specified
+address, the system won't boot.
+
+### Calling conventions
+The SELF payload is called with a pointer to the coreboot tables as first
+argument.
+
+**Note:** The only exception is made on [RISC-V] which does use the *HARTID*
+and a pointer to the *FDT* as arguments.
+
+[RISC-V]: ../../arch/riscv/index.md
diff --git a/Documentation/payloads.md b/Documentation/payloads.md
index b1eae61..650818e 100644
--- a/Documentation/payloads.md
+++ b/Documentation/payloads.md
@@ -7,6 +7,12 @@
There is various software in that space that is either explicitly written as
payload or can be made to work as one.
+## ELF
+
+Executable and linking format (ELF) compatible static linked binaries can be
+loaded as payload.
+ELF binaries are loaded through the [SELF] boot mechanism.
+
## SeaBIOS
[SeaBIOS](https://www.seabios.org) is an open source implementation of
@@ -14,6 +20,7 @@
since. While originally written for emulators such as QEMU, it can be made
to work as a coreboot payload and all the necessary code is in SeaBIOS'
mainline code.
+SeaBIOS is loaded through the [SELF] boot mechanism.
## Tianocore
@@ -40,3 +47,8 @@
firmware project drivers that often reinvent the wheel) and the ability to
define boot policy with familiar tools, no matter if those are shell scripts
or compiled userland programs written in C, Go or other programming languages.
+
+On x86 platforms Linux is loaded through the [SELF] boot mechanism, by adding a
+*tampoline code* at the start of the kernel.
+
+[SELF]: lib/payloads/selfboot.md
--
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Gerrit-Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e
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Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39527 )
Change subject: lib/spd_bin: Use UNKNOWN for denoting missing part number
......................................................................
lib/spd_bin: Use UNKNOWN for denoting missing part number
If no part number is found, currently the message below is logged.
SPD: module part number is
Change it to::
SPD: module part number is UNKNOWN
Change-Id: I281bc05b38a326f84255799eaf6f742381cffc12
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M src/lib/spd_bin.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39527/1
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 35bcb4c..54946dd 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -191,7 +191,7 @@
/* Module Part Number */
spd_get_name(spd, spd_name, type);
- printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name);
+ printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name ? spd_name : "UNKNOWN");
printk(BIOS_INFO,
"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
--
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41230 )
Change subject: Documentation/mainboard/pcengines/apu1.md: Document recent issues
......................................................................
Documentation/mainboard/pcengines/apu1.md: Document recent issues
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ie79af9ad5b8e6198ad9ba8ce9b41b22319dbf87c
---
M Documentation/mainboard/pcengines/apu1.md
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/41230/1
diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md
index ccadd63..f9d3cd7 100644
--- a/Documentation/mainboard/pcengines/apu1.md
+++ b/Documentation/mainboard/pcengines/apu1.md
@@ -95,3 +95,11 @@
[apu1c1_flash]: apu1c1.jpg
[spi_header]: apu1_spi.jpg
[flashrom]: https://flashrom.org/Flashrom
+
+### Known issues
+
+- platform does not reliably POST after power failure, it hangs at
+ sbPowerOnInit (src/vendorcode/amd/cimx/sb800/SBPort.c:296) unable to perform
+ reset via CF9 port, issue is present since C bootblock migration
+- AmdInitLate reports ASSERTION_ERRORs during DMI table creation enabled in
+ CB:38343
--
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36539 )
Change subject: [WIP]Documentation: Add Intel microcode update mechanism
......................................................................
[WIP]Documentation: Add Intel microcode update mechanism
Document microcode updates and how secure microcode updates are done in
GNU/Linux.
Propose how to do microcode updates in coreboot.
Change-Id: I78350fc81cb0de7b0b2d9cbd8537e6b3815916c0
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/soc/intel/index.md
A Documentation/soc/intel/microcode/index.md
2 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36539/1
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
index f30ff9a..1cf8548 100644
--- a/Documentation/soc/intel/index.md
+++ b/Documentation/soc/intel/index.md
@@ -2,6 +2,10 @@
This section contains documentation about coreboot on specific Intel SOCs.
+## Common
+
+- [Microcode updates](microcode/index.md)
+
## Platforms
- [Common code development strategy](code_development_model/code_development_model.md)
diff --git a/Documentation/soc/intel/microcode/index.md b/Documentation/soc/intel/microcode/index.md
new file mode 100644
index 0000000..b7f5949
--- /dev/null
+++ b/Documentation/soc/intel/microcode/index.md
@@ -0,0 +1,107 @@
+# Microcode updates on Intel CPUs
+
+## What are microcodes?
+
+```eval_rst
+Microcode is a computer hardware technique that interposes a layer of
+organisation between the CPU hardware and the programmer-visible
+instruction set architecture of the computer. [#1]_
+```
+
+In coreboot the microcode updates are stored in files in the CBFS and
+are used to update the CPU microcode at runtime using a special instruction.
+
+## How does a microcode update look like?
+
+The microcode update is a binary provided by Intel consisting out of
+a header and data.
+The header holds the processor signature for which the update is
+intented and additional metadata.
+For detailed information check the [Intel SDM] 253668-060US Chapter 9.11.1
+
+## When are mirocode updates done?
+
+Microcode updates are stored in the CPU's SRAM and thus needs to be loaded
+after a hard reset. However loading microcode updates is done multiple times
+in coreboot's boot sequence.
+
+On some CPUs it's neccessary to do an microcode update before:
+* Cache-As-RAM is enabled
+* Legacy Intel TXT FIT boot is run
+* MultiProcessor-Init is run
+
+On some CPUs it's neccessary to do an microcode update after:
+* SMM setup was done
+* SGX setup was done
+
+## How to do microcode updates?
+
+The following chapter is based multiple sources and testing due to lack of clear
+documentation.
+
+In order to safely update microcode on any generation the GNU/Linux kernel
+"late loading mechanism" takes a conservative approach and obeys the following
+rules:
+
+```eval_rst
+* All physical CPU cores must be updated with the same microcode version [#2]_
+* Caches need to be flushed on certain CPUs prior to microcode update [#3]_
+* The sibling thread must be idle while a microcode update is ongoing [#4]_
+* All other APs on the same package should be idle (or in Wait-for-SIPI) [#5]_
+* The microcode update is done sequentially [#6]_
+```
+
+The downside of this approach is that it's very slow.
+
+It seems to be possible to run microcode updates in parallel on APs on specific
+CPUs.
+
+## How to do microcode updates in coreboot ramstage?
+
+*TBD*
+
+Proposal:
+1. Run microcode update sequential by default
+2. Flush caches in non CAR environment before running a microcode update
+3. Switch to parallel microcode update after extensive testing (10000 boot cycles)
+
+For parallel microcde update:
+1. On Intel HT enabled CPUs spinlock the slibing thread of a logical core
+2. On Intel HT enabled CPUs only update one thread of a physical core
+3. Synchronize microcode loading. This will make sure no other computational work
+ is being done while an update occurs (thus no Wait-for-SIPI).
+
+## Intel Hyper-Threading enabled CPUs
+
+```eval_rst
+According to Intel SDM a Hyper-Threading enabled core shares the microcode unit
+between the logical CPU cores [#4]_. Intel NetBurst CPUs must not attempt to
+update the microcode on both logical cores at the same time, this is safe for
+newer CPU generations.
+```
+
+## Where to obtain the microcode updates?
+
+The microcode update files can be found on Intel's [Github Microcode].
+
+## References
+- [Wikipedia microcode]
+- [Github Microcode]
+- [Intel SDM]
+
+-------------
+```eval_rst
+.. [#1] Kent, Allen; Williams, James G. (April 5, 1993). `Encyclopedia of Computer Science and Technology: Volume 28 <http://https://books.google.com/books?id=EjWV8J8CQEYC>`_
+.. [#2] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology"
+.. [#3] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890717/>`_
+.. [#4] `Intel SDM Document 253668-060US`_ Chapter 8.8.5 "Microcode Update Resources"
+.. [#5] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890713/>`_
+.. [#6] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology"
+
+.. _Intel SDM Document 253668-060US: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-…
+
+```
+
+[Wikipedia microcode]: https://en.wikipedia.org/wiki/Microcode
+[Github Microcode]: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
+[Intel SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-…
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