coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Furquan Shaikh (Code Review) 24 Sep '19

24 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 12: (30 comments) https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 10: 3 Is this true for all platforms? I think there should not be any default here and instead the platforms that support it should set it accordingly. https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… PS6, Line 760: set_cse_next_boot_partition > It sends HECI command to notify CSE about it's next boot partition to boot from on next reset. […] Can you please add all these expectations as comments in .h file where the function is declared? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 71: 0 0x0 to make it consistent with 0xf0 below. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 72: 5 0x5 https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 72: MKHI_GROUP_ID_HMRFPO Commit message does not talk about this change in name for the macro. It would be ideal to have a separate change for reorganizing MKHI_GROUP_IDs. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 73: Use tabs for consistency. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 86: #define ME_HFS_CWS_NORMAL 5 : #define ME_HFS_MODE_NORMAL 0 : #define ME_HFS_TEMP_DISABLE 3 : #define HECI_OP_MODE_SEC_OVERRIDE 5 These are all named so differently -- it is not clear which field within HFS they apply to. Also are these values consistent across all different platforms? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 91: * Space before * https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 91: Boot partition info and switching command Ids All commands here typically start with MKHI_. Can you please follow the same conventions. Also, can all the host commands be grouped together in some way? In fact, all the macros used above are ordered very randomly. Can you please organize these in a better way? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 92: Use tabs for consistency. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 93: Use tabs for consistency. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 99: Why is this blank line added? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 749: Partition Info resp Failed Use lowercase for leading characters. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 757: Partition Same here. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 770: struct set_boot_partition_info_resp { : struct mkhi_hdr hdr; : } __packed; Why not just struct mkhi_hdr switch_resp;? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 781: partition_id != BP1 && partition_id != BP2 So, BP1 and BP2 are fine but not BP3? Why? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 153: enum Do we need enum for this at all? Can this be something like: #define BOOT_PARTITION(n) ((n) - 1) If more partitions are supported in the future, you won't have to update it. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 160: typedef Let's just use "enum boot_partition_status" instead of the typedef. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 167: partition_fw_version How does this relate to the fw version that is currently decoded by each SoC driver? e.g. https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/cannonlake… https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 175: struct partition_fw_version fw_version; : boot_partition_status bp_status; Please add comments. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 177: addr I believe you mean "CSE region start"? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 179: CSE region addr same here. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 185: /* : * Boot Partition Info Flag Redundancy Enabled : * It indicates CSE supports RO and RW regions. : */ : #define BP_INFO_REDUNDANCY_EN (1 << 0) : : /* : * Boot Partition Info Flag Minimum Recovery Mode Enabled : * It indicates RO supports Minimum Recovery Mode. : */ : #define BP_INFO_MIN_RECO_MODE_EN (1 << 1) : : /* : * Boot Partition Info Flag Read-only Config Enabled : * The flag indicate ME enabled HW protection to CSE RO region. : */ : #define BP_INFO_READ_ONLY_CFG (1 << 2) Can these be put together into a enum boot_partition_info_flags? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 210: /* : * Next requested boot partition is updated when : * set_cse_next_boot_partition() is invoked. : */ What does that mean? https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 216: * space before * https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 220: Just one space should be enough. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 225: a and? https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… PS6, Line 147: MAX_ME_PARTITIONS > Ok, We should add a config to indicate if the FWU is supported on the platform, and then we can tie […] Yes, that would be ideal. https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… PS6, Line 183: /* Boot Partition Info Flag Redundancy Enabled */ : #define BP_INFO_REDUNDANCY_EN (1 << 0) : : /* Boot Partition Info Flag Min. Recovery Mode Enabled */ : #define BP_INFO_MIN_RECO_MODE_EN (1 << 1) : : /* Boot Partition Info Flag Read only Config Enabled */ : #define BP_INFO_READ_ONLY_CFG (1 << 2) > In order to support CSE FW update functionality with resilience, the CSE FW logically divided into R […] Can you please add this information to the comments? It would also be good to know what REDUNDANCY_EN or RECO_MODE_EN really means. https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… PS6, Line 212: /* Retrieves boot partitions Info CSE */ > The get_boot_partition_info_resp is utilized in multiple places at different points in the update fl […] I haven't looked at the CLs later in the train, but is it really necessary to expose get_boot_partition_info_resp in the header file? Can the required information be exposed via more granular APIs? -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Sep 2019 02:03:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to...
by Furquan Shaikh (Code Review) 24 Sep '19

24 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35545 ) Change subject: soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to common ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29 Gerrit-Change-Number: 35545 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Sep 2019 01:08:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/fsp_broadwell_de: Add devhide functionality
by Andrey Petrov (Code Review) 23 Sep '19

23 Sep '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35321 ) Change subject: soc/fsp_broadwell_de: Add devhide functionality ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 54: > Possibly change all the spaces to tabs in a follow on commit? Up to you. I added tabs in this patch https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 113: Coming of from > Reword this? Done https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/ubox.h: https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 42: : static inline void iio_hide(const uint8_t devno, const uint8_t funcno) > Why make this an inline function in a . […] I orignally wanted to avoid overhead of creating another file for just a tiny function. But I decided to do it anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/35321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Gerrit-Change-Number: 35321 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Sep 2019 23:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 23 Sep '19

23 Sep '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34998 ) Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... vendorcode/cavium: Replace use of __PRE_RAM__ Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34998 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index 8e348d0..e078e74 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -18,7 +18,6 @@ static struct bdk_devicetree_key_value *config_fdt; -#if !defined(__PRE_RAM__) static struct bdk_devicetree_key_value *bdk_config_duplicate( const struct bdk_devicetree_key_value *old, size_t free_space) @@ -38,7 +37,7 @@ return new; } -#endif + /** * Set the device tree used for configuration * @@ -49,11 +48,11 @@ */ int bdk_config_set_fdt(const struct bdk_devicetree_key_value *fdt) { -#if !defined(__PRE_RAM__) - config_fdt = bdk_config_duplicate(fdt, 0); -#else - config_fdt = (void *)fdt; -#endif + if (ENV_STAGE_HAS_HEAP_SECTION) + config_fdt = bdk_config_duplicate(fdt, 0); + else + config_fdt = (void *)fdt; + return 0; } @@ -66,7 +65,6 @@ */ static void set_value(const char *name, const char *val) { -#if !defined(__PRE_RAM__) struct bdk_devicetree_key_value *iter; char n[64]; @@ -98,7 +96,6 @@ iter++; iter->key = 0; iter->value = 0; -#endif } /** @@ -207,6 +204,9 @@ /* Make sure the correct access function was called */ assert(config_info[cfg_item].ctype == BDK_CONFIG_TYPE_INT); + if (!ENV_STAGE_HAS_HEAP_SECTION) + return; + if (!config_fdt) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/trace: Replace __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 23 Sep '19

23 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35399 ) Change subject: lib/trace: Replace __PRE_RAM__ use ...................................................................... lib/trace: Replace __PRE_RAM__ use Change-Id: I957be92594aced2e8465e7f94d8d42e44c3418d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/trace.h 1 file changed, 2 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35399/1 diff --git a/src/include/trace.h b/src/include/trace.h index 4f5b8c4..aed69a8 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -16,16 +16,7 @@ #ifndef __TRACE_H #define __TRACE_H - -#ifdef __PRE_RAM__ - -#define DISABLE_TRACE -#define ENABLE_TRACE -#define DISABLE_TRACE_ON_FUNCTION - -#else /* !__PRE_RAM__ */ - -#if CONFIG(TRACE) && !defined(__SMM__) +#if !ENV_ROMSTAGE_OR_BEFORE && CONFIG(TRACE) void __cyg_profile_func_enter(void *, void *) __attribute__((no_instrument_function)); @@ -46,5 +37,5 @@ #define DISABLE_TRACE_ON_FUNCTION #endif -#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957be92594aced2e8465e7f94d8d42e44c3418d7 Gerrit-Change-Number: 35399 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Extend FSB detection to cover TSC
by Kyösti Mälkki (Code Review) 23 Sep '19

23 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31340 Change subject: cpu/intel/common: Extend FSB detection to cover TSC ...................................................................... cpu/intel/common: Extend FSB detection to cover TSC Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 23 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31340/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 83220de..d06739c 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -18,14 +18,13 @@ #include <console/console.h> #include <commonlib/helpers.h> -static int get_fsb(void) +static int get_fsb_tsc(int *fsb, int *ratio) { struct cpuinfo_x86 c; static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; msr_t msr; - int ret = -2; get_fms(&c, cpuid_eax(1)); switch (c.x86) { @@ -33,49 +32,61 @@ switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; break; case 0x25: /* Nehalem BCLK fixed at 133MHz */ - ret = 133; + *fsb = 133; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - ret = 100; + *fsb = 100; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; } break; case 0xf: /* Netburst */ msr = rdmsr(MSR_EBC_FREQUENCY_ID); + *ratio = msr.lo >> 24; switch (c.x86_model) { case 0x2: - ret = f2x_fsb[(msr.lo >> 16) & 7]; + *fsb = f2x_fsb[(msr.lo >> 16) & 7]; break; case 0x3: case 0x4: case 0x6: - ret = core2_fsb[(msr.lo >> 16) & 7]; + *fsb = core2_fsb[(msr.lo >> 16) & 7]; break; } + default: + return -2; } - return ret; + if (*fsb > 0) + return 0; + return -1; } int get_ia32_fsb(void) { - int ret; + int ret, fsb, ratio; - ret = get_fsb(); + ret = get_fsb_tsc(&fsb, &ratio); if (ret == -1) printk(BIOS_ERR, "FSB not found\n"); if (ret == -2) printk(BIOS_ERR, "CPU not supported\n"); - return ret; + if (ret < 0) + return ret; + + return fsb; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/31340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Gerrit-Change-Number: 31340 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/fsp_broadwell_de: Add devhide functionality
by Andrey Petrov (Code Review) 23 Sep '19

23 Sep '19

Hello Werner Zeh, Patrick Rudolph, Patrick Rudolph, Matt DeVillier, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35321 to look at the new patch set (#10). Change subject: soc/fsp_broadwell_de: Add devhide functionality ...................................................................... soc/fsp_broadwell_de: Add devhide functionality Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h M src/soc/intel/fsp_broadwell_de/include/soc/ubox.h M src/soc/intel/fsp_broadwell_de/southcluster.c A src/soc/intel/fsp_broadwell_de/ubox.c 5 files changed, 168 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35321/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/35321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Gerrit-Change-Number: 35321 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/fsp_broadwell_de: Add devhide functionality
by Andrey Petrov (Code Review) 23 Sep '19

23 Sep '19

Hello Werner Zeh, Patrick Rudolph, Patrick Rudolph, Matt DeVillier, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35321 to look at the new patch set (#9). Change subject: soc/fsp_broadwell_de: Add devhide functionality ...................................................................... soc/fsp_broadwell_de: Add devhide functionality Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h M src/soc/intel/fsp_broadwell_de/include/soc/ubox.h M src/soc/intel/fsp_broadwell_de/southcluster.c 4 files changed, 141 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35321/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/35321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Gerrit-Change-Number: 35321 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Andrey Petrov (Code Review) 23 Sep '19

23 Sep '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 12: folks, is it possible to determine what partition maps where to physical location with this API? -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 23 Sep 2019 17:34:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Paul Fagerburg (Code Review) 23 Sep '19

23 Sep '19

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 23 Sep 2019 16:48:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2019