coreboot-gerrit September 2019

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Change in ...coreboot[master]: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33276 Change subject: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes ...................................................................... [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes fmaptool can deal with it and it makes the file more readable. Not defining WR_RO and COREBOOT(CBFS) insures the bootblock is at the bottom of the flash. Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x220/vboot-rwa.fmd 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/33276/1 diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..be06484 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -5,25 +5,25 @@ SI_ME@0x3000 0x4ed000 } SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Gerrit-Change-Number: 33276 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/me8183: Refactor dsi driver as common code
by jitao shi (Code Review) 31 Mar '22

31 Mar '22

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34562 ) Change subject: WIP: mediatek/me8183: Refactor dsi driver as common code ...................................................................... WIP: mediatek/me8183: Refactor dsi driver as common code BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd --- A src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h 7 files changed, 604 insertions(+), 1,050 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34562/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c new file mode 100644 index 0000000..cf6d228 --- /dev/null +++ b/src/soc/mediatek/common/dsi.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +void mtk_dsi_reset(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_write32(&dsi0->dsi_con_ctrl, 1); + dsi_write32(&dsi0->dsi_con_ctrl, 0); +} + +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_setbits_le32(&dsi0->dsi_phy_lccon, 1); +} + +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags) +{ + u32 tmp_reg1 = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +} + +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); +} + +void mtk_dsi_start(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_clrbits_le32(&dsi0->dsi_start, 1); + dsi_setbits_le32(&dsi0->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + + while (read32(&dsi0->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); + mdelay(20); + } + + dsi_write32(&dsi0->dsi_intsta, 0); + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + + ((cmdq_off + i) & (0xfffffffc)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } + + dsi_clrsetbits_le32(&dsi0->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi0->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + mtk_dsi_start(0); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi0->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); +} + +void push_table(struct lcm_init_table *init_cmd) +{ + u32 cmd, i; + u32 type; + + for (i = 0; ; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].len); + break; + + case END_OF_TABLE: + return; + + case INIT_DCS_CMD: + switch (init_cmd[i].len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + + case INIT_GENENIC_CMD: + default: + switch (init_cmd[i].len) { + case 0: + type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + } + } +} + diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0ffa196..7e43138 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -82,7 +82,7 @@ ramstage-y += ../common/usb.c usb.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b2279ea..23be800 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -25,71 +25,7 @@ static bool dual_dsi_mode; -static void mipi_write32(void *a, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void mipi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void mipi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void mipi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static void dsi_write32(void *a, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 txdiv0, txdiv1; @@ -97,6 +33,7 @@ u32 reg; u32 bit_per_pixel; int i, data_rate, mipi_tx_rate; + struct mipi_tx_regs *const mipi_tx0 = getmipitx_regbase(dsi_id); reg = read32(&mipi_tx0->dsi_bg_con); @@ -111,16 +48,16 @@ mipi_write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - mipi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + dsi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - mipi_setbits_le32(&mipi_tx0->dsi_con, + dsi_setbits_le32(&mipi_tx0->dsi_con, RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); switch (format) { case MIPI_DSI_FMT_RGB565: @@ -171,7 +108,7 @@ return -1; } - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); @@ -185,29 +122,47 @@ */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; pcw /= 13; - mipi_write32(&mipi_tx0->dsi_pll_con2, pcw); + dsi_write32(&mipi_tx0->dsi_pll_con2, pcw); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - mipi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - mipi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - mipi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); return mipi_tx_rate; } -static void mtk_dsi_phy_timconfig(u32 data_rate) +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 timcon0, timcon1, timcon2, timcon3; u32 cycle_time, ui, lpx; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / + (lanes * 1000 * 100); ui = 1000 / data_rate + 0x01; cycle_time = 8000 / data_rate + 0x01; @@ -228,67 +183,13 @@ dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); } -static void mtk_dsi_reset(void) +static void mtk_dsi_config_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) { - dsi_setbits_le32(&dsi0->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi0->dsi_con_ctrl, 1); + mtk_dsi_phy_timconfig(dsi_id, format, lanes, edid); + mtk_dsi_config_vdo_timing(dsi_id, mode_flags, format, edid); } -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, const struct edid *edid) { u32 hsync_active_byte; u32 hbp_byte; @@ -298,6 +199,7 @@ u32 bpp; u32 packet_fmt; u32 hactive; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); if (format == MIPI_DSI_FMT_RGB565) bpp = 2; @@ -353,18 +255,12 @@ dsi_write32(&dsi0->dsi_psctrl, packet_fmt); } -static void mtk_dsi_start(void) -{ - dsi_write32(&dsi0->dsi_start, 0); - /* Only start master DSI */ - write32(&dsi0->dsi_start, 1); -} - static void mtk_dsi_tx_cmd_type0(u8 cmd) { struct stopwatch sw; u32 cmdq0; u32 intsta_0, intsta_1; + struct dsi_regs *const dsi0 = getdsi_regbase(0); cmdq0 = (MIPI_DSI_DCS_SHORT_WRITE << 8) | SHORT_PACKET | (cmd << 16); @@ -406,10 +302,9 @@ return -1; mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_timing(0, mode_flags, format, lanes, edid); + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable(); @@ -455,3 +350,11 @@ mipi_clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } + +void *const getmipitx_regbase(u32 dsi_id){ + return dsi_id ? (void *)MIPI_TX1_BASE : (void *)MIPI_TX0_BASE; +} + +void *const getdsi_regbase(u32 dsi_id){ + return dsi_id ? (void *)DSI1_BASE : (void *)DSI0_BASE; +} \ No newline at end of file diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index ca35bd1..9b4f5db 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -17,431 +17,12 @@ #define _DSI_REG_H_ #include <edid.h> +#include <soc/dsi_common.h> #include <types.h> -enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565 -}; - -/* video mode */ -enum { - MIPI_DSI_MODE_VIDEO = BIT(0), - /* video burst mode */ - MIPI_DSI_MODE_VIDEO_BURST = BIT(1), - /* video pulse mode */ - MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), - /* enable auto vertical count mode */ - MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), - /* enable hsync-end packets in vsync-pulse and v-porch area */ - MIPI_DSI_MODE_VIDEO_HSE = BIT(4), - /* disable hfront-porch area */ - MIPI_DSI_MODE_VIDEO_HFP = BIT(5), - /* disable hback-porch area */ - MIPI_DSI_MODE_VIDEO_HBP = BIT(6), - /* disable hsync-active area */ - MIPI_DSI_MODE_VIDEO_HSA = BIT(7), - /* flush display FIFO on vsync pulse */ - MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), - /* disable EoT packets in HS mode */ - MIPI_DSI_MODE_EOT_PACKET = BIT(9), - /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ - MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), - /* transmit data in low power */ - MIPI_DSI_MODE_LPM = BIT(11) -}; - -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u8 reserved1[32]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[204]; - u32 dsi_cmdq0; -}; - -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_cmdq0, 0x200); -static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -static struct dsi_regs *const dsi1 = (void *)DSI1_BASE; - -/* DSI_INTSTA */ -enum { - LPRX_RD_RDY_INT_FLAG = BIT(0), - CMD_DONE_INT_FLAG = BIT(1), - TE_RDY_INT_FLAG = BIT(2), - VM_DONE_INT_FLAG = BIT(3), - EXT_TE_RDY_INT_FLAG = BIT(4), - DSI_BUSY = BIT(31), -}; - -/* DSI_CON_CTRL */ -enum { - DSI_RESET = BIT(0), - DSI_EN = BIT(1), - DSI_DUAL = BIT(4), -}; - -/* DSI_MODE_CTRL */ -enum { - MODE = 3, - CMD_MODE = 0, - SYNC_PULSE_MODE = 1, - SYNC_EVENT_MODE = 2, - BURST_MODE = 3, - FRM_MODE = BIT(16), - MIX_MODE = BIT(17) -}; - -/* DSI_PSCTRL */ -enum { - DSI_PS_WC = 0x3fff, - DSI_PS_SEL = (3 << 16), - PACKED_PS_16BIT_RGB565 = (0 << 16), - LOOSELY_PS_18BIT_RGB666 = (1 << 16), - PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) -}; - -/* DSI_CMDQ_SIZE */ -enum { - CMDQ_SIZE = 0x3f, -}; - -/* DSI_PHY_LCCON */ -enum { - LC_HS_TX_EN = BIT(0), - LC_ULPM_EN = BIT(1), - LC_WAKEUP_EN = BIT(2) -}; - -/*DSI_PHY_LD0CON */ -enum { - LD0_RM_TRIG_EN = BIT(0), - LD0_ULPM_EN = BIT(1), - LD0_WAKEUP_EN = BIT(2) -}; - -enum { - LPX = (0xff << 0), - HS_PRPR = (0xff << 8), - HS_ZERO = (0xff << 16), - HS_TRAIL = (0xff << 24) -}; - -enum { - TA_GO = (0xff << 0), - TA_SURE = (0xff << 8), - TA_GET = (0xff << 16), - DA_HS_EXIT = (0xff << 24) -}; - -enum { - CONT_DET = (0xff << 0), - CLK_ZERO = (0xf << 16), - CLK_TRAIL = (0xff << 24) -}; - -enum { - CLK_HS_PRPR = (0xff << 0), - CLK_HS_POST = (0xff << 8), - CLK_HS_EXIT = (0xf << 16) -}; - -/* DSI_VM_CMD_CON */ -enum { - VM_CMD_EN = BIT(0), - TS_VFP_EN = BIT(5), -}; - -/* DSI_CMDQ0 */ -enum { - CONFIG = (0xff << 0), - SHORT_PACKET = 0, - LONG_PACKET = 2, - BTA = BIT(2), - DATA_ID = (0xff << 8), - DATA_0 = (0xff << 16), - DATA_1 = (0xff << 24), -}; - -/* MIPITX_REG */ -struct mipi_tx_regs { - u32 dsi_con; - u32 dsi_clock_lane; - u32 dsi_data_lane[4]; - u8 reserved0[40]; - u32 dsi_top_con; - u32 dsi_bg_con; - u8 reserved1[8]; - u32 dsi_pll_con0; - u32 dsi_pll_con1; - u32 dsi_pll_con2; - u32 dsi_pll_con3; - u32 dsi_pll_chg; - u32 dsi_pll_top; - u32 dsi_pll_pwr; - u8 reserved2[4]; - u32 dsi_rgs; - u32 dsi_gpi_en; - u32 dsi_gpi_pull; - u32 dsi_phy_sel; - u32 dsi_sw_ctrl_en; - u32 dsi_sw_ctrl_con0; - u32 dsi_sw_ctrl_con1; - u32 dsi_sw_ctrl_con2; - u32 dsi_dbg_con; - u32 dsi_dbg_out; - u32 dsi_apb_async_sta; -}; - -check_member(mipi_tx_regs, dsi_top_con, 0x40); -check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); - -static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE; -static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE; - -/* MIPITX_DSI0_CON */ -enum { - RG_DSI0_LDOCORE_EN = BIT(0), - RG_DSI0_CKG_LDOOUT_EN = BIT(1), - RG_DSI0_BCLK_SEL = (3 << 2), - RG_DSI0_LD_IDX_SEL = (7 << 4), - RG_DSI0_PHYCLK_SEL = (2 << 8), - RG_DSI0_DSICLK_FREQ_SEL = BIT(10), - RG_DSI0_LPTX_CLMP_EN = BIT(11) -}; - -/* MIPITX_DSI0_CLOCK_LANE */ -enum { - LDOOUT_EN = BIT(0), - CKLANE_EN = BIT(1), - IPLUS1 = BIT(2), - LPTX_IPLUS2 = BIT(3), - LPTX_IMINUS = BIT(4), - LPCD_IPLUS = BIT(5), - LPCD_IMLUS = BIT(6), - RT_CODE = (0xf << 8) -}; - -/* MIPITX_DSI_TOP_CON */ -enum { - RG_DSI_LNT_INTR_EN = BIT(0), - RG_DSI_LNT_HS_BIAS_EN = BIT(1), - RG_DSI_LNT_IMP_CAL_EN = BIT(2), - RG_DSI_LNT_TESTMODE_EN = BIT(3), - RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), - RG_DSI_LNT_AIO_SEL = (7 << 8), - RG_DSI_PAD_TIE_LOW_EN = BIT(11), - RG_DSI_DEBUG_INPUT_EN = BIT(12), - RG_DSI_PRESERVE = (7 << 13) -}; - -/* MIPITX_DSI_BG_CON */ -enum { - RG_DSI_BG_CORE_EN = BIT(0), - RG_DSI_BG_CKEN = BIT(1), - RG_DSI_BG_DIV = (0x3 << 2), - RG_DSI_BG_FAST_CHARGE = BIT(4), - RG_DSI_V12_SEL = (7 << 5), - RG_DSI_V10_SEL = (7 << 8), - RG_DSI_V072_SEL = (7 << 11), - RG_DSI_V04_SEL = (7 << 14), - RG_DSI_V032_SEL = (7 << 17), - RG_DSI_V02_SEL = (7 << 20), - rsv_23 = BIT(23), - RG_DSI_BG_R1_TRIM = (0xf << 24), - RG_DSI_BG_R2_TRIM = (0xf << 28) -}; - -/* MIPITX_DSI_PLL_CON0 */ -enum { - RG_DSI0_MPPLL_PLL_EN = BIT(0), - RG_DSI0_MPPLL_PREDIV = (3 << 1), - RG_DSI0_MPPLL_TXDIV0 = (3 << 3), - RG_DSI0_MPPLL_TXDIV1 = (3 << 5), - RG_DSI0_MPPLL_POSDIV = (7 << 7), - RG_DSI0_MPPLL_MONVC_EN = BIT(10), - RG_DSI0_MPPLL_MONREF_EN = BIT(11), - RG_DSI0_MPPLL_VOD_EN = BIT(12) -}; - -/* MIPITX_DSI_PLL_CON1 */ -enum { - RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0), - RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1), - RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2), - RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16) -}; - -/* MIPITX_DSI_PLL_PWR */ -enum { - RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), - RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), - RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) -}; - -/* LVDS_TX1_REG */ -struct lvds_tx1_regs { - u32 lvdstx1_ctl1; - u32 lvdstx1_ctl2; - u32 lvdstx1_ctl3; - u32 lvdstx1_ctl4; - u32 lvdstx1_ctl5; - u32 vopll_ctl1; - u32 vopll_ctl2; - u32 vopll_ctl3; -}; - static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800); -/* LVDS_VOPLL_CTRL3 */ -enum { - RG_LVDSTX_21EDG = BIT(0), - RG_LVDSTX_21LEV = BIT(1), - RG_LVDSTX_51EDG = BIT(2), - RG_LVDSTX_51LEV = BIT(3), - RG_AD_LVDSTX_PWR_ACK = BIT(4), - RG_DA_LVDS_ISO_EN = BIT(8), - RG_DA_LVDSTX_PWR_ON = BIT(9) -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, bool dual_dsi_mode, const struct edid *edid); void mtk_dsi_pin_drv_ctrl(void); diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 15ad154..355c889 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -43,7 +43,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 30057c7..383f79e 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -1,481 +1,310 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <console/console.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/dsi.h> -#include <timer.h> - -static void dsi_write32(void *a, uint32_t v) -{ - write32(a, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - clrsetbits_le32(a, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - clrbits_le32(a, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - setbits_le32(a, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, - const struct edid *edid) -{ - unsigned int txdiv, txdiv0, txdiv1; - u64 pcw; - int data_rate; - u32 bpp; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bpp = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bpp = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bpp = 24; - break; - } - - data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; - - printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); - - if (data_rate >= 2000000000) { - txdiv = 1; - txdiv0 = 0; - txdiv1 = 0; - } else if (data_rate >= 1000000000) { - txdiv = 2; - txdiv0 = 1; - txdiv1 = 0; - } else if (data_rate >= 500000000) { - txdiv = 4; - txdiv0 = 2; - txdiv1 = 0; - } else if (data_rate > 250000000) { - txdiv = 8; - txdiv0 = 3; - txdiv1 = 0; - } else if (data_rate >= 125000000) { - txdiv = 16; - txdiv0 = 4; - txdiv1 = 0; - } else { - printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " - "pixel clock (%u), bpp (%u), number of lanes (%u)\n", - data_rate, edid->mode.pixel_clock, bpp, - lanes); - return -1; - } - - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10)); - - dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); - udelay(30); - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); - - pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); - pcw <<= 24; - pcw /= 26; - - dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw); - dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, - txdiv0 << 8); - udelay(30); - dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN); - - /* BG_LPF_EN / BG_CORE_EN */ - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180); - udelay(40); - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0); - - /* Switch OFF each Lane */ - dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); - - dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); - - return data_rate; -} - -static void mtk_dsi_phy_timconfig(u32 data_rate, - struct mtk_phy_timing *phy_timing) -{ - u32 timcon0, timcon1, timcon2, timcon3; - - timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | - phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; - timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | - phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; - timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | - phy_timing->clk_hs_trail << 24; - timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | - phy_timing->clk_hs_exit << 16; - - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); -} - -static void mtk_dsi_reset(void) -{ - dsi_write32(&dsi->dsi_con_ctrl, 1); - dsi_write32(&dsi->dsi_con_ctrl, 0); -} - -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, - const struct edid *edid, - struct mtk_phy_timing *phy_timing) -{ - u32 ui, cycle_time, data_rate; - u32 bit_per_pixel; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bit_per_pixel = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bit_per_pixel = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bit_per_pixel = 24; - break; - } - - data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; - - ui = 1000 / (data_rate / 1000) + 1U; - cycle_time = 8000 / (data_rate / 1000) + 1U; - - phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); - - phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; - - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; - - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid, - struct mtk_phy_timing *phy_timing, - u32 lanes) -{ - u32 hsync_active_byte; - u32 hbp_byte; - u32 hfp_byte, tmp_hfp_byte; - u32 vbp_byte; - u32 vfp_byte; - u32 bpp; - u32 packet_fmt; - u32 hactive; - u32 data_phy_cycles; - - if (format == MIPI_DSI_FMT_RGB565) - bpp = 2; - else - bpp = 3; - - vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - - edid->mode.vborder; - vfp_byte = edid->mode.vso - edid->mode.vborder; - - dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); - dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); - dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); - dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bpp - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; - - hsync_active_byte = edid->mode.hspw * bpp - 10; - - data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; - - tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { - if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } else { - if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } - - dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); - dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); - dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); - - switch (format) { - case MIPI_DSI_FMT_RGB888: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - packet_fmt = LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - packet_fmt = PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - packet_fmt = PACKED_PS_16BIT_RGB565; - break; - default: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - } - - hactive = edid->mode.ha; - packet_fmt |= (hactive * bpp) & DSI_PS_WC; - - dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); - dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); -} - -static void mtk_dsi_start(void) -{ - dsi_clrbits_le32(&dsi->dsi_start, 1); - dsi_setbits_le32(&dsi->dsi_start, 1); -} - -static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) -{ - struct stopwatch sw; - u8 *tx_buf = data; - u8 cmdq_size; - u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; - - while (read32(&dsi->dsi_intsta) & (1 << 31)) { - printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); - mdelay(20); - } - - dsi_write32(&dsi->dsi_intsta, 0); - - if (MTK_DSI_HOST_IS_READ(type)) - config = BTA; - else - config = (len > 2) ? LONG_PACKET : SHORT_PACKET; - - if (len > 2) { - cmdq_size = 1 + (len + 3) / 4; - cmdq_off = 4; - cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; - reg_val = (len << 16) | (type << 8) | config; - } else { - cmdq_size = 1; - cmdq_off = 2; - cmdq_mask = CONFIG | DATA_ID; - reg_val = (type << 8) | config; - } - - for (i = 0; i < 0x20; i = i + 4) - dsi_write32((void *)DSI_BASE + 0x200 + i, 0); - - for (i = 0; i < len; i++) { - dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + - ((cmdq_off + i) & (0xfffffffc)), - (0xff << (((i + cmdq_off) & 3) * 8)), - tx_buf[i] << (((i + cmdq_off) & 3) * 8)); - } - - dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); - dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - mtk_dsi_start(); - - stopwatch_init_usecs_expire(&sw, 400); - do { - intsta_0 = read32(&dsi->dsi_intsta); - if (intsta_0 & CMD_DONE_INT_FLAG) - break; - udelay(4); - } while (!stopwatch_expired(&sw)); - - if (!(intsta_0 & CMD_DONE_INT_FLAG)) - printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); -} - -static void push_table(struct lcm_init_table *init_cmd) -{ - u32 cmd, i; - u32 type; - - for (i = 0; ; i++) { - cmd = init_cmd[i].cmd; - - switch (cmd) { - case DELAY_CMD: - mdelay(init_cmd[i].len); - break; - - case END_OF_TABLE: - return; - - case INIT_DCS_CMD: - switch (init_cmd[i].len) { - case 0: - return; - - case 1: - type = MIPI_DSI_DCS_SHORT_WRITE; - break; - - case 2: - type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - - default: - type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - - case INIT_GENENIC_CMD: - default: - switch (init_cmd[i].len) { - case 0: - type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - case 1: - type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - case 2: - type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - default: - type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - } - } -} - -int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, - const struct edid *edid, struct lcm_init_table *init_cmd) -{ - int data_rate; - struct mtk_phy_timing phy_timing; - - mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); - - data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); - - if (data_rate < 0) - return -1; - - dsi_write32(&dsi->dsi_force_commit, 3); - mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate, &phy_timing); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes); - mtk_dsi_clk_hs_mode_enable(); - push_table(init_cmd); - mtk_dsi_set_mode(mode_flags); - mtk_dsi_start(); - - return 0; -} +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void *getmipitx_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)MIPITX_BASE; +} + +void *getdsi_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)DSI_BASE; +} + +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + u32 ui, cycle_time, data_rate, bit_per_pixel; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi0->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi0->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi0->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); +} + +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, + const struct edid *edid) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 bpp; + void *mipi_tx0 = getmipitx_regbase(dsi_id); + + if (dsi_id > 0) { + printk(BIOS_ERR, "No support dual dsi, please check you panel config\n"); + return -1; + } + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bpp = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bpp = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bpp = 24; + break; + } + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; + + printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bpp, + lanes); + return -1; + } + + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); + pcw <<= 24; + pcw /= 26; + + dsi_write32(mipi_tx0 + MIPITX_PLL_CON0, pcw); + dsi_clrsetbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + dsi_clrbits_le32(mipi_tx0 + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + dsi_setbits_le32(mipi_tx0 + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte, tmp_hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + u32 data_phy_cycles; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } else { + if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } + + dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi0->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi0->dsi_size_con, edid->mode.va << 16 | hactive); + dsi_write32(&dsi0->dsi_force_commit, 3); +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd) +{ + int data_rate; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + struct mtk_phy_timing *phy_timing = NULL; + + data_rate = mtk_dsi_phy_clk_setting(0, format, lanes, edid); + + if (data_rate < 0) + return -1; + + if (dual) { + data_rate = mtk_dsi_phy_clk_setting(1, format, lanes, edid); + if (data_rate < 0) + return -1; + } + + mtk_dsi_reset(0); + if (dual) + mtk_dsi_reset(1); + + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_phy_timconfig(0, format, lanes, edid, phy_timing); + mtk_dsi_config_vdo_timing(0, mode_flags, format, lanes, edid, phy_timing); + mtk_dsi_clk_hs_mode_enable(0); + + push_table(init_cmd); + + mtk_dsi_set_mode(0, mode_flags); + if (dual) { + mtk_dsi_set_mode(1, mode_flags); + dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL); + } + mtk_dsi_start(0); + + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 1fb3509..5f614034 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -483,4 +483,19 @@ const struct edid *edid, struct lcm_init_table *init_cmd); +void *getmipitx_regbase(u32 dsi_id); +void *getdsi_regbase(u32 dsi_id); + +void dsi_write32(void *a, uint32_t v); +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v); +void dsi_clrbits_le32(void *a, uint32_t m); +void dsi_setbits_le32(void *a, uint32_t m); +void mtk_dsi_reset(u32 dsi_id); +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id); +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags); +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes); +void mtk_dsi_start(u32 dsi_id); +void push_table(struct lcm_init_table *init_cmd); + + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd Gerrit-Change-Number: 34562 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: WIP: mediatek/mt8183: Add SCP work support
by Erin Lo (Code Review) 31 Mar '22

31 Mar '22

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34382 ) Change subject: WIP: mediatek/mt8183: Add SCP work support ...................................................................... WIP: mediatek/mt8183: Add SCP work support Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries. After SCP works done, disable it Test=Build pass Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/scp.h A src/soc/mediatek/mt8183/scp.c 6 files changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..f8a5bab 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,18 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += scp_0.bin +scp_0.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_0.bin +scp_0.bin-type := raw +scp_0.bin-compression := none + +cbfs-files-y += scp_1.bin +scp_1.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_1.bin +scp_1.bin-type := raw +scp_1.bin-compression := none + +cbfs-files-y += scp_2.bin +scp_2.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_2.bin +scp_2.bin-type := raw +scp_2.bin-compression := none diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..cf3572d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,7 +19,7 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> - +#include <soc/scp.h> #include "early_init.h" void platform_romstage_main(void) @@ -33,6 +33,7 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); + scp_work(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d35a07e..0543552 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index e9f80d1..affc776 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,9 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SCP_SRAM_BASE = IO_PHYS + 0x00500000, + SCP_CFG_BASE = IO_PHYS + 0x005C0000, + SCP_CLK_CTRL_BASE = IO_PHYS + 0x005C4000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/scp.h b/src/soc/mediatek/mt8183/include/soc/scp.h new file mode 100644 index 0000000..a3003bd --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/scp.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SCP_H +#define SOC_MEDIATEK_MT8183_SCP_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_scp_regs { + u32 sw_rstn; + u32 reserved[19]; + u32 gpr0; +}; + +struct mt8183_scp_clk_ctrl_regs { + u32 reserved[11]; + u32 sram_pdn; +}; + +static struct mt8183_scp_regs *const mt8183_scp = (void *)SCP_CFG_BASE; +static struct mt8183_scp_clk_ctrl_regs *const mt8183_scp_clk_ctrl = (void *)SCP_CLK_CTRL_BASE; +void scp_work(void); +#endif /* SOC_MEDIATEK_MT8183_SCP_H */ diff --git a/src/soc/mediatek/mt8183/scp.c b/src/soc/mediatek/mt8183/scp.c new file mode 100644 index 0000000..150eeba --- /dev/null +++ b/src/soc/mediatek/mt8183/scp.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/mmio.h> +#include <soc/scp.h> +#include <string.h> + +#define BUF_SIZE (40 * KiB) +static uint8_t scp_bin[BUF_SIZE] __aligned(8); + +void scp_work(void) +{ + size_t fw_size; + + write32(&mt8183_scp_clk_ctrl->sram_pdn, 0x0); + mb(); + + fw_size = cbfs_boot_load_file("scp_0.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_0.bin not found."); + memcpy((void *)SCP_SRAM_BASE + 0x0, scp_bin, fw_size); + + fw_size = cbfs_boot_load_file("scp_1.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); + if (fw_size == 0) + die("SCP file :scp_1.bin not found."); + + fw_size = cbfs_boot_load_file("scp_2.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_2.bin not found."); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); + + + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8183_scp->sw_rstn, 0x1); + while (read32(&mt8183_scp->gpr0) != 0xaaaa){} + mb(); + write32(&mt8183_scp->sw_rstn, 0x0); + printk(BIOS_DEBUG, "scp finished \n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Gerrit-Change-Number: 34382 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: drivers/i2c/at24rf08c: Cache devices associated with this driver
by Nico Huber (Code Review) 15 Feb '22

15 Feb '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35490 ) Change subject: drivers/i2c/at24rf08c: Cache devices associated with this driver ...................................................................... drivers/i2c/at24rf08c: Cache devices associated with this driver To get rid of the fragile dev_find_slot_on_smbus(), we let the chip driver register the individual devices (EEPROMs) instead. They will be cached in an global array. So, the implementation assumes that there is only one instance of this driver but that should always be the case. Change-Id: I11eade2cea924839f4b1e1eeee612931fdfd1299 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo.h M src/drivers/i2c/at24rf08c/lenovo_serials.c 3 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35490/1 diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 67760a0..7fbae84 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -18,6 +18,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include "lenovo.h" static void at24rf08c_init(struct device *dev) { @@ -26,9 +27,14 @@ if (!dev->enabled) return; + if (dev->path.type != DEVICE_PATH_I2C) + return; + + lenovo_serials_register_bank(dev); + /* Ensure that EEPROM/RFID chip is not accessible through RFID. Need to do it only on 5c. */ - if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c) + if (dev->path.i2c.device != 0x5c) return; printk (BIOS_DEBUG, "Locking EEPROM RFID\n"); diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h index 6824eb6..45d45cc 100644 --- a/src/drivers/i2c/at24rf08c/lenovo.h +++ b/src/drivers/i2c/at24rf08c/lenovo.h @@ -1 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DRIVERS_I2C_AT24RF08C_LENOVO_H +#define DRIVERS_I2C_AT24RF08C_LENOVO_H + +#include <device/device.h> + const char *lenovo_mainboard_partnumber(void); + +void lenovo_serials_register_bank(struct device *); + +#endif /* DRIVERS_I2C_AT24RF08C_LENOVO_H */ diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 0a6b343..584714e 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -24,10 +24,20 @@ #define ERROR_STRING "*INVALID*" +static struct device *banks[4]; + +void lenovo_serials_register_bank(struct device *const dev) +{ + if (0x54 > dev->path.i2c.device || dev->path.i2c.device > 0x57) + return; + banks[dev->path.i2c.device & 3] = dev; +} + static struct device *at24rf08c_find_bank(u8 bank) { - struct device *dev; - dev = dev_find_slot_on_smbus(1, 0x54 | bank); + struct device *const dev = banks[bank]; + if (bank > ARRAY_SIZE(banks)) + return NULL; if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; @@ -72,7 +82,6 @@ dev = at24rf08c_find_bank(bank); if (dev == NULL) { - printk(BIOS_WARNING, "EEPROM not found\n"); memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); return; } @@ -134,9 +143,8 @@ memset(result, 0, sizeof (result)); - dev = dev_find_slot_on_smbus(1, 0x56); + dev = at24rf08c_find_bank(2); if (dev == NULL) { - printk(BIOS_WARNING, "EEPROM not found\n"); already_read = 1; memset(uuid, 0, 16); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/35490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11eade2cea924839f4b1e1eeee612931fdfd1299 Gerrit-Change-Number: 35490 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock
by Thomas Heijligen (Code Review) 01 Feb '22

01 Feb '22

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31371 to review the following change. Change subject: soc/intel/apl: enable lpc at bootblock ...................................................................... soc/intel/apl: enable lpc at bootblock Serial console can be attached to lpc bus. Enable it for early debug Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..e0217ef 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -120,4 +121,6 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + + pch_enable_lpc(); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b8f9f8c..2f25a3b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,9 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Generic i/o decode ranges routed to LPC */ + uint32_t lpc_gen_dec[4]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82a..ffa4cf5 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -42,6 +42,18 @@ return apl_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const struct soc_intel_apollolake_config *const config = dev->chip_info; + + if (!config) { + memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec)); + return; + } + + memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec)); +} + static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index fb50b74..d584d2c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -24,6 +24,9 @@ #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <stdint.h> + +__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {} uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Gerrit-Change-Number: 31371 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...
by Benjamin Doron (Code Review) 28 Jan '22

28 Jan '22

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 ) Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. ...................................................................... mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..f56a2a2 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000..4b3c127 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,68 @@ +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform has no way to see POST codes so disable them by default. + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + string + default "Aspire VN7-572G" + +config MAINBOARD_DIR + string + default "acer/aspire_vn7_572g" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000..b881680 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000..2eed489 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (EMBA, 0xFE800000) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID + + Name (_GPE, 0x50) // _GPE: General Purpose Events + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + }) + OperationRegion (ECO1, SystemIO, 0x62, One) + Field (ECO1, ByteAcc, Lock, Preserve) + { + PX62, 8 + } + + OperationRegion (ECO2, SystemIO, 0x66, One) + Field (ECO2, ByteAcc, Lock, Preserve) + { + PX66, 8 + } + + OperationRegion (ECMB, SystemMemory, EMBA, 0x0200) + OperationRegion (RAM, EmbeddedControl, Zero, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, + Offset (0x06), + CMD2, 8, + CMD1, 8, + CMD0, 8, + Offset (0x0A), + , 1, /* Reserved */ + , 1, /* Reserved */ + Offset (0x10), + EQEN, 1, + , 1, /* Reserved */ + Offset (0x4E), + ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */ + Offset (0x51), + , 3, /* Reserved */ + TPEN, 1, + Offset (0x52), + WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */ + BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */ + EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */ + , 3, /* Reserved */ + RFEX, 1, + Offset (0x57), + , 7, /* Reserved */ + AHKB, 1, + AHKE, 8, + Offset (0x5C), + Offset (0x5D), + Offset (0x70), + , 1, /* Reserved */ + KLID, 1, /* LID? */ + , 3, /* Reserved */ + KACS, 1, /* AC power? */ + Offset (0x71), + WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */ + BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */ + , 3, /* Reserved */ + ISS3, 1, + ISS4, 1, + ISS5, 1, + Offset (0x74), + , 2, /* Reserved */ + , 1, /* Reserved */ + TPEX, 1, + Offset (0x75), + BLST, 1, + LMIB, 1, + Offset (0x76), + ECSS, 4, + EOSS, 4 + } + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + /* Initialize AC power state */ + Store (KACS, \PWRS) + + /* Initialize LID switch state */ + Store (KLID, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + /* Battery Information Event */ + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* AC event */ + Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (ADP1, 0x80) // Status Change + } + + /* Lid event */ + Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (LID0, 0x80) // Status Change + } + + /* Battery Information Event */ + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery Status Event */ + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x80) // Status Change + } + + Method (ECWK, 1, NotSerialized) + { + EQEN = One + Notify (BAT0, 0x81) // Information Change + If (((Arg0 == 0x03) || (Arg0 == 0x04))) + { + Notify (SLPB, 0x02) // Device Wake + } + } + + Name (B0ST, Zero) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x08), + MB0S, 8 + } + + OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF) + Field (MBB0, ByteAcc, Lock, Preserve) + { + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16 + } + + Method (GBIF, 3, NotSerialized) + { + If (Arg2) + { + Arg1 [One] = 0xFFFFFFFF + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x04] = 0xFFFFFFFF + Arg1 [0x05] = Zero + Arg1 [0x06] = Zero + } + + Return (Arg1) + } + + Method (GBST, 4, NotSerialized) + { + Local0 = Zero + + If ((Arg1 & One)) + { + Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */ + Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */ + If (ACST) + { + If ((Arg1 & 0x20)) + { + Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */ + } + } + + Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */ + If ((Local1 >= 0x8000)) + { + If ((Local0 & One)) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = Zero + } + } + + If (Arg2) + { + Local1 *= Local3 + Divide (Local1, 0x03E8, Local1) + } + } + Else + { + Local0 = Zero + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3 [Zero] = Local0 + Arg3 [One] = Local1 + Arg3 [0x02] = Local2 + Arg3 [0x03] = Local3 + Return (Arg3) + } + + Name (ACST, One) + Device (ADP1) + { + Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + Method (_PSR) // _PSR: Power Source + { + Return (\PWRS) + } + Method (_STA) // _STA: Status + { + Return (0x0F) + } + } + + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B0ST) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (B0IP, Package (0x0D) + { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0x00000000, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0x00000000 /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */ + While ((Local6)) + { + Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */ + If ((Local1 & 0x08)) + { + Local6 = Zero + } + } + + Return (GBIF (Zero, B0IP, Local6)) + } + + Name (B0SP, Package (0x04) + { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP [Zero]) ^ One) + Return (GBST (Zero, MB0S, Local0, B0SP)) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl new file mode 100644 index 0000000..e145a2b --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero) +Field (SANV, AnyAcc, Lock, Preserve) +{ + BRTL, 8 +} + +Scope (\_SB.PCI0) +{ + Device (GFX0) + { + Name (_ADR, 0x00020000) // _ADR: Address + + Device (DD1F) + { + Method (_ADR, 0, Serialized) // _ADR: Address + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + Return (Package (0x0C) + { + 0x50, + 0x32, + 0x0A, + 0x14, + 0x1E, + 0x28, + 0x32, + 0x3C, + 0x46, + 0x50, + 0x5A, + 0x64 + }) + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (((Arg0 >= Zero) && (Arg0 <= 0x64))) + { + BRTL = Arg0 + } + } + + Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current + { + Return (BRTL) /* \BRTL */ + } + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000..90e75f2 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) /* Lid Device */ + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + + Method (_LID) // _LID: Lid Status + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000..f16707e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000..f38b0b8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,218 @@ +chip soc/intel/skylake + + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x60-0x66 + register "gen1_dec" = "0x00000061" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "SaGv" = "0" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root Ports 1, 9 and 10 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + +# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. +# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000..c9bcb7d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h new file mode 100644 index 0000000..4d98da1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */ +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */ +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */ +_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */ +_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */ +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ +_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ +_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */ +_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */ +_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */ +_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */ +_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */ +_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */ +_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */ +_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */ +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */ +_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */ +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */ +_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */ +_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */ +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */ +_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */ +_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */ +_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */ +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */ +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */ +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */ +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */ +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */ +_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */ +_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */ + +_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */ +_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */ +_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */ +_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */ +_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */ +_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */ +_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */ +_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */ +_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */ +_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */ +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */ +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */ +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */ +_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */ +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */ +_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */ +_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */ +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */ +_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */ +_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */ +_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */ +_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */ +_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */ +_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */ +_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */ +_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */ +}; + +#endif + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000..8cd5f97 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Purism SPC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */ + AZALIA_SUBVENDOR(0x0, 0x10251037), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90172120), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x02211030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000..86ef5af --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Gerrit-Change-Number: 35523 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron Gerrit-MessageType: newchange

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coreboot-gerrit September 2019