coreboot-gerrit March 2019

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Change in ...coreboot[master]: cpu/amd/microcode: Search all containers
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30747 Change subject: cpu/amd/microcode: Search all containers ...................................................................... cpu/amd/microcode: Search all containers Currently, it’s aborted if the first file is not found. The commit was only tested with all microcode containers present in CBFS. If only one microcode update container is present, which is not the first, it is skipped. Change the return to continue to traverse all elements. Fixes: 83e4c5613 (cpu/amd/microcode: Update parser to use stock microcode blobs) Change-Id: I5195ff0334cf49cadc25de31822a9f2f2cd90490 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/cpu/amd/microcode/microcode.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30747/1 diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index e8ab175..622c6db 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -214,7 +214,7 @@ spin_unlock(romstage_microcode_cbfs_lock()); #endif #endif - return; + continue; } amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/30747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5195ff0334cf49cadc25de31822a9f2f2cd90490 Gerrit-Change-Number: 30747 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/mmio: Avoid pointer aliasing in write8()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31945 Change subject: arch/x86/mmio: Avoid pointer aliasing in write8() ...................................................................... arch/x86/mmio: Avoid pointer aliasing in write8() Don't literally dereference a pointer to `char`. Use array indexing instead to avoid aliasing rules. Otherwise, the compiler might treat any memory as clobbered. Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/include/arch/mmio.h 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31945/1 diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..790b699 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -45,7 +45,15 @@ static __always_inline void write8(volatile void *addr, uint8_t value) { - *((volatile uint8_t *)(addr)) = value; + /* + * Don't literally dereference a pointer to `char`. Use array + * indexing instead to avoid aliasing rules. Otherwise, the + * compiler might treat any memory as clobbered. + */ + volatile struct { + uint8_t reg[1]; + } *const ref = addr; + ref->reg[0] = value; } static __always_inline void write16(volatile void *addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/31945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Gerrit-Change-Number: 31945 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 10 Jun '23

10 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32078 Change subject: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 ...................................................................... mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 It was obsevred that the DEVSLP is keeping low in S3, and SDD is drawing some power, assert DEVSLP in S3 to indicate SSD to go into low power mode. Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32078/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5987abc..15038b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -410,6 +410,7 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_E5, 1, DEEP), }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Gerrit-Change-Number: 32078 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]device/pci_rom: Add ATRM method
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31502 Change subject: [WIP]device/pci_rom: Add ATRM method ...................................................................... [WIP]device/pci_rom: Add ATRM method Add ATRM method for AMD GPUs, which is similar to _ROM. As both functions seem to have identical arguments and return values, redirect ATRM to _ROM. Don't depend on VGA devices, but display devices, as some AMD dGPUs identify themself as PCI_CLASS_DISPLAY_OTHER. Needs test on platforms with AMD display devices. Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pci_rom.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31502/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..86c839c 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -272,8 +272,8 @@ { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ @@ -319,9 +319,21 @@ memcpy(cbrom, rom, cbrom_length); - /* write _ROM method */ + /* write ACPI methods */ acpigen_write_scope(scope); + + /* Nvidia uses _ROM */ acpigen_write_rom(cbrom, cbrom_length); + + /* AMD uses ATRM. Redirect ATRM to _ROM */ + acpigen_write_method_serialized("ATRM", 2); + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("_ROM"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* pop method */ + acpigen_pop_len(); /* pop scope */ } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Gerrit-Change-Number: 31502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Updated and converted to markdown doc from wiki on porting motherboards.
by Calvin (Code Review) 10 Jun '23

10 Jun '23

Calvin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31849 Change subject: Updated and converted to markdown doc from wiki on porting motherboards. ...................................................................... Updated and converted to markdown doc from wiki on porting motherboards. Some of the documentation from the wiki (https://www.coreboot.org/Motherboard_Porting_Guide) has been ported to markdown and updated as I was able to figure things out. Still a work in progress as there is more data from that page that I will need to convert as I work through it. If I get anywhere in my project of porting coreboot to an older Chromebook, I will document more of this process as I go. Signed-off-by: calvinrempel <calvin.rempel(a)gmail.com> Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 --- M Documentation/index.md A Documentation/porting/index.md A Documentation/porting/motherboard_probe.md 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31849/1 diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..32635f9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ * [Rookie Guide](lessons/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Porting](porting/index.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/porting/index.md b/Documentation/porting/index.md new file mode 100644 index 0000000..ed282e8 --- /dev/null +++ b/Documentation/porting/index.md @@ -0,0 +1,3 @@ +# Porting New Boards + +* [Motherboard Probing](motherboard_probe.md) diff --git a/Documentation/porting/motherboard_probe.md b/Documentation/porting/motherboard_probe.md new file mode 100644 index 0000000..7562f7c --- /dev/null +++ b/Documentation/porting/motherboard_probe.md @@ -0,0 +1,131 @@ +Motherboard Porting Guide +========================= + +Please note that this guide is very much a work in progress. + +Finding out What You Have +------------------------- + +### Tools +To begin the process of porting a motherboard to coreboot, you first +need to determine what all is on it: the chipset (ie, North and South +Bridge), Flash Rom, etc. To do this, you will need a suite of +tools provided by the coreboot project, as well as some that can be +found more readily in various repositories. + +For the sake of this page, it will be assumed you are using Debian or +Ubuntu. + +#### Build Environment +If you have not already done so, get your basic build environment +installed: + + $ sudo apt install build-essential git cvs subversion + +#### Probing Utilities - From Repos +Next, a number of utilities will need to be installed which will be used +later for probing the system as well as some dev libraries which will be +used in building some of the tools in the next step.These should be +available in your distro's repo: + + $ sudo apt install pciutils pciutils-dev flashrom acpitool \ + usbutils acpidump + +#### Probing Utilities - From Source +Once the base build system in place and what utilities along with what +libraries you can glean from your distro's repositories, it is time to +build some tools from source. If you have not already done so, checkout +the git repo as described in "[Rookie Guide: Lesson 1]". + +Once you have synced the coreboot repo, cd into the utilities folder: + + $cd coreboot/util + +##### superiotool + + $ cd ./superiotool + $ make + $ sudo make install + $ cd .. + +##### inteltool + + $ cd ./inteltool + $ make + $ sudo make install + $ cd .. + +##### ectool + + $ cd ./ectool + $ make + $ make install + $ cd .. + +##### dmidecode + + $ cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode \ + co dmidecode + $ cd dmidecode + $ make + $ sudo make install + $ cd .. + +##### msrtool + + $ cd ./msrtool + $ ./configure + $ make + $ sudo make install + $ cd .. + +##### nvramtool + + $ cd ./nvramtool + $ make + $ sudo make install + +##### acpica-unix + + $ wget http://deb.debian.org/debian/pool/main/a/acpica-unix/acpica-unix_20181213.o… + $ tar -xaf acpica-unix_20181213.orig.tar.gz + $ cd ./acpica-unix-2018-12-13/ + $ make + $ sudo make install + +### Probe the Board +Now we will begin to probe the board to see what we can find out about +it. First, become root: + + $ sudo su + +Then load the msr module into the kernel: + + $ sudo modprobe msr + +Finally, we probe the board: + + $ lspci -nnvvvxxxx > lspci.log 2> lspci.err.log + $ lsusb -vvv > lsusb.log 2> lsusb.err.log + $ superiotool -deV > superiotool.log 2> superiotool.err.log + $ inteltool -a > inteltool.log 2> inteltool.err.log + $ ectool -i > ectool.log 2> ectool.err.log + $ msrtool > msrtool.log 2> msrtool.err.log + $ dmidecode > dmidecode.log 2> dmidecode.err.log + $ biosdecode > biosdecode.log 2> biosdecode.err.log + $ nvramtool -x > nvramtool.log 2> nvramtool.err.log + $ dmesg > dmesg.log 2> dmesg.err.log + $ acpidump > acpidump.log 2> acpidump.err.log + $ for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" \ + > pin_"$(basename "$x")"; done + $ for x in /proc/asound/card0/codec#*; do cat "$x" > \ + "$(basename "$x")"; done + $ cat /proc/cpuinfo > cpuinfo.log 2> cpuinfo.err.log + $ cat /proc/ioports > ioports.log 2> ioports.err.log + $ cat /sys/class/input/input*/id/bustype > input_bustypes.log + $flashrom -V -p internal:laptop=force_I_want_a_brick > \ + flashrom_info.log 2> flashrom_info.err.log + $ flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > \ + flashrom_read.log 2> flashrom_read.err.log + +[Rookie Guide: Lesson 1]: https://doc.coreboot.org/lessons/lesson1.html -- To view, visit https://review.coreboot.org/c/coreboot/+/31849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 Gerrit-Change-Number: 31849 Gerrit-PatchSet: 1 Gerrit-Owner: Calvin <calvin.rempel(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32082 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd reformatting Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 --- M src/arch/x86/acpi.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-q35/Kconfig 3 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32082/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..7bbbd2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -38,7 +38,6 @@ */ #include <console/console.h> -#include <string.h> #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..af5dddd 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,6 +253,10 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if (!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *) current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; @@ -322,6 +328,16 @@ }; } + if (rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 Gerrit-Change-Number: 32082 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Use understandable values for PWM backlight
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30567 Change subject: nb/intel/sandybridge: Use understandable values for PWM backlight ...................................................................... nb/intel/sandybridge: Use understandable values for PWM backlight This gets rid of setting the register values from the devicetree and makes it possible to use sensible values in the devicetree. TODO update autoport. Untested Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t520/variants/t520/devicetree.cb M src/mainboard/lenovo/t520/variants/w520/devicetree.cb M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/gma.c 31 files changed, 93 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30567/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 226ec04..4a7edc9 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "2" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001312" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,8 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x13121312" + register "pwm_freq" = "200" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index def3d1d..24cfe9a 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 07be8e7..05d7b34 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -15,8 +15,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + register "pwm_freq" = "953" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index eacfe57..d47684c 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -17,6 +17,9 @@ # Set backlight PWM values register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "pwm_freq" = "1041" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 0fdb55e..446c822 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -17,8 +17,8 @@ # For native gfx register "gfx.use_spread_spectrum_clock" = "0" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 753d286..bf3f03f 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000437" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 041b5e8..6bd4885 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 9f9efbb..adacbd9 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 9d6fe3f..c9151fc 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000385" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "26" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 56d90d3..c8fb413 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000d9c" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 2384e71..604d4bc 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000263" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "94" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 3e1f308..af14415 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -13,7 +12,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 35135a9..ddf7baa 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000060" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "600" - register "gpu_pch_backlight" = "0x041e041e" + register "pwm_freq" = "926" + register "duty_cycle" = "10" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index bed406a..0b7722e 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index a090308..809fee2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 5eb92bc..ddd4289 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 56e7f63..69e104a 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e69f727..3abf890 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -10,7 +10,8 @@ register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms - register "gpu_cpu_backlight" = "0x03d2" + register "duty_cycle" = "63" + device domain 0 on device pci 00.0 on diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 97350f3..671b45d 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 33b9368..3df91b9 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 4dcdc9d..20404c0 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 7a72b26..4af6c42 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -18,8 +18,8 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ccdff7c..2a3a30f 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cb88a7f..c60ac62 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001155" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "300" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 969ae38..85f3fbc 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a31be72..9a4866d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 4455fdb..eab2401 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x0000001a" - register "gpu_pch_backlight" = "0x002e0000" + register "pwm_freq" = "21229" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index b51c86e..ffc8b2e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000ac8" - register "gpu_pch_backlight" = "0x13120000" + register "pwm_freq" = "200" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index ed0d997..617e69d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_LGA1155 device lapic 0x0 on diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824..ebead59 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -37,8 +37,8 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + u32 pwm_freq; + u8 duty_cycle; /* * Maximum memory clock. diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9..c5cdd41 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -528,6 +528,17 @@ gtt_write(0xe4f24, 0x0ff803cf); } +static uint32_t get_raw_freq_mhz(void) +{ + uint32_t pp_divisor = (gtt_read(PCH_PP_DIVISOR) >> 8) & 0xffffff; + return (pp_divisor + 1) * 2 / 100; +} + +static uin32_t pwm_freq_to_reg(uint32_t pwm_freq) +{ + return get_raw_freq_mhz * 1000000 / (pwm_freq * 128); +} + static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_sandybridge_config *conf = dev->chip_info; @@ -582,14 +593,25 @@ gtt_write(0xc7210, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { + if (conf->pwm_freq) + { + uint32_t pwm_reg = pwm_freq_to_reg(conf->pwm_freq); + /* Set the pwm frequency */ gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + reg = pwm_reg << 16; + /* PCH PWM freq override */ + uint8_t duty_cycle = conf->duty_cycle; + if (duty_cycle == 0 || duty_cycle > 100) { + printk(BIOS_WARNING, "GMA: Invalid duty cycle, using 100%\n"); + duty_cycle = 100; + } + if (gtt_read(0xc8250) & (1 << 30)) + reg |= pwm_reg * duty_cycle / 100; + /* PCH PWM backlight freq + duty cycle*/ + gtt_write(0xc8254, reg); + /* CPU PWM backlight duty cycle */ + gtt_write(0x48250, (1 << 31)); + gtt_write(0x48254, pwm_reg * duty_cycle / 100); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Gerrit-Change-Number: 30567 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30693 Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t This avoid a lot of casts. Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cbmem.c M src/cpu/allwinner/a10/cbmem.c M src/cpu/allwinner/a10/ram_segs.h M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/via/vx900/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c D src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_broadwell_de/memmap.c D src/soc/intel/icelake/cbmem.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 67 files changed, 133 insertions(+), 176 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30693/1 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 73967e1..bb3c1ef 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -17,16 +17,16 @@ #if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - static void *cbmem_top_backup; - void *top_backup; + static uintptr_t cbmem_top_backup; + uintptr_t top_backup; if (ENV_RAMSTAGE && cbmem_top_backup != NULL) return cbmem_top_backup; /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); + top_backup = restore_top_of_low_cacheable(); if (ENV_RAMSTAGE) cbmem_top_backup = top_backup; diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c index a4c563a3..42331a6 100644 --- a/src/cpu/allwinner/a10/cbmem.c +++ b/src/cpu/allwinner/a10/cbmem.c @@ -20,7 +20,7 @@ #include "ram_segs.h" #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return a1x_get_cbmem_top(); } diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h index fa915cd..4b4f0e5 100644 --- a/src/cpu/allwinner/a10/ram_segs.h +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -22,21 +22,21 @@ /* * Put CBMEM at top of RAM */ -static inline void *a1x_get_cbmem_top(void) +static inline uintptr_t a1x_get_cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } /* * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. */ -static inline void *a1x_get_cbfs_cache_top(void) +static inline uintptr_t a1x_get_cbfs_cache_top(void) { /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ return a1x_get_cbmem_top() - (16 << 20); } -static inline void *a1x_get_cbfs_cache_base(void) +static inline uintptr_t a1x_get_cbfs_cache_base(void) { return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; } diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 57bd2fc..7d62064 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -89,9 +89,9 @@ return cc6_size; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); + return topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 688f357..8d39892 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,7 +65,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..82cb95d 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -22,5 +22,5 @@ /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..4dcd6b4 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -24,5 +24,5 @@ * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6..116d82d 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 1fbb553..49db504 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -56,7 +56,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -89,7 +89,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB, diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f6416..e0dfddb 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -199,7 +199,7 @@ * @param hob_list_ptr pointer to the start of the hob list * @return pointer to the start of the FSP reserved memory or NULL if not found. */ -void *find_fsp_reserved_mem(void *hob_list_ptr) +uintptr_t find_fsp_reserved_mem(void *hob_list_ptr) { EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = @@ -209,7 +209,7 @@ if (fsp_reserved_mem == NULL) return NULL; - return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); + return ((uintptr_t)fsp_reserved_mem->PhysicalStart); } #endif /* FSP_RESERVE_MEMORY_SIZE */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 317b2c9..a3c878e 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -61,7 +61,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..e7f04cc 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -74,7 +74,7 @@ * below 4GiB. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/imd.h b/src/include/imd.h index 6575312..cd2d297 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -59,7 +59,7 @@ * to be called at least once before any other imd related functions * can be used. */ -void imd_handle_init(struct imd *imd, void *upper_limit); +void imd_handle_init(struct imd *imd, uintptr_t upper_limit); /* * Initialize a handle with a shallow recovery. This function doesn't diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..f353681 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..143f617 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -132,11 +132,10 @@ e->id = id; } -static void imdr_init(struct imdr *ir, void *upper_limit) +static void imdr_init(struct imdr *ir, uintptr_t upper_limit) { - uintptr_t limit = (uintptr_t)upper_limit; /* Upper limit is aligned down to 4KiB */ - ir->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); + ir->limit = ALIGN_DOWN(upper_limit, LIMIT_ALIGN); ir->r = NULL; } @@ -396,10 +395,10 @@ } /* Initialize imd handle. */ -void imd_handle_init(struct imd *imd, void *upper_limit) +void imd_handle_init(struct imd *imd, uintptr_t upper_limit) { imdr_init(&imd->lg, upper_limit); - imdr_init(&imd->sm, NULL); + imdr_init(&imd->sm, 0); } void imd_handle_init_partial_recovery(struct imd *imd) @@ -411,7 +410,7 @@ if (imd->lg.limit == 0) return; - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); /* Initialize root pointer for the large regions. */ imdr = &imd->lg; @@ -468,7 +467,7 @@ return 0; fail: - imd_handle_init(imd, (void *)imdr->limit); + imd_handle_init(imd, imdr->limit); return -1; } @@ -495,7 +494,7 @@ /* Tear down any changes on failure. */ if (imdr_recover(&imd->sm) != 0) { - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); return -1; } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index f26ca6c..6c3ac57 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -59,7 +59,7 @@ return discovered; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize() << 20); + return (uintptr_t)_dram + (probe_ramsize() << 20); } diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index dea96f2..973eecd 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -50,7 +50,7 @@ return tomk; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (qemu_get_memory_size() * 1024); + return qemu_get_memory_size() * 1024; } diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b80..4391cdb 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,10 +15,9 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 1b86012..f16cf9a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -23,7 +23,7 @@ #include <program_loading.h> #include "e7505.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -32,7 +32,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -59,7 +59,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 675a6f4..771d331 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -37,7 +37,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); + return smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index af1a46d..1bb2031 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -117,10 +117,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -145,7 +145,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d3e88f2..2c8217e 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -30,7 +30,7 @@ return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)smm_region_start(); + return smm_region_start(); } diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 3362d93..1c09857 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -24,7 +24,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -64,7 +64,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -88,7 +88,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index fd37aea..b58b3c6 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -70,10 +70,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -110,7 +110,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index baf087e..d80ba07 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -32,9 +32,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -60,7 +60,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 21b926b..bfdfd60 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -130,10 +130,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } @@ -159,7 +159,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 00e3e78..4fc4407 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -38,9 +38,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -62,7 +62,7 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 6484326..6537427 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -128,10 +128,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -156,7 +156,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..e255265 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -113,7 +113,7 @@ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t tolm; uintptr_t fb_size; @@ -122,7 +122,7 @@ fb_size = vx900_get_chrome9hd_fb_size (); if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) - return NULL; + return 0; - return (void *)((tolm - fb_size) << 20); + return ((tolm - fb_size) << 20); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..8172a76 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -398,7 +398,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..4302811 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -57,7 +57,7 @@ *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -65,14 +65,14 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9f8aed8..35a9ba9 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -160,7 +160,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..a44ad5c 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -19,9 +19,9 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, + return min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, 4ULL * GiB); } diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..af76722 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..4f7a9e8 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -25,11 +25,11 @@ #include <soc/systemagent.h> #include <soc/pci_devs.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { const struct device *dev; const config_t *config; - void *tolum = (void *)sa_get_tseg_base(); + uintptr_t tolum = sa_get_tseg_base(); if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) return tolum; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 4f4f9f5..9db1c99 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -252,7 +252,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f1131f6..7d3a98b 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -23,7 +23,7 @@ return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a52d3b1..6596fdf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -252,7 +252,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..03371b5 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -81,7 +81,7 @@ return 0; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { char *smm_base; size_t smm_size; @@ -115,5 +115,5 @@ */ smm_region((void **)&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 175c20c..3166627 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -36,7 +36,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index afc8216..bd3cdc4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -56,7 +56,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c deleted file mode 100644 index 300556a..0000000 --- a/src/soc/intel/cannonlake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..c2caa93 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -294,7 +294,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -309,5 +309,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (uintptr_t)ebda_cfg.tolum_base; } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 246e0ea..33bc256 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..0d55357 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -157,7 +157,7 @@ /* Get SoC reserve memory size as per user selection */ reserved_mmio_size = soc_reserved_mmio_size(); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..6c38f30 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -59,7 +59,10 @@ power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +uintptr_t cbmem_top(void) +{ + return top_of_32bit_ram(); +} static inline uintptr_t smm_region_start(void) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 34fd7bb..f19505e 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -166,7 +166,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 1886c6f..ff9ce5d 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -35,7 +35,7 @@ * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..8ec6d99 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <drivers/intel/fsp1_0/fsp_util.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c deleted file mode 100644 index 4f44777..0000000 --- a/src/soc/intel/icelake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..8e1d4d6 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -293,7 +293,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -308,5 +308,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 432cae5..9968b3d 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index d67856c..9a2706d 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/reg_access.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t top_of_memory; @@ -30,5 +30,5 @@ top_of_memory -= 0x10000; /* Return the top of memory */ - return (void *)top_of_memory; + return top_of_memory; } diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 23051bd..52962be 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -65,7 +65,7 @@ die("Unable to initialize postcar frame.\n"); /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..e464bdc 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -335,7 +335,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -350,5 +350,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..5030eb8 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -161,7 +161,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565..7d0aad6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a51..d11816a 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497..21f8819 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { static uintptr_t addr; @@ -32,5 +32,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cc..db859e8 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -34,5 +34,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db6..d86b113 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -35,5 +35,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a..5897f18 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return ((uintptr_t)4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2..105e178 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495..dc02577 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e8..4606c19 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include <soc/cpu.h> #include <stddef.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return (get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de8..523e62c 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 2ee400a..7e0c4d5 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,7 +13,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t base; size_t size; @@ -23,5 +23,5 @@ base = 0x80000000; size = 128 * MiB; - return (void *)(base + size); + return (base + size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Gerrit-Change-Number: 30693 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants: Add DPTF based charge control
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30723 Change subject: mb/google/sarien/variants: Add DPTF based charge control ...................................................................... mb/google/sarien/variants: Add DPTF based charge control Add DPTF based input chargning current throttling based on temperature. BRANCH=None BUG=b:122483425 TEST=Built for sarien Change-Id: If01fea731926ec29ca5a0595b875acce9b1f5a2f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30723/1 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 2d35878..8f8cde5 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -27,7 +27,15 @@ #define DPTF_TSR1_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 2d35878..8f8cde5 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -27,7 +27,15 @@ #define DPTF_TSR1_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If01fea731926ec29ca5a0595b875acce9b1f5a2f Gerrit-Change-Number: 30723 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019