coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

1 participants
2751 discussions

Change in coreboot[master]: util/sconfig: Add helper function for allocating memory
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26738 ) Change subject: util/sconfig: Add helper function for allocating memory ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73872/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27983/ : SUCCESS -- To view, visit https://review.coreboot.org/26738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db Gerrit-Change-Number: 26738 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 04:30:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/sconfig: Get rid of nextdev member in struct device
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26741 ) Change subject: util/sconfig: Get rid of nextdev member in struct device ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73873/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27984/ : SUCCESS -- To view, visit https://review.coreboot.org/26741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2 Gerrit-Change-Number: 26741 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 04:29:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: util/sconfig: Get rid of bus pointer in device structure
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26736 ) Change subject: util/sconfig: Get rid of bus pointer in device structure ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73871/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27982/ : SUCCESS -- To view, visit https://review.coreboot.org/26736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Gerrit-Change-Number: 26736 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 04:25:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/sconfig: Re-factor emitting of headers to static.c
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26726 ) Change subject: util/sconfig: Re-factor emitting of headers to static.c ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73869/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27980/ : SUCCESS -- To view, visit https://review.coreboot.org/26726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0 Gerrit-Change-Number: 26726 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 04:23:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73870/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27981/ : SUCCESS -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 7 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 04:21:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/apollolake: Add Page table mapping for System Memory
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26745 ) Change subject: soc/intel/apollolake: Add Page table mapping for System Memory ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73864/ : SUCCESS -- To view, visit https://review.coreboot.org/26745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Gerrit-Change-Number: 26745 Gerrit-PatchSet: 2 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 02:55:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Add ACPI device name lookup
by Marc Jones (Code Review) 01 Jun '18

01 Jun '18

Marc Jones has submitted this change and it was merged. ( https://review.coreboot.org/26698 ) Change subject: soc/amd/stoneyridge: Add ACPI device name lookup ...................................................................... soc/amd/stoneyridge: Add ACPI device name lookup Add the ACPI devices defined in ASL to the soc_acpi_name() lookup function. BUG=b:80280671 TEST=Add ACPI method to specific GPP bridge. Boot and verify method with ACPI dump. Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/26698 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/chip.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved Kevin Chiu: Looks good to me, but someone else must approve diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 3b73a05..9ca2db7 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -82,6 +82,18 @@ return NULL; switch (dev->path.pci.devfn) { + case PCIE0_DEVFN: + return "PBR4"; + case PCIE1_DEVFN: + return "PBR5"; + case PCIE2_DEVFN: + return "PBR6"; + case PCIE3_DEVFN: + return "PBR7"; + case PCIE4_DEVFN: + return "PBR8"; + case HDA1_DEVFN: + return "AZHD"; case EHCI1_DEVFN: return "EHC0"; case LPC_DEVFN: -- To view, visit https://review.coreboot.org/26698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Gerrit-Change-Number: 26698 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/apollolake: Add Page table mapping for System Memory
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26745 ) Change subject: soc/intel/apollolake: Add Page table mapping for System Memory ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73863/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27976/ : SUCCESS -- To view, visit https://review.coreboot.org/26745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Gerrit-Change-Number: 26745 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 01:52:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/apollolake: Add Page table mapping for System Memory
by Hannah Williams (Code Review) 01 Jun '18

01 Jun '18

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/26745 Change subject: soc/intel/apollolake: Add Page table mapping for System Memory ...................................................................... soc/intel/apollolake: Add Page table mapping for System Memory Since we do not know before hand the memory range initialized by FSP memory init until it completes and as memory gets accessed from within FSP memory init to migrate FSP from CAR to memory, we need to add this mapping in coreboot. Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/soc/intel/apollolake/glk_page_map.txt M src/soc/intel/apollolake/romstage.c 2 files changed, 1 insertion(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26745/1 diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e4c51b0..a4844ef 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,3 +1,4 @@ +0x00000000, 0x100000000, WB, # RAM 0xd0000000, 0x100000000, UC, NX # All of MMIO # Maximum 16MiB of mmio SPI flash decode. 0xff000000, 0x100000000, WP, # memory-mapped SPI diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index cee23b6..c50134f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -248,13 +248,6 @@ tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); - /* Ensure TSEG has mappings. */ - if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) { - if (paging_identity_map_addr(tseg_base, smm_size, PAT_WB)) - printk(BIOS_ERR, "Unable to map TSEG: %lx--%lx\n", - tseg_base, tseg_base + smm_size); - } - run_postcar_phase(&pcf); } @@ -343,40 +336,6 @@ #endif } -static void prepare_fspm_pages(void) -{ - const size_t mib128 = 128 * MiB; - uintptr_t base; - /* All in units of MiB */ - size_t mem_sz; - size_t iohole_sz; - size_t low_mem_sz; - - mem_sz = memory_in_system_in_mib(); - - if (!mem_sz) { - printk(BIOS_ERR, "No memory in system! FSP will hang...\n"); - return; - } - - iohole_sz = iohole_in_mib(); - - /* Mark pages as WB where FSP will write. One region will be in cbmem, - but it's not clear what else FSP is writing to. Try to make the best - calculation. */ - low_mem_sz = 4 * (GiB / MiB) - iohole_sz; - - if (low_mem_sz > mem_sz) - low_mem_sz = mem_sz; - - /* Assume all accesses are within 128MiB of the crude low memory - calculation above. */ - base = low_mem_sz * MiB - mib128; - if (paging_identity_map_addr(base, mib128, PAT_WB)) - printk(BIOS_ERR, "Unable to map %lx--%lx\n", base, - base + mib128); -} - void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { struct region_device rdev; @@ -430,8 +389,6 @@ car_set_var(fsp_version, version); - if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) - prepare_fspm_pages(); } __weak -- To view, visit https://review.coreboot.org/26745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Gerrit-Change-Number: 26745 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

1 0

Change in coreboot[master]: google/kukui: Add MediaTek MT8183 reference board
by build bot (Jenkins) (Code Review) 01 Jun '18

01 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26722 ) Change subject: google/kukui: Add MediaTek MT8183 reference board ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73862/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27975/ : SUCCESS -- To view, visit https://review.coreboot.org/26722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I08644892d34925574f791b000b0035d5afad7022 Gerrit-Change-Number: 26722 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Jun 2018 01:40:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2018