coreboot-gerrit January 2018

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Change in coreboot[master]: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for ...
by build bot (Jenkins) (Code Review) 02 Jan '18

02 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23056 ) Change subject: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for Nautilus ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19875/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65133/ : SUCCESS -- To view, visit https://review.coreboot.org/23056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Gerrit-Change-Number: 23056 Gerrit-PatchSet: 3 Gerrit-Owner: Anonymous Coward #1001830 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 08:59:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for ...
by Rizwan Qureshi (Code Review) 02 Jan '18

02 Jan '18

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Change in coreboot[master]: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for ...
by Rizwan Qureshi (Code Review) 02 Jan '18

02 Jan '18

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/23056 ) Change subject: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for Nautilus ...................................................................... Patch Set 2: (5 comments) https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl: https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… PS2, Line 18: /* Define two ports for CIO2 device where endpoint of port0 : is connected to CAM0 and endpoint of port1 is connected to CAM1 */ I imagine there is only one port and endpoint where only CAM0 is connected. https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… PS2, Line 25: Package () { "port1", "PRT1" }, not needed, there is only one sensor. https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… PS2, Line 52: Name (PRT1, Package () { : ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), : Package () { : Package () { "port", 1 }, /* csi 1 */ : }, : ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), : Package () { : Package () { "endpoint0", "EP10" }, : } : }) Do we need this? Only one sensor on MIPI. https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/mipi_camera.asl: https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… PS2, Line 16: Scope (\_SB.PCI0.I2C2) : { : Device (PMIC) : { : Name (_HID, "INT3472") /* _HID: Hardware ID */ : Name (_UID, Zero) /* _UID: Unique ID */ : Name (_DDN, "TPS68470 PMIC") /* _DDN: DOS Device Name */ : Name (CAMD, 0x64) : : Method (_STA, 0, NotSerialized) /* _STA: Status */ : { : Return (0x0F) : } : : Method (PMON, 0, Serialized) { : /* : * Turn on 3V3_VDD. It takes around There is a lot of code which is a copy of src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/mipi_camera.asl, specially the PMIC. Can we utilize the common code from that file. Things may will turn murky. Feel free to split the original file. https://review.coreboot.org/#/c/23056/2/src/mainboard/google/poppy/variants… PS2, Line 338: /* Increment only if VSIC < 4 */ : If (LLess (VSIC, 4)) { For nautilus, this reference count will come down to 3 ideally (CAM0, VCM, NVM). hmmmm...if we decide to split the common code then this value should also be configurable or derived from somewhere. Can't think of a right now. -- To view, visit https://review.coreboot.org/23056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Gerrit-Change-Number: 23056 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001830 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 08:52:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for ...
by Anonymous Coward (Code Review) 02 Jan '18

02 Jan '18

Hello Rajmohan Mani, Rizwan Qureshi, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23056 to look at the new patch set (#3). Change subject: mainboard/google/poppy/variants/nautilus - MIPI camera asl files for Nautilus ...................................................................... mainboard/google/poppy/variants/nautilus - MIPI camera asl files for Nautilus * added IMX258 sensor entity * added DW9807 VCM control entity * enabled CIO2 and IMGu in devicetree.cb Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: andy yeh <andy.yeh(a)intel.corp-partner.google.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/nautilus/devicetree.cb A src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl A src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/mipi_camera.asl 5 files changed, 726 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/23056/3 -- To view, visit https://review.coreboot.org/23056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Gerrit-Change-Number: 23056 Gerrit-PatchSet: 3 Gerrit-Owner: Anonymous Coward #1001830 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings
by build bot (Jenkins) (Code Review) 02 Jan '18

02 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23060 ) Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19874/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65132/ : SUCCESS -- To view, visit https://review.coreboot.org/23060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Gerrit-Change-Number: 23060 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 05:29:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings
by Gaggery Tsai (Code Review) 02 Jan '18

02 Jan '18

Hello Kane Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/23060 to look at the new patch set (#2). Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings ...................................................................... soc/intel/skylake: Override KBL-U/R IccMax settings According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeroni/Pentium are different. This patch overrides the IccMax settings for KBL-U/R since device tree could not handle all of them and it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+-------+-------+ | IccMax | 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | 31A | 31A | | | | 32A(i3/i5) | 31A | 31A | +----------------+-------------+---------------+-------+-------+ BUG=b:71369428 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/vr_config.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/23060/2 -- To view, visit https://review.coreboot.org/23060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Gerrit-Change-Number: 23060 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings
by Kane Chen (Code Review) 02 Jan '18

02 Jan '18

Kane Chen has posted comments on this change. ( https://review.coreboot.org/23060 ) Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/23060/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/23060/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 276: indent https://review.coreboot.org/#/c/23060/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 281: tab -- To view, visit https://review.coreboot.org/23060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Gerrit-Change-Number: 23060 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 04:57:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings
by build bot (Jenkins) (Code Review) 02 Jan '18

02 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23060 ) Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19873/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65131/ : SUCCESS -- To view, visit https://review.coreboot.org/23060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Gerrit-Change-Number: 23060 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 04:44:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings
by Gaggery Tsai (Code Review) 02 Jan '18

02 Jan '18

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/23060 Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings ...................................................................... soc/intel/skylake: Override KBL-U/R IccMax settings According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeroni/Pentium are different. This patch overrides the IccMax settings for KBL-U/R since device tree could not handle all of them and it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+-------+-------+ | IccMax | 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | 31A | 31A | | | | 32A(i3/i5) | 31A | 31A | +----------------+-------------+---------------+-------+-------+ BUG=b:71369428 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/vr_config.c 3 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/23060/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 24a239e..b1d882d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -272,6 +272,14 @@ for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + /* + * KBL-U/R CPUs are with a complicated setting matrix for IccMax + * that devicetree is unable to handle all of them with variants. + * Besides, it's inefficient to maintain the same code per variant. + * Hence, move the IccMax override to common code here. + */ + override_kbl_ur_icc_max(params); + /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 66b4a01..1f948e2 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -98,4 +98,6 @@ void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); +void override_kbl_ur_icc_max(void *params); + #endif diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index cfbd796..3f6cbe5 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -14,10 +14,19 @@ * */ +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> +#define KBLR_ICCMAX_SA_I7_U42 6 +#define KBLU_ICCMAX_SA_U22 4.5 +#define KBLR_ICCMAX_CORE_I7_U42 64 +#define KBLU_ICCMAX_CORE_U22 32 +#define KBLU_ICCMAX_CORE_PENTIUM_CELERON 29 + /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { [VR_SYSTEM_AGENT] = { @@ -84,6 +93,44 @@ }, }; +static uint16_t get_dev_id(device_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +void override_kbl_ur_icc_max(void *params) +{ + FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; + device_t dev = SA_DEV_ROOT; + uint16_t id = get_dev_id(dev); + + /* + * Iccmax table from Doc #55910 Section 7.2 DC Specifications, the + * Iccmax is the samse among KBL-Y but KBL-U/R. This function will + * identify device ID and set corresponding Iccmax values. + * +----------------+-------------+---------------+-------+-------+ + * | Domain/Setting | SA | IA | GTUS | GTS | + * +----------------+-------------+---------------+-------+-------+ + * | IccMax | 6A(U42) | 64A(U42) | 31A | 31A | + * | | 4.5A(Others)| 29A(P/C) | 31A | 31A | + * | | | 32A(i3/i5) | 31A | 31A | + * +----------------+-------------+---------------+-------+-------+ + */ + + if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) { /* KBL 4+2 SKU */ + vr_params->IccMax[VR_SYSTEM_AGENT] = VR_CFG_AMP(KBLR_ICCMAX_SA_I7_U42); + vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLR_ICCMAX_CORE_I7_U42); + } else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) { + dev = PCH_DEV_LPC; + id = get_dev_id(dev); + if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) /* Pentium or Celeron SKU */ + vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLU_ICCMAX_CORE_PENTIUM_CELERON); + else /* KBL 2+2 SKU */ + vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLU_ICCMAX_CORE_U22); + /* The IccMax of SA is the same for i3/i5/Celeron and Pentium */ + vr_params->IccMax[VR_SYSTEM_AGENT] = VR_CFG_AMP(KBLU_ICCMAX_SA_U22); + } +} void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { -- To view, visit https://review.coreboot.org/23060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Gerrit-Change-Number: 23060 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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Change in coreboot[master]: Fix gitconfig waiting for user input
by build bot (Jenkins) (Code Review) 02 Jan '18

02 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23059 ) Change subject: Fix gitconfig waiting for user input ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19872/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65130/ : SUCCESS -- To view, visit https://review.coreboot.org/23059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2aa722c052d24dcffa9688df09bcf8dc767bd0b6 Gerrit-Change-Number: 23059 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Thiessen <alex.thiessen.de(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2018 02:50:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit January 2018