coreboot-gerrit June 2017

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Change in coreboot[master]: [WIP]mb/lenovo/ref2012: Add reference design
by Patrick Rudolph (Code Review) 08 Jun '17

08 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20107 Change subject: [WIP]mb/lenovo/ref2012: Add reference design ...................................................................... [WIP]mb/lenovo/ref2012: Add reference design Add Thinkpad 2012 reference design. Will replace all the duplicates that exists in tree. Change-Id: I69d92090b3a6200513d50b787242cafe8c21594a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/mainboard/lenovo/ref2012/Kconfig A src/mainboard/lenovo/ref2012/Makefile.inc A src/mainboard/lenovo/ref2012/acpi/ec.asl A src/mainboard/lenovo/ref2012/acpi/platform.asl A src/mainboard/lenovo/ref2012/acpi/superio.asl A src/mainboard/lenovo/ref2012/acpi_tables.c A src/mainboard/lenovo/ref2012/cmos.default A src/mainboard/lenovo/ref2012/cmos.layout A src/mainboard/lenovo/ref2012/dsdt.asl A src/mainboard/lenovo/ref2012/gma-mainboard.ads A src/mainboard/lenovo/ref2012/gpio.c A src/mainboard/lenovo/ref2012/hda_verb.c A src/mainboard/lenovo/ref2012/mainboard.c A src/mainboard/lenovo/ref2012/romstage.c A src/mainboard/lenovo/ref2012/smihandler.c A src/mainboard/lenovo/ref2012/thermal.h 16 files changed, 888 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20107/1 diff --git a/src/mainboard/lenovo/ref2012/Kconfig b/src/mainboard/lenovo/ref2012/Kconfig new file mode 100644 index 0000000..c57da78 --- /dev/null +++ b/src/mainboard/lenovo/ref2012/Kconfig @@ -0,0 +1,55 @@ +if BOARD_LENOVO_XXX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_SOCKET_RPGA989 + select DRIVERS_RICOH_RCE822 + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select NO_UART_ON_SUPERIO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select ENABLE_VMX + select DRIVERS_LENOVO_HYBRID_GRAPHICS + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config VGA_BIOS_ID + string + default "8086,0166" + +config MMCONF_BASE_ADDRESS + hex + default 0xf8000000 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/lenovo/ref2012/Makefile.inc b/src/mainboard/lenovo/ref2012/Makefile.inc new file mode 100644 index 0000000..f37c6ca --- /dev/null +++ b/src/mainboard/lenovo/ref2012/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += romstage.c +romstage-y += gpio.c +ramstage-y += acpi_tables.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/ref2012/acpi/ec.asl b/src/mainboard/lenovo/ref2012/acpi/ec.asl new file mode 100644 index 0000000..3c7f89d --- /dev/null +++ b/src/mainboard/lenovo/ref2012/acpi/ec.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/ref2012/acpi/platform.asl b/src/mainboard/lenovo/ref2012/acpi/platform.asl new file mode 100644 index 0000000..efbf0ea --- /dev/null +++ b/src/mainboard/lenovo/ref2012/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/ref2012/acpi/superio.asl b/src/mainboard/lenovo/ref2012/acpi/superio.asl new file mode 100644 index 0000000..8964c36 --- /dev/null +++ b/src/mainboard/lenovo/ref2012/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/ref2012/acpi_tables.c b/src/mainboard/lenovo/ref2012/acpi_tables.c new file mode 100644 index 0000000..c5559af --- /dev/null +++ b/src/mainboard/lenovo/ref2012/acpi_tables.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = CTDP_SENSOR_ID; + + gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; + gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON; + + gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; + gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 5; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/ref2012/cmos.default b/src/mainboard/lenovo/ref2012/cmos.default new file mode 100644 index 0000000..ae19afb --- /dev/null +++ b/src/mainboard/lenovo/ref2012/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Enable +hybrid_graphics_mode=Integrated Only diff --git a/src/mainboard/lenovo/ref2012/cmos.layout b/src/mainboard/lenovo/ref2012/cmos.layout new file mode 100644 index 0000000..99f815e --- /dev/null +++ b/src/mainboard/lenovo/ref2012/cmos.layout @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 usb_always_on +#420 1 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/ref2012/dsdt.asl b/src/mainboard/lenovo/ref2012/dsdt.asl new file mode 100644 index 0000000..638592d --- /dev/null +++ b/src/mainboard/lenovo/ref2012/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/lenovo/ref2012/gma-mainboard.ads b/src/mainboard/lenovo/ref2012/gma-mainboard.ads new file mode 100644 index 0000000..736dce7 --- /dev/null +++ b/src/mainboard/lenovo/ref2012/gma-mainboard.ads @@ -0,0 +1,20 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/ref2012/gpio.c b/src/mainboard/lenovo/ref2012/gpio.c new file mode 100644 index 0000000..2e4897a --- /dev/null +++ b/src/mainboard/lenovo/ref2012/gpio.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/ref2012/hda_verb.c b/src/mainboard/lenovo/ref2012/hda_verb.c new file mode 100644 index 0000000..02f433f --- /dev/null +++ b/src/mainboard/lenovo/ref2012/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21f3, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa21f3), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/ref2012/mainboard.c b/src/mainboard/lenovo/ref2012/mainboard.c new file mode 100644 index 0000000..f0a4f3f --- /dev/null +++ b/src/mainboard/lenovo/ref2012/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +void h8_mainboard_init_dock(void) +{ +} + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/ref2012/romstage.c b/src/mainboard/lenovo/ref2012/romstage.c new file mode 100644 index 0000000..eb2d29e --- /dev/null +++ b/src/mainboard/lenovo/ref2012/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_def.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/pmh7/pmh7.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable TPM, EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, + (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1); +} + +void rcba_config(void) +{ + /* Disable unused devices (board specific, reserved only). + * FIXME: Test if reserved bits are read only. */ + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; +} + +/* FIXME: used T530 values here */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, 2 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/lenovo/ref2012/smihandler.c b/src/mainboard/lenovo/ref2012/smihandler.c new file mode 100644 index 0000000..7d61065 --- /dev/null +++ b/src/mainboard/lenovo/ref2012/smihandler.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + h8_usb_always_on(); + + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE.*/ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/ref2012/thermal.h b/src/mainboard/lenovo/ref2012/thermal.h new file mode 100644 index 0000000..945a2e4 --- /dev/null +++ b/src/mainboard/lenovo/ref2012/thermal.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LENOVO_REF2012_THERMAL_H +#define _LENOVO_REF2012_THERMAL_H + +/* Config TDP Sensor ID */ +#define CTDP_SENSOR_ID 0 /* PECI */ + +/* Config TDP Nominal */ +#define CTDP_NOMINAL_THRESHOLD_OFF 0 +#define CTDP_NOMINAL_THRESHOLD_ON 0 + +/* Config TDP Down */ +#define CTDP_DOWN_THRESHOLD_OFF 80 +#define CTDP_DOWN_THRESHOLD_ON 90 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif -- To view, visit https://review.coreboot.org/20107 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69d92090b3a6200513d50b787242cafe8c21594a Gerrit-Change-Number: 20107 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/*/cmos: Port USB Always On
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20106 ) Change subject: mb/lenovo/*/cmos: Port USB Always On ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10835/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55159/ : SUCCESS -- To view, visit https://review.coreboot.org/20106 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 Gerrit-Change-Number: 20106 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 09:46:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/cmos: Port USB Always On
by Patrick Rudolph (Code Review) 08 Jun '17

08 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20106 Change subject: mb/lenovo/*/cmos: Port USB Always On ...................................................................... mb/lenovo/*/cmos: Port USB Always On Port commit f1395d82: "ec/lenovo/h8: Add USB Always On" to other Thinkpad boards, as it seems to work fine on all generations. Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/l520/smihandler.c M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/smihandler.c M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/smihandler.c M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/cmos.default M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/mainboard/lenovo/x230/smihandler.c 21 files changed, 39 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/20106/1 diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default index 92dc2e1..f38beb4 100644 --- a/src/mainboard/lenovo/l520/cmos.default +++ b/src/mainboard/lenovo/l520/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index 3c450c7..4ea91d4 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -67,9 +67,10 @@ 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 1 e 1 usb_always_on +#420 1 r 0 unused 421 1 e 9 sata_mode -422 2 e 10 backlight +422 2 e 10 backlight # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index d2f7cb3..f0c7a04 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -72,6 +72,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 0fc3e55..d1fbcf6 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index 924b0f1..7e05a22 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -69,7 +69,8 @@ 418 1 e 1 sticky_fn 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode -#422 2 r 1 unused +422 1 e 1 usb_always_on +#423 1 r 1 unused # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index eff0daf..825a20b 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -71,6 +71,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 0fc3e55..d1fbcf6 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index e9e582d..c135113 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -69,7 +69,8 @@ 418 1 e 1 sticky_fn 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode -#422 2 r 1 unused +422 1 e 1 usb_always_on +#423 1 r 1 unused # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 2b6e6cd..471095e 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -107,6 +107,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index f7e38d2..a0abaed 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable backlight=Both +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index f116bab..40b3998 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -67,7 +67,8 @@ 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 1 e 1 usb_always_on +#420 1 r 0 unused 421 1 e 9 sata_mode 422 2 e 10 backlight diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 70ecab2..512e631 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -105,6 +105,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 92dc2e1..5c21f9c 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only +usb_always_on=Disable diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 3c450c7..4ea91d4 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -67,9 +67,10 @@ 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 1 e 1 usb_always_on +#420 1 r 0 unused 421 1 e 9 sata_mode -422 2 e 10 backlight +422 2 e 10 backlight # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index c48cf3d..3fa8e30 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -107,6 +107,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 92dc2e1..f38beb4 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index cdcc896..c31a905 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -67,9 +67,10 @@ 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 1 e 1 usb_always_on +#420 1 r 0 unused 421 1 e 9 sata_mode -422 2 e 10 backlight +422 2 e 10 backlight # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index c7ca206..1dfd87e 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -107,6 +107,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index f7e38d2..a0abaed 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable backlight=Both +usb_always_on=Disable \ No newline at end of file diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 3766453..b0c9e06 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -67,9 +67,10 @@ 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 1 e 1 usb_always_on +#420 1 r 0 unused 421 1 e 9 sata_mode -422 2 e 10 backlight +422 2 e 10 backlight # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 09dcbf2..4572cae 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -71,6 +71,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ -- To view, visit https://review.coreboot.org/20106 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 Gerrit-Change-Number: 20106 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/intel/cannonlake: Use common GPIO driver
by Lijian Zhao (Code Review) 08 Jun '17

08 Jun '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/20074 ) Change subject: soc/intel/cannonlake: Use common GPIO driver ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/20074/1/src/soc/intel/cannonlake/include/so… File src/soc/intel/cannonlake/include/soc/gpio_defs.h: https://review.coreboot.org/#/c/20074/1/src/soc/intel/cannonlake/include/so… PS1, Line 151: #define GPP_F0_IRQ 0x0 Typo? IRQ 0 always revered for timer irq. https://review.coreboot.org/#/c/20074/1/src/soc/intel/cannonlake/include/so… PS1, Line 199: #define GPP_H1_IRQ 0x48 extra tab here? -- To view, visit https://review.coreboot.org/20074 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5 Gerrit-Change-Number: 20074 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 09:18:56 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: riscv: Bug in fetch instruction
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20105 ) Change subject: riscv: Bug in fetch instruction ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/55158/ : SUCCESS -- To view, visit https://review.coreboot.org/20105 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Gerrit-Change-Number: 20105 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 09:02:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: riscv: Bug in fetch instruction
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20105 ) Change subject: riscv: Bug in fetch instruction ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55157/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10834/ : SUCCESS -- To view, visit https://review.coreboot.org/20105 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Gerrit-Change-Number: 20105 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 08:42:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: riscv: Bug in fetch instruction
by Anonymous Coward (Code Review) 08 Jun '17

08 Jun '17

Anonymous Coward #1001664 has uploaded a new patch set (#2). ( https://review.coreboot.org/20105 ) Change subject: riscv: Bug in fetch instruction ...................................................................... riscv: Bug in fetch instruction I encountered a problem when i debug the code. The bug is continuously trap in misaligned load.This is caused by the fetch in the exception handling. Direct read 32bit value not care address alignment. But riscv have 16bit instruction. Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Signed-off-by: wxjstz <wxjstz(a)126.com> --- M src/arch/riscv/trap_handler.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20105/2 -- To view, visit https://review.coreboot.org/20105 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Gerrit-Change-Number: 20105 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001664

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Change in coreboot[master]: riscv: bug in fetch instruction
by Anonymous Coward (Code Review) 08 Jun '17

08 Jun '17

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20105 Change subject: riscv: bug in fetch instruction ...................................................................... riscv: bug in fetch instruction I encountered a problem when i debug the code. The bug is continuously trap in misaligned load.This is caused by the fetch in the exception handling. Direct read 32bit value not care address alignment. But riscv have 16bit instruction. Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Signed-off-by: wxjstz <wxjstz(a)126.com> --- M src/arch/riscv/trap_handler.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20105/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 4dd3d5b..d64a04b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -233,7 +233,12 @@ static uint32_t fetch_instruction(uintptr_t vaddr) { printk(BIOS_SPEW, "fetching instruction at 0x%016zx\n", (size_t)vaddr); - return mprv_read_u32((uint32_t *) vaddr); + uint32_t value = 0; + for(int i=0;i<2;i++){ + value <<= 16; + value += mprv_read_u16((uint16_t *)vaddr + i); + } + return value; } void handle_misaligned_load(trapframe *tf) { -- To view, visit https://review.coreboot.org/20105 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9 Gerrit-Change-Number: 20105 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Initial set of board files
by Lijian Zhao (Code Review) 08 Jun '17

08 Jun '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/20075 ) Change subject: mainboard/intel/cannonlake_rvp: Initial set of board files ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/20075/1/src/mainboard/intel/cannonlake_rvp/… File src/mainboard/intel/cannonlake_rvp/Kconfig: https://review.coreboot.org/#/c/20075/1/src/mainboard/intel/cannonlake_rvp/… PS1, Line 28: bs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.bin" Do we need to add the EC_BIN here? -- To view, visit https://review.coreboot.org/20075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Gerrit-Change-Number: 20075 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 07:48:57 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: crossgcc: Resolve pointer and integer comparison in GCC
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20103 ) Change subject: crossgcc: Resolve pointer and integer comparison in GCC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-toolchain/291/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10833/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55156/ : SUCCESS -- To view, visit https://review.coreboot.org/20103 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8b1e806c10604c0df080ac5edc667bf1141e2c17 Gerrit-Change-Number: 20103 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 07:03:13 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017