coreboot-gerrit May 2017

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Change in coreboot[master]: purism/librem13v1: Set FADT revision to ACPI 3.0
by Youness Alaoui (Code Review) 01 Jun '17

01 Jun '17

Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19985 to look at the new patch set (#3). Change subject: purism/librem13v1: Set FADT revision to ACPI 3.0 ...................................................................... purism/librem13v1: Set FADT revision to ACPI 3.0 The FADT revision was set to 5, but we do not implement the ACPI v5.0 specification, which prevents Windows from booting. Setting it to v3 (matching most other boards) fixes the issue and Windows now boots normally. Bug found by Matt DeVillier, fix tested by Youness Alaoui on Librem 13 v1 hardware. Please also see commits 00d250e2289de (intel/skylake: Switch FADT to ACPI version 3.0) [1] and 27e6042bb7d0b1 (intel/apollolake: Switch FADT to ACPI version 3.0) [2]. [1] https://review.coreboot.org/19453 [2] https://review.coreboot.org/19146 Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v1/fadt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/19985/3 -- To view, visit https://review.coreboot.org/19985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/d410pt: Add mainboard
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20000 ) Change subject: mb/intel/d410pt: Add mainboard ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/20000/1/src/mainboard/intel/d510mo/Kconfig.… File src/mainboard/intel/d510mo/Kconfig.name: PS1, Line 2: "D510MO I suppose just changing this into D510MO / D410PT would also work. Do we want a new option for exactly same code or not? -- To view, visit https://review.coreboot.org/20000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/intel/d410pt: Add mainboard
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20000 ) Change subject: mb/intel/d410pt: Add mainboard ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54669/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10377/ : SUCCESS -- To view, visit https://review.coreboot.org/20000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: purism/librem13: Disable L1 sub states support
by Youness Alaoui (Code Review) 01 Jun '17

01 Jun '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19900 ) Change subject: purism/librem13: Disable L1 sub states support ...................................................................... Patch Set 3: > Please make this run-time configurable for people not having such a > problematic device. What do you mean exactly? I only disable it for librem13 v1 boards which has the issue. A user can still enable it manually if they wish it, but by default it's disabled. Every other broadwell board will have it enabled by default. -- To view, visit https://review.coreboot.org/19900 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/d410pt: Add mainboard
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/20000 ) Change subject: mb/intel/d410pt: Add mainboard ...................................................................... mb/intel/d410pt: Add mainboard This board is almost identical to D510MO, the only differences are some differences in populated connections, CPU with less L2 cache and a 10/100 Realtek NIC. The vendor uses the very same binary for both D510M0 and D410PT. Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/d510mo/Kconfig M src/mainboard/intel/d510mo/Kconfig.name 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/20000/1 diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 0f747cc..915fe37 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -if BOARD_INTEL_D510MO +if BOARD_INTEL_D510MO || BOARD_INTEL_D410PT config BOARD_SPECIFIC_OPTIONS def_bool y @@ -43,6 +43,7 @@ config MAINBOARD_PART_NUMBER string - default "D510MO" + default "D510MO" if BOARD_INTEL_D510MO + default "D410PT" if BOARD_INTEL_D410PT endif # BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name index 2df0dca..979c101 100644 --- a/src/mainboard/intel/d510mo/Kconfig.name +++ b/src/mainboard/intel/d510mo/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_INTEL_D510MO bool "D510MO" + +config BOARD_INTEL_D410PT + bool "D410PT" -- To view, visit https://review.coreboot.org/20000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/apollolake: [WIP] Enable common SMI code for APL
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19393 ) Change subject: soc/intel/apollolake: [WIP] Enable common SMI code for APL ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54668/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10376/ : SUCCESS -- To view, visit https://review.coreboot.org/19393 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97a5bce74c6f47fee9966e0442be533291199042 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: [WIP]Add SMI common code for Intel Platforms
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19392 ) Change subject: soc/intel/common: [WIP]Add SMI common code for Intel Platforms ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54667/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10375/ : SUCCESS -- To view, visit https://review.coreboot.org/19392 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: [WIP] Enable common SMI code for APL
by Brandon Breitenstein (Code Review) 31 May '17

31 May '17

Brandon Breitenstein has uploaded a new change for review. ( https://review.coreboot.org/19393 ) Change subject: soc/intel/apollolake: [WIP] Enable common SMI code for APL ...................................................................... soc/intel/apollolake: [WIP] Enable common SMI code for APL This update changes Apollolake to use the new common SMI code. This will help to reduce code duplication and streamline code bring up. This patch depends on the PMC implementation for common code. Change-Id: I97a5bce74c6f47fee9966e0442be533291199042 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/include/soc/smm.h M src/soc/intel/apollolake/memmap.c D src/soc/intel/apollolake/smi.c M src/soc/intel/apollolake/smihandler.c 8 files changed, 25 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19393/6 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 892412d..f2c72cb 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -62,9 +62,9 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMI select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_LPSS_I2C - select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 36455f3..dfb6e79 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -68,7 +68,6 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c -ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xdci.c diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index ff300bc..8ea6519 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,12 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <fsp/memmap.h> +#include <intelblocks/smi.h> #include <reg_script.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> -#include <soc/smm.h> #include <cpu/intel/turbo.h> static const struct reg_script core_msr_script[] = { @@ -193,9 +194,9 @@ .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southbridge_smm_clear_state, + .pre_mp_smm_init = smi_southbridge_clear_state, .relocation_handler = relocation_handler, - .post_mp_init = southbridge_smm_enable_smi, + .post_mp_init = smi_southbridge_enable, }; void apollolake_init_cpus(device_t dev) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 7bad122..3728fff 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -82,6 +82,8 @@ #define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */ #define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */ #define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ +/* Save SMI Params for this platform to pass to enable_smi */ +#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) #define SMI_STS 0x44 /* Bits for SMI status */ diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 740d02b..68e8b77 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -24,6 +24,7 @@ /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); +void southbridge_trigger_smi(void); /* * The initialization of the southbridge is split into 2 compoments. One is diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 0f85b10..c40f81c 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -27,9 +27,10 @@ #include <assert.h> #include <cbmem.h> #include <device/pci.h> +#include <fsp/memmap.h> +#include <intelblocks/smi.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> -#include <soc/smm.h> static uintptr_t smm_region_start(void) { diff --git a/src/soc/intel/apollolake/smi.c b/src/soc/intel/apollolake/smi.c deleted file mode 100644 index 227f2f0..0000000 --- a/src/soc/intel/apollolake/smi.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <string.h> -#include <soc/pm.h> -#include <soc/smm.h> - -void southbridge_smm_clear_state(void) -{ - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - - if (pmc_get_smi_en() & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "Done\n"); - - /* Dump and clear status registers */ - pmc_clear_smi_status(); - pmc_clear_pm1_status(); - pmc_clear_tco_status(); - pmc_clear_gpe_status(); -} - -void southbridge_smm_enable_smi(void) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - pmc_enable_pm1(PWRBTN_EN | GBL_EN); - pmc_disable_gpe(PME_B0_EN); - - /* Enable SMI generation */ - pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - pmc_clear_smi_status(); - - /* Clear PM1 status */ - pmc_clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - pmc_enable_smi(EOS); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 0272a5c..91f100d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -21,22 +21,27 @@ #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/smi.h> +#include <intelblocks/smihandler.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/intel/common/smi.h> #include <spi-generic.h> #include <stdint.h> #include <stdlib.h> -#include <soc/smm.h> -int smm_disable_busmaster(device_t dev) +int smihandler_disable_busmaster(device_t dev) { if (dev == PCH_DEV_PMC) return 0; return 1; +} + +uint16_t smihandler_get_acpi_base(void) +{ + return ACPI_PMIO_BASE; } const struct smm_save_state_ops *get_smm_save_state_ops(void) @@ -45,24 +50,24 @@ } void __attribute__((weak)) -mainboard_smi_gpi_handler(const struct gpi_status *sts) { } +smi_mainboard_gpi_handler(const struct gpi_status *sts) { } static void southbridge_smi_gpi(const struct smm_save_state_ops *save_state_ops) { struct gpi_status smi_sts; gpi_clear_get_smi_status(&smi_sts); - mainboard_smi_gpi_handler(&smi_sts); + smi_mainboard_gpi_handler(&smi_sts); /* Clear again after mainboard handler */ gpi_clear_get_smi_status(&smi_sts); } const smi_handler_t southbridge_smi[32] = { - [SLP_SMI_STS] = southbridge_smi_sleep, - [APM_SMI_STS] = southbridge_smi_apmc, - [FAKE_PM1_SMI_STS] = southbridge_smi_pm1, + [SLP_SMI_STS] = smihandler_southbridge_sleep, + [APM_SMI_STS] = smihandler_southbridge_apmc, + [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, [GPIO_SMI_STS] = southbridge_smi_gpi, - [TCO_SMI_STS] = southbridge_smi_tco, - [PERIODIC_SMI_STS] = southbridge_smi_periodic, + [TCO_SMI_STS] = smihandler_southbridge_tco, + [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, }; -- To view, visit https://review.coreboot.org/19393 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I97a5bce74c6f47fee9966e0442be533291199042 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: [WIP]Add SMI common code for Intel Platforms
by Brandon Breitenstein (Code Review) 31 May '17

31 May '17

Brandon Breitenstein has uploaded a new change for review. ( https://review.coreboot.org/19392 ) Change subject: soc/intel/common: [WIP]Add SMI common code for Intel Platforms ...................................................................... soc/intel/common: [WIP]Add SMI common code for Intel Platforms SMI code is very similar across Intel platforms. Move this code to common/block/smi to allow it to be shared between platforms instead of duplicating the code for each platform. This patch relies on the PMC implemenation for common code. Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/common/Makefile.inc A src/soc/intel/common/block/include/intelblocks/smi.h R src/soc/intel/common/block/include/intelblocks/smihandler.h A src/soc/intel/common/block/smi/Kconfig A src/soc/intel/common/block/smi/Makefile.inc A src/soc/intel/common/block/smi/smi.c R src/soc/intel/common/block/smi/smihandler.c 7 files changed, 165 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19392/6 diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index b01fc8a..1a1cef1 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -35,8 +35,6 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c -smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c - bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/block/include/intelblocks/smi.h b/src/soc/intel/common/block/include/intelblocks/smi.h new file mode 100644 index 0000000..75a6e49 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/smi.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 201 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SMI_H +#define SOC_INTEL_COMMON_BLOCK_SMI_H + +#include <soc/gpio.h> + +/* + * The initialization of the southbridge is split into 2 compoments. One is + * for clearing the state in the SMM registers. The other is for enabling + * SMIs. + */ +void smi_southbridge_clear_state(void); +void smi_southbridge_enable(void); + +/* Mainboard handler for GPI SMIs*/ +void smi_mainboard_gpi_handler(const struct gpi_status *sts); + +#endif diff --git a/src/soc/intel/common/smi.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h similarity index 76% rename from src/soc/intel/common/smi.h rename to src/soc/intel/common/block/include/intelblocks/smihandler.h index 22c5104..a119e18 100644 --- a/src/soc/intel/common/smi.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _INTEL_COMMON_SMI_H_ -#define _INTEL_COMMON_SMI_H_ +#ifndef SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H +#define SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H /* * The register value is used with get_reg and set_reg @@ -59,48 +59,55 @@ * the SMI event on SLP_EN. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_sleep(const struct smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_APM event. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_apmc(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_apmc(const struct smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_PM1 event. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_pm1(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_pm1(const struct smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_GPE0 event. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_gpe0(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpe0(const struct smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_tco(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_tco(const struct smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI PERIODIC_STS event. The default functionality is provided in * soc/intel/common/smihandler.c */ -void southbridge_smi_periodic(const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_periodic(const struct smm_save_state_ops *save_state_ops); /* * This function returns a 1 or 0 depending on whether disable_busmaster * needs to be done for the specified device on S5 entry */ -int smm_disable_busmaster(device_t dev); +int smihandler_disable_busmaster(device_t dev); + +/* + * This function returns the ACPI base address for the platform. This is + * dependent on the specific platform defining this value. 0 is returned + * if the value is not defined by the platform. + */ +uint16_t smihandler_get_acpi_base(void); /* * Returns gnvs pointer within SMM context diff --git a/src/soc/intel/common/block/smi/Kconfig b/src/soc/intel/common/block/smi/Kconfig new file mode 100644 index 0000000..485986e --- /dev/null +++ b/src/soc/intel/common/block/smi/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_SMI + bool + default n + help + Intel Processor common SMI support diff --git a/src/soc/intel/common/block/smi/Makefile.inc b/src/soc/intel/common/block/smi/Makefile.inc new file mode 100644 index 0000000..1737df8 --- /dev/null +++ b/src/soc/intel/common/block/smi/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMI) += smi.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMI) += smihandler.c diff --git a/src/soc/intel/common/block/smi/smi.c b/src/soc/intel/common/block/smi/smi.c new file mode 100644 index 0000000..8cf083a --- /dev/null +++ b/src/soc/intel/common/block/smi/smi.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <intelblocks/smi.h> +#include <soc/pm.h> + +void smi_southbridge_clear_state(void) +{ + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + + if (pmc_get_smi_en() & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + printk(BIOS_DEBUG, "Done\n"); + + /* Dump and clear status registers */ + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_gpe_status(); +} + +void smi_southbridge_enable(void) +{ + printk(BIOS_DEBUG, "Enabling SMIs.\n"); + /* Configure events */ + pmc_enable_pm1(PWRBTN_EN | GBL_EN); + pmc_disable_gpe(PME_B0_EN); + + /* Enable SMI generation: */ + pmc_enable_smi(ENABLE_SMI_PARAMS); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* + * Issue SMI to set the gnvs pointer in SMM. + * tcg and smi1 are unused. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" ((u32)gnvs), + "d" (APM_CNT) + ); +} diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/block/smi/smihandler.c similarity index 87% rename from src/soc/intel/common/smihandler.c rename to src/soc/intel/common/block/smi/smihandler.c index 549a914..d7f0cb0 100644 --- a/src/soc/intel/common/smihandler.c +++ b/src/soc/intel/common/block/smi/smihandler.c @@ -21,6 +21,7 @@ #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/smihandler.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -28,14 +29,18 @@ #include <spi-generic.h> #include <stdint.h> #include <stdlib.h> -#include "smi.h" /* GNVS needs to be set by coreboot initiating a software SMI. */ static struct global_nvs_t *gnvs; -__attribute__((weak)) int smm_disable_busmaster(device_t dev) +__attribute__((weak)) int smihandler_disable_busmaster(device_t dev) { return 1; +} + +__attribute__((weak)) uint16_t smihandler_get_acpi_base(void) +{ + return 0; } static void *find_save_state(const struct smm_save_state_ops *save_state_ops, @@ -70,9 +75,10 @@ return state; } +/* Inherited from cpu/x86/smm.h resulting in a different signature */ void southbridge_smi_set_eos(void) { - enable_smi(EOS); + pmc_enable_smi(EOS); } struct global_nvs_t *smm_get_gnvs(void) @@ -91,7 +97,7 @@ u32 reg32; device_t dev = PCI_DEV(bus, slot, func); - if (!smm_disable_busmaster(dev)) + if (!smihandler_disable_busmaster(dev)) continue; val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -127,15 +133,16 @@ } -void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_sleep(const struct + smm_save_state_ops * save_state_ops) { uint32_t reg32; uint8_t slp_typ; /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + reg32 = inl(smihandler_get_acpi_base() + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -147,7 +154,7 @@ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ - clear_gpe_status(); + pmc_clear_gpe_status(); /* Next, do the deed. */ @@ -168,7 +175,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; @@ -178,7 +185,7 @@ } /* Clear the gpio gpe0 status bits in ACPI registers */ - clear_gpi_gpe_sts(); + pmc_clear_gpi_gpe_sts(); /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ @@ -187,7 +194,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ >= ACPI_S3) @@ -198,15 +205,15 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + reg32 = inl(smihandler_get_acpi_base() + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } } static void southbridge_smi_gsmi(const struct - smm_save_state_ops *save_state_ops) + smm_save_state_ops * save_state_ops) { u8 sub_command, ret; void *io_smi = NULL; @@ -239,7 +246,8 @@ } -void southbridge_smi_apmc(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_apmc(const struct + smm_save_state_ops * save_state_ops) { uint8_t reg8; void *state = NULL; @@ -266,11 +274,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: @@ -300,9 +308,10 @@ mainboard_smi_apmc(reg8); } -void southbridge_smi_pm1(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_pm1(const struct + smm_save_state_ops * save_state_ops) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status(); /* * While OSPM is not active, poweroff immediately @@ -312,19 +321,21 @@ /* power button pressed */ if (IS_ENABLED(CONFIG_ELOG_GSMI)) elog_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -void southbridge_smi_gpe0(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpe0(const struct + smm_save_state_ops * save_state_ops) { - clear_gpe_status(); + pmc_clear_gpe_status(); } -void southbridge_smi_tco(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_tco(const struct + smm_save_state_ops * save_state_ops) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -336,11 +347,12 @@ } } -void southbridge_smi_periodic(const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_periodic(const struct + smm_save_state_ops * save_state_ops) { uint32_t reg32; - reg32 = get_smi_en(); + reg32 = pmc_get_smi_en(); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -358,7 +370,7 @@ * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status(); save_state_ops = get_smm_save_state_ops(); -- To view, visit https://review.coreboot.org/19392 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support in APL for PMC common...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19375 ) Change subject: [WIP]soc/intel/apollolake: Add support in APL for PMC common code ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54666/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10374/ : SUCCESS -- To view, visit https://review.coreboot.org/19375 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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