Hello build bot (Jenkins),
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Change subject: nb/intel/sandybridge/raminit: Fix odt stretch
......................................................................
nb/intel/sandybridge/raminit: Fix odt stretch
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 35 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/17616/3
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
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Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17611
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge/raminit: Reduce log level
......................................................................
nb/intel/sandybridge/raminit: Reduce log level
Silency noisy raminit logging by:
* Removing verbose logging from loops.
* Printing detailed summary at end of loop instead.
* Using the same scheme already present in some functions.
Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 8 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/17611/4
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Gerrit-Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Gerrit-PatchSet: 4
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17609
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge/raminit: Add default values
......................................................................
nb/intel/sandybridge/raminit: Add default values
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_ivy.c
1 file changed, 48 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/17609/4
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Gerrit-Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17615
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge/raminit: Always run quick_ram_check
......................................................................
nb/intel/sandybridge/raminit: Always run quick_ram_check
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/17615/3
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Gerrit-Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17610
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge/raminit: Fix normalize_training
......................................................................
nb/intel/sandybridge/raminit: Fix normalize_training
Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/17610/4
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Gerrit-Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17607
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge/raminit: Add 100Mhz refclock support
......................................................................
nb/intel/sandybridge/raminit: Add 100Mhz refclock support
Add support for 100Mhz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_ivy.c
1 file changed, 40 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/17607/4
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Gerrit-Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
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Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/17606
to look at the new patch set (#5).
Change subject: nb/intel/sandybridge/raminit: Use Ivybridge specific values
......................................................................
nb/intel/sandybridge/raminit: Use Ivybridge specific values
Use Ivybridge specific values on Ivybridge instead of Sandybridge values.
The values are extracted from MRC.bin.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_ivy.c
M src/northbridge/intel/sandybridge/raminit_sandy.c
3 files changed, 255 insertions(+), 95 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/17606/5
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/17616 )
Change subject: [WIP]nb/intel/sandybridge/raminit: Fix odt stretch
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/17616/2/src/northbridge/intel/sandybridge/r…
File src/northbridge/intel/sandybridge/raminit_common.c:
PS2, Line 202: stretch = ctrl->ref_card_offset[channel];
could this be moved outside of conditional?
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Gerrit-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
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