Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16595
-gerrit
commit ab16aa0a4c82f8884c1b3e30d7d45fc8ae9c542c
Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Date: Tue Aug 23 11:20:20 2016 +0530
soc/intel/apollolake: Update PL1 value in RAPL MMIO register
Due to an incorrect value set for the power limit PL1, the
system is not able to leverage full TDP capacity. FSP code
sets the PL1 value as 6W in RAPL MMIO register based on
fused soc tdp value. This RAPL MMIO register is a physically
separate instance from RAPL MSR register. This patch sets
PL1 value to 15W in RAPL MMIO register.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package power
with heavy workload.
Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
src/soc/intel/apollolake/chip.c | 22 ++++++++++++++++++++++
src/soc/intel/apollolake/include/soc/cpu.h | 1 +
src/soc/intel/apollolake/include/soc/northbridge.h | 2 ++
3 files changed, 25 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 78c669d..69ee122 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -34,6 +34,7 @@
#include <spi-generic.h>
#include <soc/pm.h>
#include <soc/p2sb.h>
+#include <soc/northbridge.h>
#include "chip.h"
@@ -189,6 +190,24 @@ static void pcie_override_devicetree_after_silicon_init(void)
pcie_update_device_tree(PCIEB0_DEVFN, 2);
}
+static void rapl_update(void)
+{
+ uint32_t *rapl_reg;
+ uint32_t val;
+ const uint32_t power_mw = 15000;
+
+ rapl_reg = (void*)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL);
+
+ /* Due to an incorrect value set for the power limit PL1 as 6W in RAPL
+ * MMIO register from FSP code, the system is not able to leverage full
+ * TDP capacity. This RAPL MMIO register is a physically separate
+ * instance from RAPL MSR register. Punit algorithm controls to the
+ * minimum power limit PL1 mentioned in the RAPL MMIO and MSR registers.
+ * Here, setting RAPL PL1 in Bits[14:0] to 15W in RAPL MMIO register. */
+ val = (power_mw << (rdmsr(MSR_PKG_POWER_SKU_UNIT).lo & 0xf)) / 1000;
+ write32(rapl_reg, (read32(rapl_reg) & ~0x7fff) | val);
+}
+
static void soc_init(void *data)
{
struct global_nvs_t *gnvs;
@@ -218,6 +237,9 @@ static void soc_init(void *data)
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+
+ /* Update RAPL package power limit */
+ rapl_update();
}
static void soc_final(void *data)
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 8887c17..22412af 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -38,6 +38,7 @@ void apollolake_init_cpus(struct device *dev);
#define PREFETCH_L1_DISABLE (1 << 0)
#define PREFETCH_L2_DISABLE (1 << 2)
+#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
#define MSR_IA32_PQR_ASSOC 0xc8f
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
index 0f61674..04e369e 100644
--- a/src/soc/intel/apollolake/include/soc/northbridge.h
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -34,5 +34,7 @@
#define MCH_IMR_PITCH 0x20
#define MCH_NUM_IMRS 20
+/* RAPL Package Power Limit register under MCHBAR. */
+#define MCHBAR_RAPL_PPL 0x70A8
#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16597
-gerrit
commit 5d81da7fb1c3a8bcc79ac8d9d0b8494e7e71d030
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Sep 13 12:31:57 2016 -0500
soc/intel/apollolake: initialize GNVS structure to 0
The code was not previously initializing the GNVS structure
to all 0's in the ACPI write tables path. Fix this and also
rearrange the ordering of updating the fields to only handle
the chip_info specific bits till last such that most of the
structure is filled in prior to bailing out in the case of a
bad devicetree.
Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/apollolake/acpi.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4f4276a..1ca04fd 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -28,6 +28,7 @@
#include <soc/pm.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
+#include <string.h>
#include "chip.h"
#define CSTATE_RES(address_space, width, offset, address) \
@@ -151,11 +152,8 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
struct soc_intel_apollolake_config *cfg;
struct device *dev = NB_DEV_ROOT;
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
- return;
- }
- cfg = dev->chip_info;
+ /* Clear out GNVS. */
+ memset(gnvs, 0, sizeof(*gnvs));
if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
@@ -166,11 +164,17 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
- /* Enable DPTF based on mainboard configuration */
- gnvs->dpte = cfg->dptf_enable;
-
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+ cfg = dev->chip_info;
+
+ /* Enable DPTF based on mainboard configuration */
+ gnvs->dpte = cfg->dptf_enable;
}
/* Save wake source information for calculating ACPI _SWS values */
the following patch was just integrated into master:
commit 6d8e39127ba6fe4c24813f876cea7f8aef63dfee
Author: Gwendal Grignou <gwendal(a)chromium.org>
Date: Mon Sep 12 20:51:58 2016 -0700
mainboard/google/reef: add MKBP EC event as SCI event.
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.
BUG=b:27849483
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.
Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16594 for details.
-gerrit
the following patch was just integrated into master:
commit a1e1e5c7e3d85643228aeee24dda8e3e2eb325bd
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sun Aug 21 10:51:53 2016 +0200
i945.h: fix #include path
Fix the #include path.
Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16294
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16294 for details.
-gerrit
the following patch was just integrated into master:
commit a422ffc53490b232a4c72cd499d9f9e58d8521cf
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:43:20 2016 +0200
cpu/amd/family_10h-family_15h: transition away from device_t
Replace the use of the old device_t definition inside
cpu/amd/family_10h-family_15h.
Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16436
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16436 for details.
-gerrit
the following patch was just integrated into master:
commit ec4555b96d9c4ec57b03e21c6d9af3626c24b933
Author: Antonello Dettori <dev(a)dettori.io>
Date: Fri Sep 2 09:12:20 2016 +0200
lenovo/t60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/t60.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16405
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16405 for details.
-gerrit
the following patch was just integrated into master:
commit 8d7181ddd16c06e484c74b0df4431e5557631b07
Author: Antonello Dettori <dev(a)dettori.io>
Date: Thu Sep 1 16:50:42 2016 +0200
southbridge/amd/agesa/hudson: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/agesa/hudson.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16401
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16401 for details.
-gerrit
the following patch was just integrated into master:
commit 5ea2cadfff2055932a16339521be098dae510261
Author: Antonello Dettori <dev(a)dettori.io>
Date: Fri Sep 2 09:13:10 2016 +0200
northbridge/intel/nehalem: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/nehalem.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16406
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16406 for details.
-gerrit
the following patch was just integrated into master:
commit 040117af5296080dcaf5dcaf687fb6bbf80e83a5
Author: Antonello Dettori <dev(a)dettori.io>
Date: Fri Sep 2 09:15:33 2016 +0200
southbridge/intel/ibexpeak: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/ibexpeak.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Ic569aada9301b37e73196872584e191d553acd86
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16408
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16408 for details.
-gerrit
the following patch was just integrated into master:
commit 061d781e993b1fffd559a0af08cbb41a4a0675c7
Author: Antonello Dettori <dev(a)dettori.io>
Date: Tue Aug 30 22:05:32 2016 +0200
southbridge/intel/i82801gx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801gx.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16370 for details.
-gerrit