coreboot-gerrit July 2016

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New patch to review for coreboot: intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI
by Werner Zeh 06 Jul '16

06 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15548 -gerrit commit 16efb9d129ad2d025f0cdc1326a34422ec584c94 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 12:58:57 2016 +0200 intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/acpi.c | 30 +++++++++++++++++++++++- src/soc/intel/fsp_broadwell_de/include/soc/irq.h | 10 ++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index afa4048..1e08868 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -78,7 +78,35 @@ static acpi_cstate_t cstate_map[] = { static int acpi_sci_irq(void) { - return 9; + uint8_t actl = 0; + static uint8_t sci_irq = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* If this function was already called, just return the stored value. */ + if (sci_irq) + return sci_irq; + /* Get contents of ACPI control register. */ + actl = pci_read_config8(dev, ACPI_CNTL_OFFSET) & SCIS_MASK; + /* Determine how SCI is routed. */ + switch (actl) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = actl + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = actl - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; } void acpi_create_intel_hpet(acpi_hpet_t *hpet) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h index ea04326..1344f3b 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h @@ -51,6 +51,16 @@ #define PIRQG 6 #define PIRQH 7 +#define ACPI_CNTL_OFFSET 0x44 +#define SCIS_MASK 0x07 +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + /* In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */

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New patch to review for coreboot: siemens/mc_bdx1: Set up opcode menu for SPI controller
by Werner Zeh 06 Jul '16

06 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15547 -gerrit commit 9a586e7817424fbe65bc8a27b29ff7d380afb642 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 11:59:10 2016 +0200 siemens/mc_bdx1: Set up opcode menu for SPI controller Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/mainboard.c | 68 +++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index af886a9..bad072b 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -31,9 +31,57 @@ #include <boot/coreboot_tables.h> #include <hwilib.h> #include <i210.h> +#include <soc/pci_devs.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 + +/* + * SPI Opcode Menu setup for SPIBAR lock down + * should support most common flash chips. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + +#define SPIBAR_OFFSET 0x3800 +#define SPI_REG_PREOP 0x94 +#define SPI_REG_OPTYPE 0x96 +#define SPI_REG_OPMENU_L 0x98 +#define SPI_REG_OPMENU_H 0x9c + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. @@ -42,6 +90,25 @@ static void mainboard_enable(device_t dev) { } + +static void mainboard_final(void *chip_info) +{ + void *spi_base = NULL; + uint32_t rcba = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* Get address of SPI controller. */ + rcba = (pci_read_config32(dev, 0xf0) & 0xffffc000); + if (!rcba) + return; + spi_base = (void *)(rcba + SPIBAR_OFFSET); + /* Setup OPCODE menu */ + write16((spi_base + SPI_REG_PREOP), SPI_OPPREFIX); + write16((spi_base + SPI_REG_OPTYPE), SPI_OPTYPE); + write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); + write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); +} + /** \brief This function can decide if a given MAC address is valid or not. * Currently, addresses filled with 0xff or 0x00 are not valid. * @param mac Buffer to the MAC address to check @@ -116,4 +183,5 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .final = mainboard_final };

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New patch to review for coreboot: PCI: Use PCI_DEVFN macro instead of DEV_FUNC
by Werner Zeh 06 Jul '16

06 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15546 -gerrit commit 0a4c63610d9c1a0aa6d0a1f67f2a084f9995d21b Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 08:47:56 2016 +0200 PCI: Use PCI_DEVFN macro instead of DEV_FUNC There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/include/soc/pci_devs.h | 72 +++++++++++----------- .../intel/fsp_broadwell_de/include/soc/pci_devs.h | 38 ++++++------ src/soc/intel/quark/include/soc/pci_devs.h | 5 +- src/southbridge/intel/fsp_rangeley/pci_devs.h | 39 ++++++------ 4 files changed, 79 insertions(+), 75 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 2d0dac1..f9c978d 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -17,49 +17,49 @@ #ifndef _BAYTRAIL_PCI_DEVS_H_ #define _BAYTRAIL_PCI_DEVS_H_ +#include <device/pci_def.h> + #define BUS0 0 /* All these devices live on bus 0 with the associated device and function */ -#define DEV_FUNC(x,y) ((x<<3) | y) - /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x0f00 -# define SOC_DEV_FUNC DEV_FUNC(SOC_DEV,SOC_FUNC) +# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -# define GFX_DEV_FUNC DEV_FUNC(GFX_DEV,GFX_FUNC) +# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) /* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 # define MIPI_DEVID 0x0f38 -# define MIPI_DEV_FUNC DEV_FUNC(MIPI_DEV,MIPI_FUNC) +# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) /* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 # define EMMC_DEVID 0x0f14 -# define EMMC_DEV_FUNC DEV_FUNC(EMMC_DEV,EMMC_FUNC) +# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 # define SDIO_DEVID 0x0f15 -# define SDIO_DEV_FUNC DEV_FUNC(SDIO_DEV,SDIO_FUNC) +# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 # define SD_DEVID 0x0f16 -# define SD_DEV_FUNC DEV_FUNC(SD_DEV,SD_FUNC) +# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) /* SATA */ #define SATA_DEV 0x13 @@ -74,7 +74,7 @@ # define SATA_SP 0xD0 # define SATA_BIST1 0xE4 # define SATA_BIST2 0xE8 -# define SATA_DEV_FUNC DEV_FUNC(SATA_DEV,SATA_FUNC) +# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) #define SATA_MA_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_MA #define SATA_SP_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_SP @@ -88,25 +88,25 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC DEV_FUNC(XHCI_DEV,XHCI_FUNC) +# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 -# define LPE_DEV_FUNC DEV_FUNC(LPE_DEV,LPE_FUNC) +# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) /* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 # define OTG_DEVID 0x0f37 -# define OTG_DEV_FUNC DEV_FUNC(LPE_DEV,LPE_FUNC) +# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) /* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 # define MMC45_DEVID 0x0f50 -# define MMC45_DEV_FUNC DEV_FUNC(MMC45_DEV,MMC45_FUNC) +# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) /* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -134,26 +134,26 @@ # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 # define I2C7_DEVID 0x0f47 -# define SIO_DMA1_DEV_FUNC DEV_FUNC(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC DEV_FUNC(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC DEV_FUNC(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC DEV_FUNC(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC DEV_FUNC(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC DEV_FUNC(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC DEV_FUNC(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC DEV_FUNC(I2C7_DEV,I2C7_FUNC) +# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 # define TXE_DEVID 0x0f18 -# define TXE_DEV_FUNC DEV_FUNC(TXE_DEV,TXE_FUNC) +# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEVID 0x0f04 -# define HDA_DEV_FUNC DEV_FUNC(HDA_DEV,HDA_FUNC) +# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) # define HDA_AZUBAR 0x14 # define HDA_MMLA 0x64 # define HDA_MMUA 0x68 @@ -175,16 +175,16 @@ # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e -# define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT4_FUNC) +# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 -# define EHCI_DEV_FUNC DEV_FUNC(EHCI_DEV,EHCI_FUNC) +# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) /* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -206,12 +206,12 @@ # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 # define SPI_DEVID 0xf0e -# define SIO_DMA2_DEV_FUNC DEV_FUNC(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC DEV_FUNC(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC DEV_FUNC(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC DEV_FUNC(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC DEV_FUNC(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC DEV_FUNC(SPI_DEV,SPI_FUNC) +# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) /* Platform Controller Unit */ @@ -222,9 +222,9 @@ # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -# define LPC_DEV_FUNC DEV_FUNC(LPC_DEV,LPC_FUNC) +# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC DEV_FUNC(SMBUS_DEV,SMBUS_FUNC) +# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) #define INITIAL_TIMESTAMP_LOCATION HDA_MMUA_BDFO #define BEFORE_CAR_TIMESTAMP_LOCATION SATA_BIST1_BDFO diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index 646ed3f..9923601 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -17,38 +17,40 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <device/pci_def.h> + #define BUS0 0 #define SOC_DEV 0 #define SOC_FUNC 0 #define SOC_DEVID 0x2F00 #define SOC_DEVID_ES2 0x6F00 -#define SOC_DEV_FUNC DEV_FUNC(SOC_DEV, SOC_FUNC) +#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) #define LPC_DEV 31 #define LPC_FUNC 0 #define LPC_DEVID 0x8C42 #define LPC_DEVID_ES2 0x8C54 -#define LPC_DEV_FUNC DEV_FUNC(LPC_DEV, LPC_FUNC) +#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define SATA_DEV 31 #define SATA_FUNC 2 #define AHCI_DEVID 0x8C02 -#define SATA_DEV_FUNC DEV_FUNC(SATA_DEV, SATA_FUNC) +#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SATA2_DEV 31 #define SATA2_FUNC 5 -#define SATA2_DEV_FUNC DEV_FUNC(SATA2_DEV, SATA2_FUNC) +#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) #define EHCI1_DEV 29 #define EHCI1_FUNC 0 #define EHCI1_DEVID 0x8C26 -#define EHCI1_DEV_FUNC DEV_FUNC(EHCI_DEV1, EHCI_FUNC1) +#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) #define EHCI2_DEV 26 #define EHCI2_FUNC 0 #define EHCI2_DEVID 0x8C2D -#define EHCI2_DEV_FUNC DEV_FUNC(EHCI_DEV2, EHCI_FUNC2) +#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) #define XHCI_DEV 20 #define XHCI_FUNC 0 @@ -56,22 +58,22 @@ #define XHCI_FUS_REG 0xE0 #define XHCI_FUNC_DISABLE (1 << 0) #define XHCI_USB2PR_REG 0xD0 -#define XHCI_DEV_FUNC DEV_FUNC(XHCI_DEV, XHCI_FUNC) +#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define GBE_DEV 25 #define GBE_FUNC 0 #define GBE_DEVID 0x8C33 -#define GBE_DEV_FUNC DEV_FUNC(GBE_DEV, GBE_FUNC) +#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) #define ME_DEV 22 #define ME_FUNC 0 #define ME_DEVID 0x8C3A -#define ME_DEV_FUNC DEV_FUNC(ME_DEV, ME_FUNC) +#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) #define HDA_DEV 27 #define HDA_FUNC 0 #define HDA_DEVID 0x8C20 -#define HDA_DEV_FUNC DEV_FUNC(HDA_DEV, HDA_FUNC) +#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) #define PCIE_DEV 28 #define PCIE_PORT1_DEV PCIE_DEV @@ -98,13 +100,13 @@ #define PCIE_PORT8_DEV PCIE_DEV #define PCIE_PORT8_FUNC 7 #define PCIE_PORT8_DEVID 0x8C1E -#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT1_FUNC) -#define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT2_FUNC) -#define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT3_FUNC) -#define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT4_FUNC) -#define PCIE_PORT5_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT5_FUNC) -#define PCIE_PORT6_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT6_FUNC) -#define PCIE_PORT7_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT7_FUNC) -#define PCIE_PORT8_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT8_FUNC) +#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) +#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) +#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) +#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) +#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) +#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) +#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) +#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 0c99eb9..1aecf6f 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -19,6 +19,7 @@ #define _QUARK_PCI_DEVS_H_ #include <device/pci.h> +#include <device/pci_def.h> #include <soc/reg_access.h> /* DEVICE 0 (Memory Controller Hub) */ @@ -54,12 +55,12 @@ #define PCIE_DEV 0x17 #define PCIE_PORT0_DEV PCIE_DEV #define PCIE_PORT0_FUNC 0 -#define PCIE_PORT0_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT0_FUNC) +#define PCIE_PORT0_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT1_DEV PCIE_DEV #define PCIE_PORT1_FUNC 1 -#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) #define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) /* Platform Controller Unit */ diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 3eacf0d..29f9085 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -17,58 +17,59 @@ #ifndef _RANGELEY_PCI_DEVS_H_ #define _RANGELEY_PCI_DEVS_H_ +#include <device/pci_def.h> + #define BUS0 0 /* All these devices live on bus 0 with the associated device and function */ -#define DEV_FUNC(x,y) ((x<<3) | y) /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x1f08 -# define SOC_DEV_FUNC DEV_FUNC(SOC_DEV,SOC_FUNC) +# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x1f10 -# define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) +# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 # define PCIE_PORT2_DEVID 0x1f11 -# define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) +# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 # define PCIE_PORT3_DEVID 0x1f12 -# define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) +# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 # define PCIE_PORT4_DEVID 0x1f13 -# define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) +# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 # define HOST_BRIDGE_DEVID 0x1f14 -# define HOST_BRIDGE_DEV_FUNC DEV_FUNC(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) +# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 # define RCEC_DEVID 0x1f16 -# define RCEC_DEV_FUNC DEV_FUNC(RCEC_DEV,RCEC_FUNC) +# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 # define SMBUS1_DEVID 0x1f15 -# define SMBUS1_DEV_FUNC DEV_FUNC(SMBUS1_DEV,SMBUS1_FUNC) +# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 @@ -76,37 +77,37 @@ #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 # define GBE1_DEVID GBE_DEVID -# define GBE1_DEV_FUNC DEV_FUNC(GBE1_DEV,GBE1_FUNC) +# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 # define GBE2_DEVID GBE_DEVID -# define GBE2_DEV_FUNC DEV_FUNC(GBE2_DEV,GBE2_FUNC) +# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 # define GBE3_DEVID GBE_DEVID -# define GBE3_DEV_FUNC DEV_FUNC(GBE3_DEV,GBE3_FUNC) +# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 # define GBE4_DEVID GBE_DEVID -# define GBE4_DEV_FUNC DEV_FUNC(GBE4_DEV,GBE4_FUNC) +# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 # define USB2_DEVID 0x1f2c -# define USB2_DEV_FUNC DEV_FUNC(USB2_DEV,USB2_FUNC) +# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 # define SATA2_DEVID 0x1f22 -# define SATA2_DEV_FUNC DEV_FUNC(SATA2_DEV,SATA2_FUNC) +# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 # define SATA3_DEVID 0x1f32 -# define SATA3_DEV_FUNC DEV_FUNC(SATA3_DEV,SATA3_FUNC) +# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ #define PCU_DEV 0x1f @@ -115,19 +116,19 @@ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 # define LPC_DEVID 0x1f38 -# define LPC_DEV_FUNC DEV_FUNC(LPC_DEV,LPC_FUNC) +# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 # define SMBUS0_DEVID 0x1f3c -# define SMBUS0_DEV_FUNC DEV_FUNC(SMBUS0_DEV,SMBUS0_FUNC) +# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 # define IQAT_DEVID 0x1f18 -# define IQAT_DEV_FUNC DEV_FUNC(IQAT_DEV,IQAT_FUNC) +# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) #endif /* _RANGELEY_PCI_DEVS_H_ */

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New patch to review for coreboot: siemens/mc_bdx1: Add usage of Siemens NC FPGA driver
by Werner Zeh 06 Jul '16

06 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15545 -gerrit commit e803158932b7c17bfaf5db01020811f95de81c74 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jul 6 06:44:42 2016 +0200 siemens/mc_bdx1: Add usage of Siemens NC FPGA driver Enable NC FPGA driver for this mainboard. Change-Id: I87b6b10038f3d161a25b2008b7ea44b5627cca43 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index f947f3d..960fe00 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select CBFS_AUTOGEN_ATTRIBUTES select USE_SIEMENS_HWILIB select DRIVER_INTEL_I210 + select DRIVER_SIEMENS_NC_FPGA config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: siemens/nc_fpga: Add driver for Siemens NC FPGA
by Werner Zeh 06 Jul '16

06 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15543 -gerrit commit a98c98a14c798f4bf5e4b5e478704a396085ef8f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Jul 5 07:16:34 2016 +0200 siemens/nc_fpga: Add driver for Siemens NC FPGA Add driver code to initialize Siemens NC FPGA as PCI device. Beside some glue logic it contains a FAN controller and temperature monitor. Change-Id: I2cb722a60081028ee5a8251f51125f12ed38d824 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/siemens/nc_fpga/Kconfig | 3 + src/drivers/siemens/nc_fpga/Makefile.inc | 16 ++++ src/drivers/siemens/nc_fpga/nc_fpga.c | 139 +++++++++++++++++++++++++++++++ src/drivers/siemens/nc_fpga/nc_fpga.h | 64 ++++++++++++++ 4 files changed, 222 insertions(+) diff --git a/src/drivers/siemens/nc_fpga/Kconfig b/src/drivers/siemens/nc_fpga/Kconfig new file mode 100644 index 0000000..832446f --- /dev/null +++ b/src/drivers/siemens/nc_fpga/Kconfig @@ -0,0 +1,3 @@ +config DRIVER_SIEMENS_NC_FPGA + bool + default n diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc new file mode 100644 index 0000000..724ed6f --- /dev/null +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c new file mode 100644 index 0000000..def456b --- /dev/null +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <string.h> +#include <delay.h> +#include <hwilib.h> +#include "nc_fpga.h" + +#define FPGA_SET_PARAM(src, dst) \ +{ \ + typeof(dst) var; \ + size_t len = sizeof(var); \ + if (hwilib_get_field(src, (uint8_t *)&var, len) == len) \ + dst = (typeof(dst))(var); \ +} + +static void init_temp_mon (void *base_adr) +{ + uint32_t cc[5], i = 0; + uint8_t num = 0; + volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; + + /* Program sensor delay first. */ + FPGA_SET_PARAM(FANSensorDelay, ctrl->sensordelay); + /* Program correction curve for every used sensor. */ + if (hwilib_get_field(FANSensorNum, &num, sizeof(num) != sizeof(num)) || + (num == 0) || (num > MAX_NUM_SENSORS)) + return; + for (i = 0; i < num; i ++) { + if (hwilib_get_field(FANSensorCfg0 + i, (uint8_t *)&cc[0], + sizeof(cc)) == sizeof(cc)) { + ctrl->sensorcfg[cc[0]].rmin = cc[1] & 0xffff; + ctrl->sensorcfg[cc[0]].rmax = cc[2] & 0xffff; + ctrl->sensorcfg[cc[0]].nmin = cc[3] & 0xffff; + ctrl->sensorcfg[cc[0]].nmax = cc[4] & 0xffff; + } + } + ctrl->sensornum = num; +} + +static void init_fan_ctrl (void *base_adr) +{ + uint8_t mask = 0, freeze_mode = 0, fan_req = 0; + volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; + + /* Program all needed fields of FAN controller. */ + FPGA_SET_PARAM(FANSensorSelect, ctrl->sensorselect); + FPGA_SET_PARAM(T_Warn, ctrl->t_warn); + FPGA_SET_PARAM(T_Crit, ctrl->t_crit); + FPGA_SET_PARAM(FANSamplingTime, ctrl->samplingtime); + FPGA_SET_PARAM(FANSetPoint, ctrl->setpoint); + FPGA_SET_PARAM(FANHystCtrl, ctrl->hystctrl); + FPGA_SET_PARAM(FANHystVal, ctrl->hystval); + FPGA_SET_PARAM(FANHystThreshold, ctrl->hystthreshold); + FPGA_SET_PARAM(FANKp, ctrl->kp); + FPGA_SET_PARAM(FANKi, ctrl->ki); + FPGA_SET_PARAM(FANKd, ctrl->kd); + FPGA_SET_PARAM(FANMaxSpeed, ctrl->fanmax); + /* Set freeze and FAN configuration. */ + if ((hwilib_get_field(FF_FanReq, &fan_req, 1) == 1) && + (hwilib_get_field(FF_FreezeDis, &freeze_mode, 1) == 1)) { + if (!fan_req) + mask = 1; + else if (fan_req && freeze_mode) + mask = 2; + else + mask = 3; + ctrl->fanmon = mask << 10; + } +} + +/** \brief This function is the driver entry point for the init phase + * of the PCI bus allocator. It will initialize all the needed parts + * of NC_FPGA. + * @param *dev Pointer to the used PCI device + * @return void Nothing is given back + */ +static void nc_fpga_init(struct device *dev) +{ + void *bar0_ptr = NULL; + uint8_t cmd_reg; + uint32_t cap = 0; + + /* All we need is mapped to BAR 0, get the address. */ + bar0_ptr = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); + cmd_reg = pci_read_config8(dev, PCI_COMMAND); + /* Ensure BAR0 has a valid value. */ + if (!bar0_ptr || !(cmd_reg & PCI_COMMAND_MEMORY)) + return; + /* Ensure this is really a NC FPGA by checking magic register. */ + if (read32(bar0_ptr + NC_MAGIC_OFFSET) != NC_FPGA_MAGIC) + return; + /* Open hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + /* Set up FAN controller and temperature monitor according to */ + /* capability bits. */ + cap = read32(bar0_ptr + NC_CAP1_OFFSET); + if (cap & (NC_CAP1_TEMP_MON | NC_CAP1_FAN_CTRL)) + init_temp_mon(bar0_ptr + NC_FANMON_CTRL_OFFSET); + if (cap & NC_CAP1_FAN_CTRL) + init_fan_ctrl(bar0_ptr + NC_FANMON_CTRL_OFFSET); +} + +static struct device_operations nc_fpga_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nc_fpga_init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const unsigned short nc_fpga_device_ids[] = { 0x4091, 0 }; + +static const struct pci_driver nc_fpga_driver __pci_driver = { + .ops = &nc_fpga_ops, + .vendor = 0x110A, + .devices = nc_fpga_device_ids, +}; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h new file mode 100644 index 0000000..886f3dd --- /dev/null +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SIEMENS_NC_FPGA_H_ +#define _SIEMENS_NC_FPGA_H_ + +#define NC_MAGIC_OFFSET 0x020 +#define NC_FPGA_MAGIC 0x4E433746 +#define NC_CAP1_OFFSET 0x080 +#define NC_CAP1_FAN_CTRL 0x080 +#define NC_CAP1_TEMP_MON 0x100 +#define NC_FANMON_CTRL_OFFSET 0x400 + +#define MAX_NUM_SENSORS 4 + +typedef struct { + uint16_t rmin; + uint16_t rmax; + uint16_t nmin; + uint16_t nmax; +} temp_cc_t; + +typedef struct { + uint16_t res0; + uint8_t sensornum; + uint8_t res1; + uint32_t sensordelay; + uint32_t res2[4]; + temp_cc_t sensorcfg[8]; + uint32_t res3[4]; + uint8_t sensorselect; + uint8_t res4[3]; + uint16_t t_warn; + uint16_t t_crit; + uint16_t res5; + uint8_t res6[2]; + uint32_t samplingtime; + uint16_t setpoint; + uint8_t hystctrl; + uint8_t res7; + uint16_t kp; + uint16_t ki; + uint16_t kd; + uint16_t res8[2]; + uint16_t fanmax; + uint16_t hystval; + uint16_t hystthreshold; + uint16_t res9[4]; + uint32_t fanmon; +} __attribute__ ((packed)) fan_ctrl_t; + +#endif /* _SIEMENS_NC_FPGA_H_ */

1 0

Patch set updated for coreboot: Add stub implementation of MVMAP2315 SOC
by hakim giydan 05 Jul '16

05 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15506 -gerrit commit 2dabff4a322d1dbf91155b30e05ceb6314679cdd Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Tue Jul 5 14:51:07 2016 -0700 Add stub implementation of MVMAP2315 SOC Most things still need to be filled in, but this will allow us to build boards which use this SOC Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used as templates to create this directory Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Kconfig | 37 +++ src/soc/marvell/mvmap2315/Makefile.inc | 53 +++ src/soc/marvell/mvmap2315/assert.c | 42 +++ src/soc/marvell/mvmap2315/bootblock.stub | 20 ++ src/soc/marvell/mvmap2315/cbmem.c | 25 ++ src/soc/marvell/mvmap2315/clock.c | 50 +++ src/soc/marvell/mvmap2315/gic.c | 30 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 35 ++ src/soc/marvell/mvmap2315/include/soc/assert.h | 31 ++ src/soc/marvell/mvmap2315/include/soc/clock.h | 358 +++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/memlayout.ld | 66 ++++ .../marvell/mvmap2315/include/soc/mmu_operations.h | 27 ++ .../mvmap2315/include/soc/monotonic_timer.h | 50 +++ src/soc/marvell/mvmap2315/include/soc/power.h | 33 ++ src/soc/marvell/mvmap2315/include/soc/ramstage.h | 23 ++ src/soc/marvell/mvmap2315/media.c | 26 ++ src/soc/marvell/mvmap2315/mmu_operations.c | 46 +++ src/soc/marvell/mvmap2315/monotonic_timer.c | 63 ++++ src/soc/marvell/mvmap2315/power.c | 41 +++ src/soc/marvell/mvmap2315/ramstage.c | 34 ++ src/soc/marvell/mvmap2315/romstage.c | 78 +++++ src/soc/marvell/mvmap2315/romstage_asm.S | 66 ++++ src/soc/marvell/mvmap2315/soc.c | 46 +++ src/soc/marvell/mvmap2315/stage_entry.S | 26 ++ src/soc/marvell/mvmap2315/uart.c | 46 +++ 25 files changed, 1352 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Kconfig b/src/soc/marvell/mvmap2315/Kconfig new file mode 100644 index 0000000..cfa622e --- /dev/null +++ b/src/soc/marvell/mvmap2315/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_MARVELL_MVMAP2315 + bool + default n + select ARM_LPAE + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV7_R + select ARCH_VERSTAGE_ARMV7_R + select GENERIC_UDELAY + select GIC + select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select UNCOMPRESSED_RAMSTAGE + select VBOOT_DYNAMIC_WORK_BUFFER + +if SOC_MARVELL_MVMAP2315 + +config EMULATION + bool + default n +endif diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc new file mode 100644 index 0000000..d80453a --- /dev/null +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += assert.c +ramstage-y += cbmem.c +ramstage-y += clock.c +ramstage-y += gic.c +ramstage-y += media.c +ramstage-y += mmu_operations.c +ramstage-y += monotonic_timer.c +ramstage-y += ramstage.c +ramstage-y += soc.c +ramstage-y += stage_entry.S +ramstage-y += uart.c + +romstage-y += assert.c +romstage-y += cbmem.c +romstage-y += clock.c +romstage-y += media.c +romstage-y += monotonic_timer.c +romstage-y += power.c +romstage-y += romstage_asm.S +romstage-y += romstage.c +romstage-y += uart.c + +CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ + +all: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.bin + +## Replacing bootblock.bin with bootblock.stub since bootROM load and +## jump to romstage code directly. +## it is necessary to create a bootblock.stub file, or the final coreboot +## make stage will fail when it can't find bootblock.bin. + +$(objcbfs)/bootblock.bin: src/soc/marvell/mvmap2315/bootblock.stub + cat src/soc/marvell/mvmap2315/bootblock.stub > $(objcbfs)/bootblock.bin + +## generating romtage.bin since it is required to create the BDB + +$(objcbfs)/romstage.bin: $(objcbfs)/romstage.elf + $(OBJCOPY_romstage) -O binary $(objcbfs)/romstage.elf $(objcbfs)/romstage.bin diff --git a/src/soc/marvell/mvmap2315/assert.c b/src/soc/marvell/mvmap2315/assert.c new file mode 100644 index 0000000..f4c498c --- /dev/null +++ b/src/soc/marvell/mvmap2315/assert.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <console/console.h> +#include <soc/assert.h> +#include <stddef.h> + +/*Trivial __assert_func */ +static void __assert_func(const char *file, int line, + const char *func, + const char *failedexpr) +{ +#ifdef CONFIG_CONSOLE_SERIAL_UART + printk(BIOS_ERR, "\n\nASSERT!!\n\n"); + printk(BIOS_ERR, "%s:%d - %s - %s\n", file, line, func, failedexpr); +#endif + + /* Purposely empty */ + while (1) + ; +} + +/* Minimal __assert() */ +void __assert(const char *failedexpr, const char *file, int line) +{ + __assert_func(file, line, NULL, failedexpr); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.stub b/src/soc/marvell/mvmap2315/bootblock.stub new file mode 100644 index 0000000..0793599 --- /dev/null +++ b/src/soc/marvell/mvmap2315/bootblock.stub @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* This is a dummy file to replace bootblock.bin in the final coreboot + * image since bootblobk is been bypassed and the system is jumping + * directory to romstage from bootROM + */ diff --git a/src/soc/marvell/mvmap2315/cbmem.c b/src/soc/marvell/mvmap2315/cbmem.c new file mode 100644 index 0000000..a78c2ca --- /dev/null +++ b/src/soc/marvell/mvmap2315/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)CONFIG_RAMTOP; +} diff --git a/src/soc/marvell/mvmap2315/clock.c b/src/soc/marvell/mvmap2315/clock.c new file mode 100644 index 0000000..f3e17cc --- /dev/null +++ b/src/soc/marvell/mvmap2315/clock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/clock.h> +#include <arch/io.h> +#include <soc/clock.h> + +void clock_init_arm_generic_timer(void) +{ + u32 freq = MVMAP2315_CLK_M_KHZ * 1000; + u32 reg; + + set_cntfrq(freq); + + reg = read32(&mvmap2315_gentimer->cntfid0); + reg = freq; + write32(&mvmap2315_gentimer->cntfid0, reg); + + reg = read32(&mvmap2315_gentimer->cntcr); + reg |= MVMAP2315_GENTIMER_EN; + write32(&mvmap2315_gentimer->cntcr, reg); +} + +void configure_main_clk_pll(void) +{ + u32 reg; + + /* pick up speed as soon as possible */ + while (!(read32(&mvmap2315_pll->lock_status) + & MVMAP2315_PLL_LOCK)) + ; + + write32(&mvmap2315_apmu_clk->apaonclk_clkgenconfig, 1); + + reg = read32(&mvmap2315_pll->fixed_mode_ssc_mode); + reg &= ~MVMAP2315_PLL_BYPASS_EN; + write32(&mvmap2315_pll->fixed_mode_ssc_mode, reg); +} diff --git a/src/soc/marvell/mvmap2315/gic.c b/src/soc/marvell/mvmap2315/gic.c new file mode 100644 index 0000000..9d0f9a6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/gic.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <gic.h> + +/* Return a pointer to the base of the GIC distributor mmio region. */ +void *gicd_base(void) +{ + return (void *)MVMAP2315_GICD_BASE; +} + +/* Return a pointer to the base of the GIC cpu mmio region. */ +void *gicc_base(void) +{ + return (void *)MVMAP2315_GICC_BASE; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h new file mode 100644 index 0000000..6cf5db2 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ +#define __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum { + MVMAP2315_RAM_BASE = 0x00000000, + MVMAP2315_CBFS_BASE = 0x00400000, + MVMAP2315_MAIN_PLL_BASE = 0xE0125000, + MVMAP2315_APMU_CLK_BASE = 0xE0125400, + MVMAP2315_GENTIMER_BASE = 0xE0137000, + MVMAP2315_TIMER0_BASE = 0xE1020000, + MVMAP2315_MPMU_CLK_BASE = 0xEF000800, + MVMAP2315_GICD_BASE = 0xF0401000, + MVMAP2315_GICC_BASE = 0xF0402000, + MVMAP2315_FLASH_BASE = 0xFE000000, +}; + +#endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/assert.h b/src/soc/marvell/mvmap2315/include/soc/assert.h new file mode 100644 index 0000000..760e39b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/assert.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ASSERT_H__ +#define __SOC_MARVELL_MVMAP2315_ASSERT_H__ + +#include <stdint.h> +#include <stdlib.h> + +void __assert(const char *failedexpr, const char *file, int line); + +#define assert(x) \ + do { \ + if (!(x)) \ + __assert("assertion failed", \ + __FILE__, __LINE__); \ + } while (0) + +#endif /* __SOC_MARVELL_MVMAP2315_ASSERT_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h new file mode 100644 index 0000000..12d32c1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/clock.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_CLOCK_H__ +#define __SOC_MARVELL_MVMAP2315_CLOCK_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_CLK_M_KHZ 25000 +#define MVMAP2315_GENTIMER_EN BIT(0) + +struct mvmap2315_gentimer_regs { + u32 cntcr; + u32 cntsr; + u32 cntcvl; + u32 cntcvu; + u8 _reserved0[0x10]; + u32 cntfid0; + u8 _reserved1[0xfac]; + u32 pidr4; + u8 _reserved2[0x0c]; + u32 pidr0; + u32 pidr1; + u32 pidr2; + u32 pidr3; + u32 cidr0; + u32 cidr1; + u32 cidr2; + u32 cidr3; +}; + +check_member(mvmap2315_gentimer_regs, cidr3, 0xFFC); +static struct mvmap2315_gentimer_regs * const mvmap2315_gentimer + = (void *)MVMAP2315_GENTIMER_BASE; + +#define MVMAP2315_PLL_LOCK BIT(0) +#define MVMAP2315_PLL_BYPASS_EN BIT(16) + +struct mvmap2315_main_pll_regs { + u32 rst_prediv; + u32 mult_postdiv; + u32 kvco; + u32 misc; + u32 feedback_mode_deskew; + u32 offset_mode; + u32 fixed_mode_ssc_mode; + u32 ssc_freq_ssc_range; + u32 clk_ctrl_marvell_test; + u32 lock_status; + u32 reserve_out; +}; + +check_member(mvmap2315_main_pll_regs, reserve_out, 0x28); +static struct mvmap2315_main_pll_regs * const mvmap2315_pll + = (void *)MVMAP2315_MAIN_PLL_BASE; + +#define MVMAP2315_UART_CLK_EN BIT(0) +struct mvmap2315_apmu_clk_regs { + u32 uartfracdivcfg0; + u8 _reserved0[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved1[0x0c]; + u32 r4clkstatus; + u8 _reserved2[0x5c]; + u32 busclk2x_a2_clkgenconfig; + u32 busclk2x_a2_clkgenstatus; + u8 _reserved3[0x08]; + u32 busclk_mcix2_clkgenconfig; + u32 busclk_mcix2_clkgenstatus; + u32 busclk_mcix2_phyreset_clkgenconfig; + u32 busclk_mcix2_phyreset_clkgenstatus; + u32 busclk_mcix10_clkgenconfig; + u32 busclk_mcix10_clkgenstatus; + u32 busclk_mcix1_phyreset0_clkgenconfig; + u32 busclk_mcix1_phyreset0_clkgenstatus; + u32 busclk_mcix11_clkgenconfig; + u32 busclk_mcix11_clkgenstatus; + u32 busclk_mcix1_phyreset1_clkgenconfig; + u32 busclk_mcix1_phyreset1_clkgenstatus; + u32 busclk_mcix12_clkgenconfig; + u32 busclk_mcix12_clkgenstatus; + u32 busclk_mcix1_phyreset2_clkgenconfig; + u32 busclk_mcix1_phyreset2_clkgenstatus; + u32 busclk_mcix13_clkgenconfig; + u32 busclk_mcix13_clkgenstatus; + u32 busclk_mcix1_phyreset3_clkgenconfig; + u32 busclk_mcix1_phyreset3_clkgenstatus; + u8 _reserved4[0x10]; + u32 busclk_aes_clkgenconfig; + u32 busclk_aes_clkgenstatus; + u32 busclk_apaonbus_hs_clkgenconfig; + u32 busclk_apaonbus_hs_clkgenstatus; + u32 busclk_a2_clkgenconfig; + u32 busclk_a2_clkgenstatus; + u8 _reserved5[0x78]; + u32 apaonclk_clkgenconfig; + u32 apaonclk_clkgenstatus; + u32 apaonclk_apmucpu_clkgenconfig; + u32 apaonclk_apmucpu_clkgenstatus; + u32 apaonclk_sdmmc_clkgenconfig; + u32 apaonclk_sdmmc_clkgenstatus; + u8 _reserved6[0x08]; + u32 apaonclk_m2m_clkgenconfig; + u32 apaonclk_m2m_clkgenstatus; + u32 apaonclk_apb_clkgenconfig; + u32 apaonclk_apb_clkgenstatus; + u8 _reserved7[0x50]; + u32 bistclk_clkgenconfig; + u32 bistclk_clkgenstatus; + u32 bistclk_a2reset_clkgenconfig; + u32 bistclk_a2reset_clkgenstatus; + u32 bistclk_apcpureset_clkgenconfig; + u32 bistclk_apcpureset_clkgenstatus; + u32 bistclk_coresightreset_clkgenconfig; + u32 bistclk_coresightreset_clkgenstatus; + u32 bistclk_mcflcreset_clkgenconfig; + u32 bistclk_mcflcreset_clkgenstatus; + u8 _reserved8[0x08]; + u32 bistclk_gpu3dreset_clkgenconfig; + u32 bistclk_gpu3dreset_clkgenstatus; + u32 bistclk_gpu3dcorereset0_clkgenconfig; + u32 bistclk_gpu3dcorereset0_clkgenstatus; + u32 bistclk_gpu3dcorereset1_clkgenconfig; + u32 bistclk_gpu3dcorereset1_clkgenstatus; + u32 bistclk_gpu3dcorereset2_clkgenconfig; + u32 bistclk_gpu3dcorereset2_clkgenstatus; + u32 bistclk_gpu3dcorereset3_clkgenconfig; + u32 bistclk_gpu3dcorereset3_clkgenstatus; + u32 bistclk_gpu2dreset_clkgenconfig; + u32 bistclk_gpu2dreset_clkgenstatus; + u32 bistclk_zramreset_clkgenconfig; + u32 bistclk_zramreset_clkgenstatus; + u32 bistclk_vpuencreset_clkgenconfig; + u32 bistclk_vpuencreset_clkgenstatus; + u32 bistclk_vpudecreset_clkgenconfig; + u32 bistclk_vpudecreset_clkgenstatus; + u32 bistclk_displayreset_clkgenconfig; + u32 bistclk_displayreset_clkgenstatus; + u32 bistclk_edisplayreset_clkgenconfig; + u32 bistclk_edisplayreset_clkgenstatus; + u8 _reserved9[0x78]; + u32 sdmmcbaseclk_clkgenconfig; + u32 sdmmcbaseclk_clkgenstatus; + u8 _reserved10[0x08]; + u32 cfgclk_a2_clkgenconfig; + u32 cfgclk_a2_clkgenstatus; + u8 _reserved11[0x08]; + u32 uartclk0_clkgenconfig; + u32 uartclk0_clkgenstatus; + u8 _reserved12[0x08]; + u32 uartclk1_clkgenconfig; + u32 uartclk1_clkgenstatus; + u8 _reserved13[0x08]; + u32 sspclk0_clkgenconfig; + u32 sspclk0_clkgenstatus; + u8 _reserved14[0x08]; + u32 sspclk1_clkgenconfig; + u32 sspclk1_clkgenstatus; + u8 _reserved15[0x08]; + u32 i2cclk0_clkgenconfig; + u32 i2cclk0_clkgenstatus; + u8 _reserved16[0x08]; + u32 i2cclk1_clkgenconfig; + u32 i2cclk1_clkgenstatus; + u8 _reserved17[0x08]; + u32 i2cclk2_clkgenconfig; + u32 i2cclk2_clkgenstatus; + u8 _reserved18[0x08]; + u32 i2cclk3_clkgenconfig; + u32 i2cclk3_clkgenstatus; + u8 _reserved19[0x08]; + u32 i2cclk4_clkgenconfig; + u32 i2cclk4_clkgenstatus; +}; + +check_member(mvmap2315_apmu_clk_regs, i2cclk4_clkgenstatus, 0x3A4); +static struct mvmap2315_apmu_clk_regs * const mvmap2315_apmu_clk + = (void *)MVMAP2315_APMU_CLK_BASE; + +#define MVMAP2315_AP_RST_EN BIT(0) +#define MVMAP2315_MCU_RST_EN BIT(0) +struct mvmap2315_mpmu_clk_regs { + u32 resetap; + u32 resetmcu; + u32 resetstatus; + u8 _reserved0[4]; + u32 apaudiopllselect; + u8 _reserved1[0x0c]; + u32 sspa_asrc_rx_clk0; + u32 sspa_asrc_rx_clk1; + u32 sspa_asrc_rx_clk2; + u32 sspa_asrc_tx_clk0; + u32 sspa_asrc_tx_clk1; + u32 sspa_asrc_tx_clk2; + u32 dmic_asrc_clk; + u8 _reserved2[4]; + u32 uartfracdivcfg0; + u8 _reserved3[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved4[0xcc]; + u32 clk32k_clkgenconfig; + u32 clk32k_clkgenstatus; + u8 _reserved5[0x08]; + u32 cpudbgclk_clkgenconfig; + u32 cpudbgclk_clkgenstatus; + u8 _reserved6[0x08]; + u32 m4clk_bist_clkgenconfig; + u32 m4clk_bist_clkgenstatus; + u8 _reserved7[0x08]; + u32 bspiclk_clkgenconfig; + u32 bspiclk_clkgenstatus; + u8 _reserved8[0x08]; + u32 dmicclk_clkgenconfig; + u32 dmicclk_clkgenstatus; + u8 _reserved9[0x48]; + u32 sspaclk0_clkgenconfig; + u32 sspaclk0_clkgenstatus; + u32 sspaclk1_clkgenconfig; + u32 sspaclk1_clkgenstatus; + u32 sspaclk2_clkgenconfig; + u32 sspaclk2_clkgenstatus; + u8 _reserved10[0x38]; + u32 mcuclk_clkgenconfig; + u32 mcuclk_clkgenstatus; + u8 _reserved11[0x08]; + u32 mcuclk_cdma_clkgenconfig; + u32 mcuclk_cdma_clkgenstatus; + u8 _reserved12[0x08]; + u32 mcuclk_bspi_clkgenconfig; + u32 mcuclk_bspi_clkgenstatus; + u8 _reserved13[0x08]; + u32 mcuclk_owi_clkgenconfig; + u32 mcuclk_owi_clkgenstatus; + u8 _reserved14[0x08]; + u32 mcuclk_uart0_clkgenconfig; + u32 mcuclk_uart0_clkgenstatus; + u8 _reserved15[0x08]; + u32 mcuclk_uart1_clkgenconfig; + u32 mcuclk_uart1_clkgenstatus; + u8 _reserved16[0x08]; + u32 mcuclk_ssp0_clkgenconfig; + u32 mcuclk_ssp0_clkgenstatus; + u8 _reserved17[0x08]; + u32 mcuclk_ssp1_clkgenconfig; + u32 mcuclk_ssp1_clkgenstatus; + u8 _reserved18[0x08]; + u32 mcuclk_sspa0_clkgenconfig; + u32 mcuclk_sspa0_clkgenstatus; + u8 _reserved19[0x08]; + u32 mcuclk_sspa1_clkgenconfig; + u32 mcuclk_sspa1_clkgenstatus; + u8 _reserved20[0x08]; + u32 mcuclk_sspa2_clkgenconfig; + u32 mcuclk_sspa2_clkgenstatus; + u8 _reserved21[0x08]; + u32 mcuclk_dmic0_clkgenconfig; + u32 mcuclk_dmic0_clkgenstatus; + u8 _reserved22[0x08]; + u32 mcuclk_dmic1_clkgenconfig; + u32 mcuclk_dmic1_clkgenstatus; + u8 _reserved23[0x08]; + u32 mcuclk_dmic2_clkgenconfig; + u32 mcuclk_dmic2_clkgenstatus; + u8 _reserved24[0x08]; + u32 mcuclk_dmic3_clkgenconfig; + u32 mcuclk_dmic3_clkgenstatus; + u8 _reserved25[0x18]; + u32 dmic_dclk0_clkgenconfig; + u32 dmic_dclk0_clkgenstatus; + u8 _reserved26[0x08]; + u32 dmic_dclk1_clkgenconfig; + u32 dmic_dclk1_clkgenstatus; + u8 _reserved27[0x08]; + u32 dmic_dclk2_clkgenconfig; + u32 dmic_dclk2_clkgenstatus; + u8 _reserved28[0x08]; + u32 dmic_dclk3_clkgenconfig; + u32 dmic_dclk3_clkgenstatus; + u8 _reserved29[0x08]; + u32 dmic_engdetclk_clkgenconfig; + u32 dmic_engdetclk_clkgenstatus; + u8 _reserved30[0x38]; + u32 refclk_clkgenconfig; + u32 refclk_clkgenstatus; + u8 _reserved31[0x08]; + u32 refclk_ssp0_clkgenconfig; + u32 refclk_ssp0_clkgenstatus; + u8 _reserved32[0x08]; + u32 refclk_ssp1_clkgenconfig; + u32 refclk_ssp1_clkgenstatus; + u8 _reserved33[0x08]; + u32 refclk_uart0_clkgenconfig; + u32 refclk_uart0_clkgenstatus; + u8 _reserved34[0x08]; + u32 refclk_uart1_clkgenconfig; + u32 refclk_uart1_clkgenstatus; + u8 _reserved35[0x08]; + u32 refclk_i2c0_clkgenconfig; + u32 refclk_i2c0_clkgenstatus; + u8 _reserved36[0x08]; + u32 refclk_i2c1_clkgenconfig; + u32 refclk_i2c1_clkgenstatus; + u8 _reserved37[0x08]; + u32 refclk_i2c2_clkgenconfig; + u32 refclk_i2c2_clkgenstatus; + u8 _reserved38[0x08]; + u32 refclk_i2c3_clkgenconfig; + u32 refclk_i2c3_clkgenstatus; + u8 _reserved39[0x08]; + u32 refclk_i2c4_clkgenconfig; + u32 refclk_i2c4_clkgenstatus; + u8 _reserved40[0x08]; + u32 refclk_i2c5_clkgenconfig; + u32 refclk_i2c5_clkgenstatus; + u8 _reserved41[0x08]; + u32 refclk_sspa0_clkgenconfig; + u32 refclk_sspa0_clkgenstatus; + u8 _reserved42[0x08]; + u32 refclk_sspa1_clkgenconfig; + u32 refclk_sspa1_clkgenstatus; + u8 _reserved43[0x08]; + u32 refclk_sspa2_clkgenconfig; + u32 refclk_sspa2_clkgenstatus; + u8 _reserved44[0x08]; + u32 tsenclk_clkgenconfig; + u32 tsenclk_clkgenstatus; + u8 _reserved45[0x08]; + u32 ap_tsenclk_clkgenconfig; + u32 ap_tsenclk_clkgenstatus; + u8 _reserved46[0x08]; + u32 sspa_mclk_clkgenconfig; + u32 sspa_mclk_clkgenstatus; +}; + +check_member(mvmap2315_mpmu_clk_regs, sspa_mclk_clkgenstatus, 0x484); +static struct mvmap2315_mpmu_clk_regs * const mvmap2315_mpmu_clk + = (void *)MVMAP2315_MPMU_CLK_BASE; + +void clock_init_arm_generic_timer(void); +void configure_main_clk_pll(void); + +#endif /* __SOC_MARVELL_MVMAP2315_CLOCK_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/memlayout.ld b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld new file mode 100644 index 0000000..665e4f5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + +#if ENV_RAMSTAGE + TIMESTAMP(0x00060010, 128K) + STACK(0x00080010, 8K) +#endif + + VBOOT2_WORK(0x00082010, 16K) + VERSTAGE(0x1A0000, 128K) + POSTRAM_CBFS_CACHE(0x1C0000, 256K) + RAMSTAGE(0x00200000, 640K) + TTB(0x00300000, 1024K) + + SRAM_START(0xE0000000) + + /* The bootblock code won't actually be used, but the make process + * will fail if we don't provide a link address for it. Using LCM + * memory that is actually assigned to the bootROM so we don't + * use any LCM memory needed by coreboot code that will actually + * run. + */ + BOOTBLOCK(0xE0000000, 16K) + + /* The first 40K of LCM memory is reserved for the validated BDB + * as well as for bootROM usage when it is executing callbacks. + */ + + /* ROMSTAGE will be placed starting at the start of the second + * 32K segment in LCM. The Romstage code must not exceed 80KB, + * or it will encroach into LCM space reserved for APMU firmware + */ + ROMSTAGE(0xE0008000, 80K) + PRERAM_CBFS_CACHE(0xE001C000, 256) + PRERAM_CBMEM_CONSOLE(0xE001C100, 8K) + +#if ENV_ROMSTAGE + STACK(0xE001E100, 2K) + TIMESTAMP(0xE001E900, 1K) +#endif + + /* the folowing 2.5K are reserved for FIQ stack use + * memory address higher than 0xE001F700 + */ + + SRAM_END(0xE0020000) +} diff --git a/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h new file mode 100644 index 0000000..8c51367 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ +#define __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ + +#include <stdint.h> +#include <stdlib.h> + +#define MVMAP2315_DEVICE_SIZE 0x7E000000 +#define MVMAP2315_FLASH_SIZE 0x02000000 + +void mvmap2315_mmu_init(void); + +#endif /*__SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__*/ diff --git a/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h new file mode 100644 index 0000000..79c477b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ +#define __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_TIMER_T1CR_TE BIT(0) +#define MVMAP2315_TIMER_T1CR_TM BIT(1) +#define MVMAP2315_TIMER_T1CR_TIM BIT(2) +#define MVMAP2315_TIMER_T1CR_TPWM BIT(3) + +struct mvmap2315_timer_regs { + u32 t1lc; + u32 t1cv; + u32 t1cr; + u32 t1eoi; + u32 t1is; + u8 _reserved0[0x8c]; + u32 tis; + u32 teoi; + u32 tris; + u32 tcv; + u32 t1lc2; +}; + +check_member(mvmap2315_timer_regs, t1lc2, 0xB0); +static struct mvmap2315_timer_regs * const mvmap2315_timer0 + = (void *)MVMAP2315_TIMER0_BASE; + +void start_monotonic_timer(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/power.h b/src/soc/marvell/mvmap2315/include/soc/power.h new file mode 100644 index 0000000..308f657 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/power.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_POWER_H__ +#define __SOC_MARVELL_MVMAP2315_POWER_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum boot_paths { + NO_BOOT = 0, + CHARGING_SCREEN = 1, + FULL_BOOT = 2 +}; + +void no_boot(void); +void full_boot(void); +void charging_screen(void); +void start_ap_cores(void *entry); +u32 get_boot_path(void); + +#endif /* __SOC_MARVELL_MVMAP2315_POWER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/ramstage.h b/src/soc/marvell/mvmap2315/include/soc/ramstage.h new file mode 100644 index 0000000..61608cf --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/ramstage.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ +#define __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ + +#include <stdint.h> +#include <stdlib.h> + +void ramstage_entry(void); + +#endif /* __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ */ diff --git a/src/soc/marvell/mvmap2315/media.c b/src/soc/marvell/mvmap2315/media.c new file mode 100644 index 0000000..80d4281 --- /dev/null +++ b/src/soc/marvell/mvmap2315/media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static struct mem_region_device mdev = + MEM_REGION_DEV_RO_INIT((void *)MVMAP2315_CBFS_BASE, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &mdev.rdev; +} diff --git a/src/soc/marvell/mvmap2315/mmu_operations.c b/src/soc/marvell/mvmap2315/mmu_operations.c new file mode 100644 index 0000000..105dd72 --- /dev/null +++ b/src/soc/marvell/mvmap2315/mmu_operations.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> +#include <memrange.h> +#include <arch/mmu.h> +#include <soc/addressmap.h> +#include <soc/mmu_operations.h> + +static void mvmap2315_mmu_config(void) +{ + const unsigned long ram_mem = MA_MEM | MA_NS | MA_RW; + const unsigned long dev_mem = MA_DEV | MA_S | MA_RW; + const unsigned long flash_mem = MA_MEM | MA_S | MA_RW; + + mmu_config_range((void *)MVMAP2315_RAM_BASE, (2UL * GiB), ram_mem); + + mmu_config_range((void *)(2UL * GiB), + MVMAP2315_DEVICE_SIZE, dev_mem); + + mmu_config_range((void *)MVMAP2315_FLASH_BASE, + MVMAP2315_FLASH_SIZE, flash_mem); +} + +void mvmap2315_mmu_init(void) +{ + mmu_init(); + + mvmap2315_mmu_config(); + + mmu_enable(); +} diff --git a/src/soc/marvell/mvmap2315/monotonic_timer.c b/src/soc/marvell/mvmap2315/monotonic_timer.c new file mode 100644 index 0000000..2316798 --- /dev/null +++ b/src/soc/marvell/mvmap2315/monotonic_timer.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/monotonic_timer.h> +#include <timer.h> + +void start_monotonic_timer(void) +{ + u32 reg; + + reg = read32(&mvmap2315_timer0->t1cr); + + /* disable timer */ + reg &= ~MVMAP2315_TIMER_T1CR_TE; + /* set to free-running mode (loads max value at timer expiration) */ + reg &= ~MVMAP2315_TIMER_T1CR_TM; + /* mask interrupt (not currently used) */ + reg |= MVMAP2315_TIMER_T1CR_TIM; + /* disable PWM output */ + reg &= ~MVMAP2315_TIMER_T1CR_TPWM; + + write32(&mvmap2315_timer0->t1cr, reg); + + /* perform dummy read to clear all active interrupts */ + reg = read32(&mvmap2315_timer0->t1eoi); + + /* must provide an initial load count even in free-running mode */ + reg = read32(&mvmap2315_timer0->t1lc); + reg = 0xFFFFFFFF; + write32(&mvmap2315_timer0->t1lc, reg); + + /* enable timer */ + reg = read32(&mvmap2315_timer0->t1cr); + reg |= MVMAP2315_TIMER_T1CR_TE; + write32(&mvmap2315_timer0->t1cr, reg); + + /* busy wait until timer count is non-zero */ + while (!read32(&mvmap2315_timer0->t1cv)) + ; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + u32 reg; + + /* invert count to change from down to up count */ + reg = ~read32(&mvmap2315_timer0->t1cv); + + mt->microseconds = (long)(reg / 13); +} diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c new file mode 100644 index 0000000..578fb51 --- /dev/null +++ b/src/soc/marvell/mvmap2315/power.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/power.h> + +void start_ap_cores(void *entry) +{ + /*TODO: start_ap_cores */ +} + +void no_boot(void) +{ + /*TODO: impelement no_boot */ +} + +void charging_screen(void) +{ + /*TODO: impelement charging_screen */ +} + +void full_boot(void) +{ + /*TODO: impelement full_boot */ +} + +u32 get_boot_path(void) +{ + return FULL_BOOT; +} diff --git a/src/soc/marvell/mvmap2315/ramstage.c b/src/soc/marvell/mvmap2315/ramstage.c new file mode 100644 index 0000000..bd830c8 --- /dev/null +++ b/src/soc/marvell/mvmap2315/ramstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stages.h> +#include <console/console.h> +#include <gic.h> +#include <soc/clock.h> +#include <soc/mmu_operations.h> +#include <soc/ramstage.h> + +void ramstage_entry(void) +{ + gic_init(); + + mvmap2315_mmu_init(); + + clock_init_arm_generic_timer(); + + /* Jump to boot state machine in common code. */ + main(); +} diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c new file mode 100644 index 0000000..8924d01 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <soc/assert.h> +#include <soc/clock.h> +#include <soc/monotonic_timer.h> +#include <soc/power.h> +#include <timestamp.h> + +/* + * main -- romstage main code. + * + */ +void main(void) +{ + u32 boot_path; + + configure_main_clk_pll(); + + timestamp_init(0); + + asm volatile ("bl cpu_enable_icache" : : : "r0", "r1"); + + asm volatile ("bl cpu_init" : : : "r0"); + + start_monotonic_timer(); + + timestamp_add_now(TS_START_ROMSTAGE); + + boot_path = get_boot_path(); + + switch (boot_path) { + case NO_BOOT: + no_boot(); + break; + + case CHARGING_SCREEN: + charging_screen(); + break; + + case FULL_BOOT: + full_boot(); + break; + } + + timestamp_add_now(TS_END_ROMSTAGE); + + run_ramstage(); +} + +static void romstage_continue(void) +{ + /* TODO: R4 Functionality to be added */ + while (1) + ; +} + +void platform_prog_run(struct prog *prog) +{ + if (!prog_entry(prog)) + __assert("ramstage entrypoint not found", __FILE__, __LINE__); + + start_ap_cores(prog_entry(prog)); + romstage_continue(); +} diff --git a/src/soc/marvell/mvmap2315/romstage_asm.S b/src/soc/marvell/mvmap2315/romstage_asm.S new file mode 100644 index 0000000..3fac9a5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage_asm.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +# .balign 16 + +.arm +ENTRY(stage_entry) + blx _thumb_start +ENDPROC(stage_entry) + +.thumb +ENTRY(_thumb_start) + + ldr sp, =_estack + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + nop + + /* First arg: start of memory block */ + ldr a1, =_bss + + /* Second arg: fill value */ + mov a2, #0 + ldr a3, =_ebss + + /* Third arg: length of block */ + sub a3, a3, a1 + bl memset + + /* initializing FIQ stack */ + mrs r0, CPSR + mov r1, r0 + bic r1, r1, #0x40 + orr r0, r0, #0x51 + and r0, r0, #0xFFFFFFF1 + msr CPSR_c, r0 + ldr sp, =0xE001F700 + orr r0, r0, #0x10 + and r0, r0, #0xFFFFFFB0 + msr CPSR_cf, r1 + + /* call the code to authenticate this */ + bl main + /* should never return from this */ +ENDPROC(_thumb_start) diff --git a/src/soc/marvell/mvmap2315/soc.c b/src/soc/marvell/mvmap2315/soc.c new file mode 100644 index 0000000..a206e7b --- /dev/null +++ b/src/soc/marvell/mvmap2315/soc.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> + +static void soc_enable(device_t dev) +{ + /* Provide RAM resource for use by coreboot. Memory area needs to + * inclue load address for the payload. note that base and size are + * in Kbytes, so actual base and size are 0x10000000. + */ + + ram_resource(dev, 0, 0x0, CONFIG_RAMTOP / 1024); +} + +static struct device_operations soc_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = soc_enable, + .init = DEVICE_NOOP, + .scan_bus = NULL, +}; + +static void enable_mvmap2315_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_marvell_mvmap2315_ops = { + CHIP_NAME("SOC Marvell MVMAP2315") + .enable_dev = enable_mvmap2315_dev, +}; diff --git a/src/soc/marvell/mvmap2315/stage_entry.S b/src/soc/marvell/mvmap2315/stage_entry.S new file mode 100644 index 0000000..1bdf2d6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/stage_entry.S @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(stage_entry) + + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c new file mode 100644 index 0000000..a486ee4 --- /dev/null +++ b/src/soc/marvell/mvmap2315/uart.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <boot/coreboot_tables.h> + +void uart_init(int idx) +{ + /*TODO: implement uart_init */ +} + +void uart_tx_byte(int idx, unsigned char data) +{ + /*TODO: implement uart_tx_byte */ +} + +void uart_tx_flush(int idx) +{ + /*TODO: implement uart_tx_flush */ +} + +unsigned char uart_rx_byte(int idx) +{ + /*TODO: implement uart_rx_byte */ + return 0; +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + /*TODO: implement uart_fill_lb */ +} +#endif

1 0

Patch set updated for coreboot: Add stub implementation of MVMAP2315 SOC
by hakim giydan 05 Jul '16

05 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15506 -gerrit commit 4eb70107cff78b3d762b4c02cbc96bbdcd18082f Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Tue Jul 5 14:04:03 2016 -0700 Add stub implementation of MVMAP2315 SOC Most things still need to be filled in, but this will allow us to build boards which use this SOC Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used as templates to create this directory Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Kconfig | 37 +++ src/soc/marvell/mvmap2315/Makefile.inc | 53 +++ src/soc/marvell/mvmap2315/assert.c | 42 +++ src/soc/marvell/mvmap2315/bootblock.stub | 20 ++ src/soc/marvell/mvmap2315/cbmem.c | 25 ++ src/soc/marvell/mvmap2315/clock.c | 50 +++ src/soc/marvell/mvmap2315/gic.c | 30 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 35 ++ src/soc/marvell/mvmap2315/include/soc/assert.h | 31 ++ src/soc/marvell/mvmap2315/include/soc/clock.h | 358 +++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/memlayout.ld | 66 ++++ .../marvell/mvmap2315/include/soc/mmu_operations.h | 27 ++ .../mvmap2315/include/soc/monotonic_timer.h | 50 +++ src/soc/marvell/mvmap2315/include/soc/power.h | 33 ++ src/soc/marvell/mvmap2315/include/soc/ramstage.h | 23 ++ src/soc/marvell/mvmap2315/media.c | 26 ++ src/soc/marvell/mvmap2315/mmu_operations.c | 46 +++ src/soc/marvell/mvmap2315/monotonic_timer.c | 63 ++++ src/soc/marvell/mvmap2315/power.c | 41 +++ src/soc/marvell/mvmap2315/ramstage.c | 34 ++ src/soc/marvell/mvmap2315/romstage.c | 78 +++++ src/soc/marvell/mvmap2315/romstage_asm.S | 66 ++++ src/soc/marvell/mvmap2315/soc.c | 46 +++ src/soc/marvell/mvmap2315/stage_entry.S | 26 ++ src/soc/marvell/mvmap2315/uart.c | 46 +++ 25 files changed, 1352 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Kconfig b/src/soc/marvell/mvmap2315/Kconfig new file mode 100644 index 0000000..cfa622e --- /dev/null +++ b/src/soc/marvell/mvmap2315/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_MARVELL_MVMAP2315 + bool + default n + select ARM_LPAE + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV7_R + select ARCH_VERSTAGE_ARMV7_R + select GENERIC_UDELAY + select GIC + select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select UNCOMPRESSED_RAMSTAGE + select VBOOT_DYNAMIC_WORK_BUFFER + +if SOC_MARVELL_MVMAP2315 + +config EMULATION + bool + default n +endif diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc new file mode 100644 index 0000000..d80453a --- /dev/null +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marvell, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += assert.c +ramstage-y += cbmem.c +ramstage-y += clock.c +ramstage-y += gic.c +ramstage-y += media.c +ramstage-y += mmu_operations.c +ramstage-y += monotonic_timer.c +ramstage-y += ramstage.c +ramstage-y += soc.c +ramstage-y += stage_entry.S +ramstage-y += uart.c + +romstage-y += assert.c +romstage-y += cbmem.c +romstage-y += clock.c +romstage-y += media.c +romstage-y += monotonic_timer.c +romstage-y += power.c +romstage-y += romstage_asm.S +romstage-y += romstage.c +romstage-y += uart.c + +CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ + +all: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.bin + +## Replacing bootblock.bin with bootblock.stub since bootROM load and +## jump to romstage code directly. +## it is necessary to create a bootblock.stub file, or the final coreboot +## make stage will fail when it can't find bootblock.bin. + +$(objcbfs)/bootblock.bin: src/soc/marvell/mvmap2315/bootblock.stub + cat src/soc/marvell/mvmap2315/bootblock.stub > $(objcbfs)/bootblock.bin + +## generating romtage.bin since it is required to create the BDB + +$(objcbfs)/romstage.bin: $(objcbfs)/romstage.elf + $(OBJCOPY_romstage) -O binary $(objcbfs)/romstage.elf $(objcbfs)/romstage.bin diff --git a/src/soc/marvell/mvmap2315/assert.c b/src/soc/marvell/mvmap2315/assert.c new file mode 100644 index 0000000..f4c498c --- /dev/null +++ b/src/soc/marvell/mvmap2315/assert.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <console/console.h> +#include <soc/assert.h> +#include <stddef.h> + +/*Trivial __assert_func */ +static void __assert_func(const char *file, int line, + const char *func, + const char *failedexpr) +{ +#ifdef CONFIG_CONSOLE_SERIAL_UART + printk(BIOS_ERR, "\n\nASSERT!!\n\n"); + printk(BIOS_ERR, "%s:%d - %s - %s\n", file, line, func, failedexpr); +#endif + + /* Purposely empty */ + while (1) + ; +} + +/* Minimal __assert() */ +void __assert(const char *failedexpr, const char *file, int line) +{ + __assert_func(file, line, NULL, failedexpr); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.stub b/src/soc/marvell/mvmap2315/bootblock.stub new file mode 100644 index 0000000..0793599 --- /dev/null +++ b/src/soc/marvell/mvmap2315/bootblock.stub @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* This is a dummy file to replace bootblock.bin in the final coreboot + * image since bootblobk is been bypassed and the system is jumping + * directory to romstage from bootROM + */ diff --git a/src/soc/marvell/mvmap2315/cbmem.c b/src/soc/marvell/mvmap2315/cbmem.c new file mode 100644 index 0000000..a78c2ca --- /dev/null +++ b/src/soc/marvell/mvmap2315/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stddef.h> + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)CONFIG_RAMTOP; +} diff --git a/src/soc/marvell/mvmap2315/clock.c b/src/soc/marvell/mvmap2315/clock.c new file mode 100644 index 0000000..f3e17cc --- /dev/null +++ b/src/soc/marvell/mvmap2315/clock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/clock.h> +#include <arch/io.h> +#include <soc/clock.h> + +void clock_init_arm_generic_timer(void) +{ + u32 freq = MVMAP2315_CLK_M_KHZ * 1000; + u32 reg; + + set_cntfrq(freq); + + reg = read32(&mvmap2315_gentimer->cntfid0); + reg = freq; + write32(&mvmap2315_gentimer->cntfid0, reg); + + reg = read32(&mvmap2315_gentimer->cntcr); + reg |= MVMAP2315_GENTIMER_EN; + write32(&mvmap2315_gentimer->cntcr, reg); +} + +void configure_main_clk_pll(void) +{ + u32 reg; + + /* pick up speed as soon as possible */ + while (!(read32(&mvmap2315_pll->lock_status) + & MVMAP2315_PLL_LOCK)) + ; + + write32(&mvmap2315_apmu_clk->apaonclk_clkgenconfig, 1); + + reg = read32(&mvmap2315_pll->fixed_mode_ssc_mode); + reg &= ~MVMAP2315_PLL_BYPASS_EN; + write32(&mvmap2315_pll->fixed_mode_ssc_mode, reg); +} diff --git a/src/soc/marvell/mvmap2315/gic.c b/src/soc/marvell/mvmap2315/gic.c new file mode 100644 index 0000000..9d0f9a6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/gic.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <gic.h> + +/* Return a pointer to the base of the GIC distributor mmio region. */ +void *gicd_base(void) +{ + return (void *)MVMAP2315_GICD_BASE; +} + +/* Return a pointer to the base of the GIC cpu mmio region. */ +void *gicc_base(void) +{ + return (void *)MVMAP2315_GICC_BASE; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h new file mode 100644 index 0000000..6cf5db2 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ +#define __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum { + MVMAP2315_RAM_BASE = 0x00000000, + MVMAP2315_CBFS_BASE = 0x00400000, + MVMAP2315_MAIN_PLL_BASE = 0xE0125000, + MVMAP2315_APMU_CLK_BASE = 0xE0125400, + MVMAP2315_GENTIMER_BASE = 0xE0137000, + MVMAP2315_TIMER0_BASE = 0xE1020000, + MVMAP2315_MPMU_CLK_BASE = 0xEF000800, + MVMAP2315_GICD_BASE = 0xF0401000, + MVMAP2315_GICC_BASE = 0xF0402000, + MVMAP2315_FLASH_BASE = 0xFE000000, +}; + +#endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/assert.h b/src/soc/marvell/mvmap2315/include/soc/assert.h new file mode 100644 index 0000000..760e39b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/assert.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_ASSERT_H__ +#define __SOC_MARVELL_MVMAP2315_ASSERT_H__ + +#include <stdint.h> +#include <stdlib.h> + +void __assert(const char *failedexpr, const char *file, int line); + +#define assert(x) \ + do { \ + if (!(x)) \ + __assert("assertion failed", \ + __FILE__, __LINE__); \ + } while (0) + +#endif /* __SOC_MARVELL_MVMAP2315_ASSERT_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h new file mode 100644 index 0000000..12d32c1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/clock.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_CLOCK_H__ +#define __SOC_MARVELL_MVMAP2315_CLOCK_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_CLK_M_KHZ 25000 +#define MVMAP2315_GENTIMER_EN BIT(0) + +struct mvmap2315_gentimer_regs { + u32 cntcr; + u32 cntsr; + u32 cntcvl; + u32 cntcvu; + u8 _reserved0[0x10]; + u32 cntfid0; + u8 _reserved1[0xfac]; + u32 pidr4; + u8 _reserved2[0x0c]; + u32 pidr0; + u32 pidr1; + u32 pidr2; + u32 pidr3; + u32 cidr0; + u32 cidr1; + u32 cidr2; + u32 cidr3; +}; + +check_member(mvmap2315_gentimer_regs, cidr3, 0xFFC); +static struct mvmap2315_gentimer_regs * const mvmap2315_gentimer + = (void *)MVMAP2315_GENTIMER_BASE; + +#define MVMAP2315_PLL_LOCK BIT(0) +#define MVMAP2315_PLL_BYPASS_EN BIT(16) + +struct mvmap2315_main_pll_regs { + u32 rst_prediv; + u32 mult_postdiv; + u32 kvco; + u32 misc; + u32 feedback_mode_deskew; + u32 offset_mode; + u32 fixed_mode_ssc_mode; + u32 ssc_freq_ssc_range; + u32 clk_ctrl_marvell_test; + u32 lock_status; + u32 reserve_out; +}; + +check_member(mvmap2315_main_pll_regs, reserve_out, 0x28); +static struct mvmap2315_main_pll_regs * const mvmap2315_pll + = (void *)MVMAP2315_MAIN_PLL_BASE; + +#define MVMAP2315_UART_CLK_EN BIT(0) +struct mvmap2315_apmu_clk_regs { + u32 uartfracdivcfg0; + u8 _reserved0[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved1[0x0c]; + u32 r4clkstatus; + u8 _reserved2[0x5c]; + u32 busclk2x_a2_clkgenconfig; + u32 busclk2x_a2_clkgenstatus; + u8 _reserved3[0x08]; + u32 busclk_mcix2_clkgenconfig; + u32 busclk_mcix2_clkgenstatus; + u32 busclk_mcix2_phyreset_clkgenconfig; + u32 busclk_mcix2_phyreset_clkgenstatus; + u32 busclk_mcix10_clkgenconfig; + u32 busclk_mcix10_clkgenstatus; + u32 busclk_mcix1_phyreset0_clkgenconfig; + u32 busclk_mcix1_phyreset0_clkgenstatus; + u32 busclk_mcix11_clkgenconfig; + u32 busclk_mcix11_clkgenstatus; + u32 busclk_mcix1_phyreset1_clkgenconfig; + u32 busclk_mcix1_phyreset1_clkgenstatus; + u32 busclk_mcix12_clkgenconfig; + u32 busclk_mcix12_clkgenstatus; + u32 busclk_mcix1_phyreset2_clkgenconfig; + u32 busclk_mcix1_phyreset2_clkgenstatus; + u32 busclk_mcix13_clkgenconfig; + u32 busclk_mcix13_clkgenstatus; + u32 busclk_mcix1_phyreset3_clkgenconfig; + u32 busclk_mcix1_phyreset3_clkgenstatus; + u8 _reserved4[0x10]; + u32 busclk_aes_clkgenconfig; + u32 busclk_aes_clkgenstatus; + u32 busclk_apaonbus_hs_clkgenconfig; + u32 busclk_apaonbus_hs_clkgenstatus; + u32 busclk_a2_clkgenconfig; + u32 busclk_a2_clkgenstatus; + u8 _reserved5[0x78]; + u32 apaonclk_clkgenconfig; + u32 apaonclk_clkgenstatus; + u32 apaonclk_apmucpu_clkgenconfig; + u32 apaonclk_apmucpu_clkgenstatus; + u32 apaonclk_sdmmc_clkgenconfig; + u32 apaonclk_sdmmc_clkgenstatus; + u8 _reserved6[0x08]; + u32 apaonclk_m2m_clkgenconfig; + u32 apaonclk_m2m_clkgenstatus; + u32 apaonclk_apb_clkgenconfig; + u32 apaonclk_apb_clkgenstatus; + u8 _reserved7[0x50]; + u32 bistclk_clkgenconfig; + u32 bistclk_clkgenstatus; + u32 bistclk_a2reset_clkgenconfig; + u32 bistclk_a2reset_clkgenstatus; + u32 bistclk_apcpureset_clkgenconfig; + u32 bistclk_apcpureset_clkgenstatus; + u32 bistclk_coresightreset_clkgenconfig; + u32 bistclk_coresightreset_clkgenstatus; + u32 bistclk_mcflcreset_clkgenconfig; + u32 bistclk_mcflcreset_clkgenstatus; + u8 _reserved8[0x08]; + u32 bistclk_gpu3dreset_clkgenconfig; + u32 bistclk_gpu3dreset_clkgenstatus; + u32 bistclk_gpu3dcorereset0_clkgenconfig; + u32 bistclk_gpu3dcorereset0_clkgenstatus; + u32 bistclk_gpu3dcorereset1_clkgenconfig; + u32 bistclk_gpu3dcorereset1_clkgenstatus; + u32 bistclk_gpu3dcorereset2_clkgenconfig; + u32 bistclk_gpu3dcorereset2_clkgenstatus; + u32 bistclk_gpu3dcorereset3_clkgenconfig; + u32 bistclk_gpu3dcorereset3_clkgenstatus; + u32 bistclk_gpu2dreset_clkgenconfig; + u32 bistclk_gpu2dreset_clkgenstatus; + u32 bistclk_zramreset_clkgenconfig; + u32 bistclk_zramreset_clkgenstatus; + u32 bistclk_vpuencreset_clkgenconfig; + u32 bistclk_vpuencreset_clkgenstatus; + u32 bistclk_vpudecreset_clkgenconfig; + u32 bistclk_vpudecreset_clkgenstatus; + u32 bistclk_displayreset_clkgenconfig; + u32 bistclk_displayreset_clkgenstatus; + u32 bistclk_edisplayreset_clkgenconfig; + u32 bistclk_edisplayreset_clkgenstatus; + u8 _reserved9[0x78]; + u32 sdmmcbaseclk_clkgenconfig; + u32 sdmmcbaseclk_clkgenstatus; + u8 _reserved10[0x08]; + u32 cfgclk_a2_clkgenconfig; + u32 cfgclk_a2_clkgenstatus; + u8 _reserved11[0x08]; + u32 uartclk0_clkgenconfig; + u32 uartclk0_clkgenstatus; + u8 _reserved12[0x08]; + u32 uartclk1_clkgenconfig; + u32 uartclk1_clkgenstatus; + u8 _reserved13[0x08]; + u32 sspclk0_clkgenconfig; + u32 sspclk0_clkgenstatus; + u8 _reserved14[0x08]; + u32 sspclk1_clkgenconfig; + u32 sspclk1_clkgenstatus; + u8 _reserved15[0x08]; + u32 i2cclk0_clkgenconfig; + u32 i2cclk0_clkgenstatus; + u8 _reserved16[0x08]; + u32 i2cclk1_clkgenconfig; + u32 i2cclk1_clkgenstatus; + u8 _reserved17[0x08]; + u32 i2cclk2_clkgenconfig; + u32 i2cclk2_clkgenstatus; + u8 _reserved18[0x08]; + u32 i2cclk3_clkgenconfig; + u32 i2cclk3_clkgenstatus; + u8 _reserved19[0x08]; + u32 i2cclk4_clkgenconfig; + u32 i2cclk4_clkgenstatus; +}; + +check_member(mvmap2315_apmu_clk_regs, i2cclk4_clkgenstatus, 0x3A4); +static struct mvmap2315_apmu_clk_regs * const mvmap2315_apmu_clk + = (void *)MVMAP2315_APMU_CLK_BASE; + +#define MVMAP2315_AP_RST_EN BIT(0) +#define MVMAP2315_MCU_RST_EN BIT(0) +struct mvmap2315_mpmu_clk_regs { + u32 resetap; + u32 resetmcu; + u32 resetstatus; + u8 _reserved0[4]; + u32 apaudiopllselect; + u8 _reserved1[0x0c]; + u32 sspa_asrc_rx_clk0; + u32 sspa_asrc_rx_clk1; + u32 sspa_asrc_rx_clk2; + u32 sspa_asrc_tx_clk0; + u32 sspa_asrc_tx_clk1; + u32 sspa_asrc_tx_clk2; + u32 dmic_asrc_clk; + u8 _reserved2[4]; + u32 uartfracdivcfg0; + u8 _reserved3[0x0c]; + u32 uartfracdivcfg1; + u8 _reserved4[0xcc]; + u32 clk32k_clkgenconfig; + u32 clk32k_clkgenstatus; + u8 _reserved5[0x08]; + u32 cpudbgclk_clkgenconfig; + u32 cpudbgclk_clkgenstatus; + u8 _reserved6[0x08]; + u32 m4clk_bist_clkgenconfig; + u32 m4clk_bist_clkgenstatus; + u8 _reserved7[0x08]; + u32 bspiclk_clkgenconfig; + u32 bspiclk_clkgenstatus; + u8 _reserved8[0x08]; + u32 dmicclk_clkgenconfig; + u32 dmicclk_clkgenstatus; + u8 _reserved9[0x48]; + u32 sspaclk0_clkgenconfig; + u32 sspaclk0_clkgenstatus; + u32 sspaclk1_clkgenconfig; + u32 sspaclk1_clkgenstatus; + u32 sspaclk2_clkgenconfig; + u32 sspaclk2_clkgenstatus; + u8 _reserved10[0x38]; + u32 mcuclk_clkgenconfig; + u32 mcuclk_clkgenstatus; + u8 _reserved11[0x08]; + u32 mcuclk_cdma_clkgenconfig; + u32 mcuclk_cdma_clkgenstatus; + u8 _reserved12[0x08]; + u32 mcuclk_bspi_clkgenconfig; + u32 mcuclk_bspi_clkgenstatus; + u8 _reserved13[0x08]; + u32 mcuclk_owi_clkgenconfig; + u32 mcuclk_owi_clkgenstatus; + u8 _reserved14[0x08]; + u32 mcuclk_uart0_clkgenconfig; + u32 mcuclk_uart0_clkgenstatus; + u8 _reserved15[0x08]; + u32 mcuclk_uart1_clkgenconfig; + u32 mcuclk_uart1_clkgenstatus; + u8 _reserved16[0x08]; + u32 mcuclk_ssp0_clkgenconfig; + u32 mcuclk_ssp0_clkgenstatus; + u8 _reserved17[0x08]; + u32 mcuclk_ssp1_clkgenconfig; + u32 mcuclk_ssp1_clkgenstatus; + u8 _reserved18[0x08]; + u32 mcuclk_sspa0_clkgenconfig; + u32 mcuclk_sspa0_clkgenstatus; + u8 _reserved19[0x08]; + u32 mcuclk_sspa1_clkgenconfig; + u32 mcuclk_sspa1_clkgenstatus; + u8 _reserved20[0x08]; + u32 mcuclk_sspa2_clkgenconfig; + u32 mcuclk_sspa2_clkgenstatus; + u8 _reserved21[0x08]; + u32 mcuclk_dmic0_clkgenconfig; + u32 mcuclk_dmic0_clkgenstatus; + u8 _reserved22[0x08]; + u32 mcuclk_dmic1_clkgenconfig; + u32 mcuclk_dmic1_clkgenstatus; + u8 _reserved23[0x08]; + u32 mcuclk_dmic2_clkgenconfig; + u32 mcuclk_dmic2_clkgenstatus; + u8 _reserved24[0x08]; + u32 mcuclk_dmic3_clkgenconfig; + u32 mcuclk_dmic3_clkgenstatus; + u8 _reserved25[0x18]; + u32 dmic_dclk0_clkgenconfig; + u32 dmic_dclk0_clkgenstatus; + u8 _reserved26[0x08]; + u32 dmic_dclk1_clkgenconfig; + u32 dmic_dclk1_clkgenstatus; + u8 _reserved27[0x08]; + u32 dmic_dclk2_clkgenconfig; + u32 dmic_dclk2_clkgenstatus; + u8 _reserved28[0x08]; + u32 dmic_dclk3_clkgenconfig; + u32 dmic_dclk3_clkgenstatus; + u8 _reserved29[0x08]; + u32 dmic_engdetclk_clkgenconfig; + u32 dmic_engdetclk_clkgenstatus; + u8 _reserved30[0x38]; + u32 refclk_clkgenconfig; + u32 refclk_clkgenstatus; + u8 _reserved31[0x08]; + u32 refclk_ssp0_clkgenconfig; + u32 refclk_ssp0_clkgenstatus; + u8 _reserved32[0x08]; + u32 refclk_ssp1_clkgenconfig; + u32 refclk_ssp1_clkgenstatus; + u8 _reserved33[0x08]; + u32 refclk_uart0_clkgenconfig; + u32 refclk_uart0_clkgenstatus; + u8 _reserved34[0x08]; + u32 refclk_uart1_clkgenconfig; + u32 refclk_uart1_clkgenstatus; + u8 _reserved35[0x08]; + u32 refclk_i2c0_clkgenconfig; + u32 refclk_i2c0_clkgenstatus; + u8 _reserved36[0x08]; + u32 refclk_i2c1_clkgenconfig; + u32 refclk_i2c1_clkgenstatus; + u8 _reserved37[0x08]; + u32 refclk_i2c2_clkgenconfig; + u32 refclk_i2c2_clkgenstatus; + u8 _reserved38[0x08]; + u32 refclk_i2c3_clkgenconfig; + u32 refclk_i2c3_clkgenstatus; + u8 _reserved39[0x08]; + u32 refclk_i2c4_clkgenconfig; + u32 refclk_i2c4_clkgenstatus; + u8 _reserved40[0x08]; + u32 refclk_i2c5_clkgenconfig; + u32 refclk_i2c5_clkgenstatus; + u8 _reserved41[0x08]; + u32 refclk_sspa0_clkgenconfig; + u32 refclk_sspa0_clkgenstatus; + u8 _reserved42[0x08]; + u32 refclk_sspa1_clkgenconfig; + u32 refclk_sspa1_clkgenstatus; + u8 _reserved43[0x08]; + u32 refclk_sspa2_clkgenconfig; + u32 refclk_sspa2_clkgenstatus; + u8 _reserved44[0x08]; + u32 tsenclk_clkgenconfig; + u32 tsenclk_clkgenstatus; + u8 _reserved45[0x08]; + u32 ap_tsenclk_clkgenconfig; + u32 ap_tsenclk_clkgenstatus; + u8 _reserved46[0x08]; + u32 sspa_mclk_clkgenconfig; + u32 sspa_mclk_clkgenstatus; +}; + +check_member(mvmap2315_mpmu_clk_regs, sspa_mclk_clkgenstatus, 0x484); +static struct mvmap2315_mpmu_clk_regs * const mvmap2315_mpmu_clk + = (void *)MVMAP2315_MPMU_CLK_BASE; + +void clock_init_arm_generic_timer(void); +void configure_main_clk_pll(void); + +#endif /* __SOC_MARVELL_MVMAP2315_CLOCK_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/memlayout.ld b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld new file mode 100644 index 0000000..665e4f5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + +#if ENV_RAMSTAGE + TIMESTAMP(0x00060010, 128K) + STACK(0x00080010, 8K) +#endif + + VBOOT2_WORK(0x00082010, 16K) + VERSTAGE(0x1A0000, 128K) + POSTRAM_CBFS_CACHE(0x1C0000, 256K) + RAMSTAGE(0x00200000, 640K) + TTB(0x00300000, 1024K) + + SRAM_START(0xE0000000) + + /* The bootblock code won't actually be used, but the make process + * will fail if we don't provide a link address for it. Using LCM + * memory that is actually assigned to the bootROM so we don't + * use any LCM memory needed by coreboot code that will actually + * run. + */ + BOOTBLOCK(0xE0000000, 16K) + + /* The first 40K of LCM memory is reserved for the validated BDB + * as well as for bootROM usage when it is executing callbacks. + */ + + /* ROMSTAGE will be placed starting at the start of the second + * 32K segment in LCM. The Romstage code must not exceed 80KB, + * or it will encroach into LCM space reserved for APMU firmware + */ + ROMSTAGE(0xE0008000, 80K) + PRERAM_CBFS_CACHE(0xE001C000, 256) + PRERAM_CBMEM_CONSOLE(0xE001C100, 8K) + +#if ENV_ROMSTAGE + STACK(0xE001E100, 2K) + TIMESTAMP(0xE001E900, 1K) +#endif + + /* the folowing 2.5K are reserved for FIQ stack use + * memory address higher than 0xE001F700 + */ + + SRAM_END(0xE0020000) +} diff --git a/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h new file mode 100644 index 0000000..8c51367 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ +#define __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__ + +#include <stdint.h> +#include <stdlib.h> + +#define MVMAP2315_DEVICE_SIZE 0x7E000000 +#define MVMAP2315_FLASH_SIZE 0x02000000 + +void mvmap2315_mmu_init(void); + +#endif /*__SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__*/ diff --git a/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h new file mode 100644 index 0000000..79c477b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/monotonic_timer.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ +#define __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_TIMER_T1CR_TE BIT(0) +#define MVMAP2315_TIMER_T1CR_TM BIT(1) +#define MVMAP2315_TIMER_T1CR_TIM BIT(2) +#define MVMAP2315_TIMER_T1CR_TPWM BIT(3) + +struct mvmap2315_timer_regs { + u32 t1lc; + u32 t1cv; + u32 t1cr; + u32 t1eoi; + u32 t1is; + u8 _reserved0[0x8c]; + u32 tis; + u32 teoi; + u32 tris; + u32 tcv; + u32 t1lc2; +}; + +check_member(mvmap2315_timer_regs, t1lc2, 0xB0); +static struct mvmap2315_timer_regs * const mvmap2315_timer0 + = (void *)MVMAP2315_TIMER0_BASE; + +void start_monotonic_timer(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MONOTONIC_TIMER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/power.h b/src/soc/marvell/mvmap2315/include/soc/power.h new file mode 100644 index 0000000..308f657 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/power.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_POWER_H__ +#define __SOC_MARVELL_MVMAP2315_POWER_H__ + +#include <stdint.h> +#include <stdlib.h> + +enum boot_paths { + NO_BOOT = 0, + CHARGING_SCREEN = 1, + FULL_BOOT = 2 +}; + +void no_boot(void); +void full_boot(void); +void charging_screen(void); +void start_ap_cores(void *entry); +u32 get_boot_path(void); + +#endif /* __SOC_MARVELL_MVMAP2315_POWER_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/ramstage.h b/src/soc/marvell/mvmap2315/include/soc/ramstage.h new file mode 100644 index 0000000..61608cf --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/ramstage.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ +#define __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ + +#include <stdint.h> +#include <stdlib.h> + +void ramstage_entry(void); + +#endif /* __SOC_MARVELL_MVMAP2315_RAMSTAGE_H__ */ diff --git a/src/soc/marvell/mvmap2315/media.c b/src/soc/marvell/mvmap2315/media.c new file mode 100644 index 0000000..cafc85d --- /dev/null +++ b/src/soc/marvell/mvmap2315/media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static struct mem_region_device mdev = + MEM_REGION_DEV_INIT((void *)MVMAP2315_CBFS_BASE, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &mdev.rdev; +} diff --git a/src/soc/marvell/mvmap2315/mmu_operations.c b/src/soc/marvell/mvmap2315/mmu_operations.c new file mode 100644 index 0000000..105dd72 --- /dev/null +++ b/src/soc/marvell/mvmap2315/mmu_operations.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> +#include <memrange.h> +#include <arch/mmu.h> +#include <soc/addressmap.h> +#include <soc/mmu_operations.h> + +static void mvmap2315_mmu_config(void) +{ + const unsigned long ram_mem = MA_MEM | MA_NS | MA_RW; + const unsigned long dev_mem = MA_DEV | MA_S | MA_RW; + const unsigned long flash_mem = MA_MEM | MA_S | MA_RW; + + mmu_config_range((void *)MVMAP2315_RAM_BASE, (2UL * GiB), ram_mem); + + mmu_config_range((void *)(2UL * GiB), + MVMAP2315_DEVICE_SIZE, dev_mem); + + mmu_config_range((void *)MVMAP2315_FLASH_BASE, + MVMAP2315_FLASH_SIZE, flash_mem); +} + +void mvmap2315_mmu_init(void) +{ + mmu_init(); + + mvmap2315_mmu_config(); + + mmu_enable(); +} diff --git a/src/soc/marvell/mvmap2315/monotonic_timer.c b/src/soc/marvell/mvmap2315/monotonic_timer.c new file mode 100644 index 0000000..2316798 --- /dev/null +++ b/src/soc/marvell/mvmap2315/monotonic_timer.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/monotonic_timer.h> +#include <timer.h> + +void start_monotonic_timer(void) +{ + u32 reg; + + reg = read32(&mvmap2315_timer0->t1cr); + + /* disable timer */ + reg &= ~MVMAP2315_TIMER_T1CR_TE; + /* set to free-running mode (loads max value at timer expiration) */ + reg &= ~MVMAP2315_TIMER_T1CR_TM; + /* mask interrupt (not currently used) */ + reg |= MVMAP2315_TIMER_T1CR_TIM; + /* disable PWM output */ + reg &= ~MVMAP2315_TIMER_T1CR_TPWM; + + write32(&mvmap2315_timer0->t1cr, reg); + + /* perform dummy read to clear all active interrupts */ + reg = read32(&mvmap2315_timer0->t1eoi); + + /* must provide an initial load count even in free-running mode */ + reg = read32(&mvmap2315_timer0->t1lc); + reg = 0xFFFFFFFF; + write32(&mvmap2315_timer0->t1lc, reg); + + /* enable timer */ + reg = read32(&mvmap2315_timer0->t1cr); + reg |= MVMAP2315_TIMER_T1CR_TE; + write32(&mvmap2315_timer0->t1cr, reg); + + /* busy wait until timer count is non-zero */ + while (!read32(&mvmap2315_timer0->t1cv)) + ; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + u32 reg; + + /* invert count to change from down to up count */ + reg = ~read32(&mvmap2315_timer0->t1cv); + + mt->microseconds = (long)(reg / 13); +} diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c new file mode 100644 index 0000000..578fb51 --- /dev/null +++ b/src/soc/marvell/mvmap2315/power.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/power.h> + +void start_ap_cores(void *entry) +{ + /*TODO: start_ap_cores */ +} + +void no_boot(void) +{ + /*TODO: impelement no_boot */ +} + +void charging_screen(void) +{ + /*TODO: impelement charging_screen */ +} + +void full_boot(void) +{ + /*TODO: impelement full_boot */ +} + +u32 get_boot_path(void) +{ + return FULL_BOOT; +} diff --git a/src/soc/marvell/mvmap2315/ramstage.c b/src/soc/marvell/mvmap2315/ramstage.c new file mode 100644 index 0000000..bd830c8 --- /dev/null +++ b/src/soc/marvell/mvmap2315/ramstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stages.h> +#include <console/console.h> +#include <gic.h> +#include <soc/clock.h> +#include <soc/mmu_operations.h> +#include <soc/ramstage.h> + +void ramstage_entry(void) +{ + gic_init(); + + mvmap2315_mmu_init(); + + clock_init_arm_generic_timer(); + + /* Jump to boot state machine in common code. */ + main(); +} diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c new file mode 100644 index 0000000..8924d01 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <soc/assert.h> +#include <soc/clock.h> +#include <soc/monotonic_timer.h> +#include <soc/power.h> +#include <timestamp.h> + +/* + * main -- romstage main code. + * + */ +void main(void) +{ + u32 boot_path; + + configure_main_clk_pll(); + + timestamp_init(0); + + asm volatile ("bl cpu_enable_icache" : : : "r0", "r1"); + + asm volatile ("bl cpu_init" : : : "r0"); + + start_monotonic_timer(); + + timestamp_add_now(TS_START_ROMSTAGE); + + boot_path = get_boot_path(); + + switch (boot_path) { + case NO_BOOT: + no_boot(); + break; + + case CHARGING_SCREEN: + charging_screen(); + break; + + case FULL_BOOT: + full_boot(); + break; + } + + timestamp_add_now(TS_END_ROMSTAGE); + + run_ramstage(); +} + +static void romstage_continue(void) +{ + /* TODO: R4 Functionality to be added */ + while (1) + ; +} + +void platform_prog_run(struct prog *prog) +{ + if (!prog_entry(prog)) + __assert("ramstage entrypoint not found", __FILE__, __LINE__); + + start_ap_cores(prog_entry(prog)); + romstage_continue(); +} diff --git a/src/soc/marvell/mvmap2315/romstage_asm.S b/src/soc/marvell/mvmap2315/romstage_asm.S new file mode 100644 index 0000000..3fac9a5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/romstage_asm.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +# .balign 16 + +.arm +ENTRY(stage_entry) + blx _thumb_start +ENDPROC(stage_entry) + +.thumb +ENTRY(_thumb_start) + + ldr sp, =_estack + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + nop + + /* First arg: start of memory block */ + ldr a1, =_bss + + /* Second arg: fill value */ + mov a2, #0 + ldr a3, =_ebss + + /* Third arg: length of block */ + sub a3, a3, a1 + bl memset + + /* initializing FIQ stack */ + mrs r0, CPSR + mov r1, r0 + bic r1, r1, #0x40 + orr r0, r0, #0x51 + and r0, r0, #0xFFFFFFF1 + msr CPSR_c, r0 + ldr sp, =0xE001F700 + orr r0, r0, #0x10 + and r0, r0, #0xFFFFFFB0 + msr CPSR_cf, r1 + + /* call the code to authenticate this */ + bl main + /* should never return from this */ +ENDPROC(_thumb_start) diff --git a/src/soc/marvell/mvmap2315/soc.c b/src/soc/marvell/mvmap2315/soc.c new file mode 100644 index 0000000..a206e7b --- /dev/null +++ b/src/soc/marvell/mvmap2315/soc.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <device/device.h> + +static void soc_enable(device_t dev) +{ + /* Provide RAM resource for use by coreboot. Memory area needs to + * inclue load address for the payload. note that base and size are + * in Kbytes, so actual base and size are 0x10000000. + */ + + ram_resource(dev, 0, 0x0, CONFIG_RAMTOP / 1024); +} + +static struct device_operations soc_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = soc_enable, + .init = DEVICE_NOOP, + .scan_bus = NULL, +}; + +static void enable_mvmap2315_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_marvell_mvmap2315_ops = { + CHIP_NAME("SOC Marvell MVMAP2315") + .enable_dev = enable_mvmap2315_dev, +}; diff --git a/src/soc/marvell/mvmap2315/stage_entry.S b/src/soc/marvell/mvmap2315/stage_entry.S new file mode 100644 index 0000000..1bdf2d6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/stage_entry.S @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(stage_entry) + + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c new file mode 100644 index 0000000..a486ee4 --- /dev/null +++ b/src/soc/marvell/mvmap2315/uart.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <boot/coreboot_tables.h> + +void uart_init(int idx) +{ + /*TODO: implement uart_init */ +} + +void uart_tx_byte(int idx, unsigned char data) +{ + /*TODO: implement uart_tx_byte */ +} + +void uart_tx_flush(int idx) +{ + /*TODO: implement uart_tx_flush */ +} + +unsigned char uart_rx_byte(int idx) +{ + /*TODO: implement uart_rx_byte */ + return 0; +} + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + /*TODO: implement uart_fill_lb */ +} +#endif

1 0

Patch set updated for coreboot: arch: Add ARMv7-R configuration
by hakim giydan 05 Jul '16

05 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335 -gerrit commit 07be4d89f5a863b2449cb2a4678bd9a6d1d384b5 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Tue Jul 5 13:33:46 2016 -0700 arch: Add ARMv7-R configuration This change adds armv7-r configuration for romstage and verstage, and any other files needed to initialize an amrv7-r processor ARMv7-R is an ARM processor based on the Cortex-R series Currently, there is already support for the Cortex-M series, so the same files had been renamed and reused for Cortex-R series as well Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/arch/arm/armv7/Kconfig | 8 +++ src/arch/arm/armv7/Makefile.inc | 33 +++++++++-- src/arch/arm/armv7/bootblock_m.S | 50 ---------------- src/arch/arm/armv7/bootblock_m_r.S | 50 ++++++++++++++++ src/arch/arm/armv7/cache_m.c | 79 ------------------------- src/arch/arm/armv7/cache_m_r.c | 79 +++++++++++++++++++++++++ src/arch/arm/armv7/cpu_r.S | 116 +++++++++++++++++++++++++++++++++++++ src/arch/arm/armv7/exception_m.c | 36 ------------ src/arch/arm/armv7/exception_m_r.c | 36 ++++++++++++ util/xcompile/xcompile | 3 +- 10 files changed, 320 insertions(+), 170 deletions(-) diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 0ab3542..4fe3fd7 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M config ARCH_VERSTAGE_ARMV7_M def_bool n select ARCH_VERSTAGE_ARM + +config ARCH_VERSTAGE_ARMV7_R + def_bool n + select ARCH_VERSTAGE_ARM + +config ARCH_ROMSTAGE_ARMV7_R + def_bool n + select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2e9c49c..1b5ce93 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -3,6 +3,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2013 The ChromiumOS Authors +## Copyright (C) 2016 Marvell Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,9 +19,10 @@ armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 armv7-a_flags = -march=armv7-a $(armv7_flags) armv7-m_flags = -march=armv7-m $(armv7_flags) +armv7-r_flags = -march=armv7-r $(armv7_flags) armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated - +armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags) ############################################################################### # bootblock ############################################################################### @@ -44,10 +46,10 @@ bootblock-generic-ccopts += $(armv7-m_flags) bootblock-S-ccopts += $(armv7_asm_flags) ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) -bootblock-y += bootblock_m.S +bootblock-y += bootblock_m_r.S endif -bootblock-y += exception_m.c -bootblock-y += cache_m.c +bootblock-y += exception_m_r.c +bootblock-y += cache_m_r.c endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 @@ -73,6 +75,17 @@ libverstage-S-ccopts += $(armv7_asm_flags) verstage-generic-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y) +libverstage-generic-ccopts += $(armv7-r_flags) +libverstage-S-ccopts += $(armv7-r_asm_flags) +verstage-generic-ccopts += $(armv7-r_flags) +verstage-S-ccopts += $(armv7-r_asm_flags) + +verstage-y += cache_m_r.c +verstage-y += cpu_r.S +verstage-y += exception_m_r.c +verstage-y += mmu.c + endif # CONFIG_ARCH_VERSTAGE_ARMV7_M ################################################################################ @@ -91,6 +104,18 @@ romstage-S-ccopts += $(armv7_asm_flags) rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y) +romstage-y += cache_m_r.c +romstage-y += cpu_r.S +romstage-y += exception_m_r.c +romstage-y += mmu.c + +romstage-generic-ccopts += $(armv7-r_flags) +romstage-S-ccopts += $(armv7-r_asm_flags) + +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_ROMSTAGE_ARMV7 ############################################################################### diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S deleted file mode 100644 index 2e46ca0..0000000 --- a/src/arch/arm/armv7/bootblock_m.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <arch/asm.h> - -ENTRY(_start) - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr r0, =_stack - ldr r1, =_estack - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - -call_bootblock: - ldr sp, =_estack /* Set up stack pointer */ - bl main -ENDPROC(_start) diff --git a/src/arch/arm/armv7/bootblock_m_r.S b/src/arch/arm/armv7/bootblock_m_r.S new file mode 100644 index 0000000..2e46ca0 --- /dev/null +++ b/src/arch/arm/armv7/bootblock_m_r.S @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <arch/asm.h> + +ENTRY(_start) + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +call_bootblock: + ldr sp, =_estack /* Set up stack pointer */ + bl main +ENDPROC(_start) diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c deleted file mode 100644 index ec8a970..0000000 --- a/src/arch/arm/armv7/cache_m.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * cache.c: Cache maintenance routines for ARMv7-M - */ - -#include <stdint.h> - -#include <arch/cache.h> - -void tlb_invalidate_all(void) -{ -} - -void dcache_clean_all(void) -{ -} - -void dcache_clean_invalidate_all(void) -{ -} - -void dcache_invalidate_all(void) -{ -} - -unsigned int dcache_line_bytes(void) -{ - return 0; -} - -void dcache_clean_by_mva(void const *addr, size_t len) -{ -} - -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_mmu_disable(void) -{ -} - -void dcache_mmu_enable(void) -{ -} - -void cache_sync_instructions(void) -{ -} diff --git a/src/arch/arm/armv7/cache_m_r.c b/src/arch/arm/armv7/cache_m_r.c new file mode 100644 index 0000000..d584465 --- /dev/null +++ b/src/arch/arm/armv7/cache_m_r.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-M & ARMv7-R + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ +} + +void dcache_clean_all(void) +{ +} + +void dcache_clean_invalidate_all(void) +{ +} + +void dcache_invalidate_all(void) +{ +} + +unsigned int dcache_line_bytes(void) +{ + return 0; +} + +void dcache_clean_by_mva(void const *addr, size_t len) +{ +} + +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_mmu_disable(void) +{ +} + +void dcache_mmu_enable(void) +{ +} + +void cache_sync_instructions(void) +{ +} diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S new file mode 100644 index 0000000..5c53def --- /dev/null +++ b/src/arch/arm/armv7/cpu_r.S @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(cpu_disable_dcache) + + /* Read System Control Register configuration dat */ + mrc p15, 0, R0, c1, c0, 0 + + bic R0, R0, #0x1 <<2 + dsb + + /* disable data cache */ + mcr p15, 0, R0, c1, c0, 0 + + bx lr + +ENDPROC(cpu_disable_dcache) + +ENTRY(cpu_enable_dcache) + + /* Read System Control Register configuration data */ + mcr p15, 0, R1, c1, c0, 0 + + orr R1, R1, #0x1 <<2 + mov R0, #0 + dsb + + /* Invalidate entire data cache */ + mcr p15, 0, r0, c15, c5, 0 + + /* enabled data cache */ + mcr p15, 0, R1, c1, c0, 0 + + bx lr + +ENDPROC(cpu_enable_dcache) + +ENTRY(cpu_disable_icache) + + /* Read System Control Register configuration data */ + mcr p15, 0, R0, c1, c0, 0 + + /* enable instruction cache */ + bic R0, R0, #0x1 <<12 + + /* disable instruction cache */ + mcr p15, 0, R0, c1, c0, 0 + + isb + + bx lr + +ENDPROC(cpu_disable_icache) + +ENTRY(cpu_enable_icache) + + /* Read System Control Register configuration data */ + mrc p15, 0, R1, c1, c0, 0 + + /* enable instruction cache */ + orr R1, R1, #0x1 <<12 + + mov R0, #0 + + /* Invalidate entire instruction cache */ + mcr p15, 0, r0, c7, c5, 0 + + /* enable instruction cache */ + mcr p15, 0, R1, c1, c0, 0 + + isb + + bx lr + +ENDPROC(cpu_enable_icache) + +ENTRY(cpu_init) + + mrc p15,0,r0,c9,c14,0 + mov r0, $1 + mcr p15,0,r0,c9,c14,0 + + /* read performance monitor control register into R0 */ + mrc p15, 0, r0, c9, c12, 0 + + /* set the enable-bit for the performance counters and cycle counter */ + orr r0, r0, #1 + + /* write the perfomance monitor control register back */ + mcr p15, 0, r0, c9, c12, 0 + + /* load the bit-mask into r0 */ + mov r0, #0x80000000 + + /* write the bit-mask to the enable set register + * and enable cycle counter bit + */ + mcr p15, 0, r0, c9, c12, 1 + + bx lr + +ENDPROC(cpu_init) diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c deleted file mode 100644 index d76cc6a..0000000 --- a/src/arch/arm/armv7/exception_m.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/exception.h> -#include <console/console.h> - -void exception_init(void) -{ - printk(BIOS_DEBUG, "Exception handlers not installed.\n"); -} diff --git a/src/arch/arm/armv7/exception_m_r.c b/src/arch/arm/armv7/exception_m_r.c new file mode 100644 index 0000000..d76cc6a --- /dev/null +++ b/src/arch/arm/armv7/exception_m_r.c @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <console/console.h> + +void exception_init(void) +{ + printk(BIOS_DEBUG, "Exception handlers not installed.\n"); +} diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 13a0e8f..c030545 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -5,6 +5,7 @@ # Copyright (C) 2007-2010 coresystems GmbH # Copyright (C) 2012 Google Inc # Copyright (C) 2016 Raptor Engineering, LLC +# Copyright (C) 2016 Marvell Inc # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -316,7 +317,7 @@ arch_config_arm() { TBFDARCHS="littlearm" TCLIST="armv7-a armv7a arm" TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" + TSUPP="arm armv4 armv7 armv7_m armv7_r" TABI="eabi" }

1 0

Patch set updated for coreboot: pcengines/apu2: Add IVRS table generation
by Philipp Deppenwiese 05 Jul '16

05 Jul '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15165 -gerrit commit 01e195dd0a603c77fa5ffa03fe63168e5667b42b Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:49:36 2016 -0500 pcengines/apu2: Add IVRS table generation The resultant IVRS tables have been tested and work with PCI passthrough under Xen. Change-Id: I81b5b421098f29163d6ae98527de152c8046b1d9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/pcengines/apu2/acpi_tables.c | 35 +++++++++++++++++++++++++++--- src/mainboard/pcengines/apu2/devicetree.cb | 2 +- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 17995ce..c3e24c9 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,9 +58,37 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) { - /* TODO - * Add IVRS entries - */ + uint8_t *p; + + uint32_t apicid_sb800; + uint32_t apicid_northbridge; + + apicid_sb800 = CONFIG_MAX_CPUS; + apicid_northbridge = CONFIG_MAX_CPUS + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_northbridge; /* IOAPIC ID */ + p[5] = 0x0; /* Device 0 Function 0 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sb800; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; return current; } diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..f402167 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU + device pci 0.2 on end # IOMMU device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge

1 0

Patch set updated for coreboot: nb/amd/pi/00730F01: Add initial native IVRS support
by Philipp Deppenwiese 05 Jul '16

05 Jul '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15164 -gerrit commit d1f414137b19558edc2ea640808c7d1d98938732 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:48:58 2016 -0500 nb/amd/pi/00730F01: Add initial native IVRS support Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/amd/olivehillplus/acpi_tables.c | 9 ++ src/mainboard/pcengines/apu2/acpi_tables.c | 9 ++ src/northbridge/amd/pi/00730F01/northbridge.c | 208 ++++++++++++++++++++++++-- 3 files changed, 214 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c index d5ebad4..a1a5a6b 100644 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ b/src/mainboard/amd/olivehillplus/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9b1c1b1..44b1501 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -478,6 +479,193 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } +static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) +{ + uint8_t *p; + struct device *sibling; + struct bus *link; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if (*root_level != -1) { + if (depth >= *root_level) { + if (dev->enabled) { + if (depth == *root_level) { + if (dev->path.pci.devfn == 0x2) { + /* IOMMU */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else if (dev->path.pci.devfn < (0x2 << 3)) { + /* FCH control device */ + } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) { + /* FCH PCIe bridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + if (dev->path.pci.devfn == (0x14 << 3)) { + /* SMBUS controller */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x97; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Other southbridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } else { + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { + /* Device behind bridge */ + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Device is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Device is legacy PCI or PCI-X */ + p = (uint8_t *) *current; + p[0] = 0x42; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Reserved */ + p[5] = parent->path.pci.devfn; /* Device */ + p[6] = parent->bus->secondary; /* Bus */ + p[7] = 0x0; /* Reserved */ + *length += 8; + *current += 8; + } + } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Bridge is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } + } + } + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = sibling->sibling) + add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); + + free(root_level); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n"); + return (unsigned long)ivrs; + } + + ivrs->iv_info = 0x0; + ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ + ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */ + ivrs->iv_info |= (0x2 << 5); /* Guest virtual address width */ + + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = 0xfeb00000; + ivrs->ivhd.iommu_base_high = 0x0; + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x13 << 8); + ivrs->ivhd.efr = 0x0; + + /* Describe HPET */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = 0x0; /* HPET number */ + p[5] = 0x14 << 3; /* HPET device */ + p[6] = nb_dev->bus->secondary; /* HPET bus */ + p[7] = 0x2; /* Variety */ + ivrs->ivhd.length += 8; + current += 8; + + /* Describe PCI devices */ + add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + + /* Describe IOAPICs */ + unsigned long prev_current = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - prev_current); + + return current; +} + static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; @@ -507,7 +695,7 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_slit_t *slit; acpi_header_t *ssdt; acpi_header_t *alib; - acpi_header_t *ivrs; + acpi_ivrs_t *ivrs; acpi_hest_t *hest; /* HEST */ @@ -517,17 +705,13 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } + /* IVRS */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); /* SRAT */ current = ALIGN(current, 8);

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coreboot-gerrit July 2016