coreboot-gerrit March 2016

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Patch set updated for coreboot: soc/intel/apollolake: Add support for memory-mapped boot media
by Andrey Petrov 07 Mar '16

07 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13706 -gerrit commit b3aef6d823f487d20e9597dec82181eee1386a11 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 12 15:12:43 2016 -0800 soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 9 ++++ src/soc/intel/apollolake/Kconfig | 3 ++ src/soc/intel/apollolake/Makefile.inc | 3 ++ src/soc/intel/apollolake/mmap_boot.c | 74 ++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 52d3777..9920b46 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,4 +17,13 @@ config MAINBOARD_VENDOR string default "Intel" +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + + endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c32b80f..8487414 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,4 +85,7 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 76fa4c7..e27fd27 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,6 +11,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c +bootblock-y += mmap_boot.c bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c @@ -18,11 +19,13 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += placeholders.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ramstage-y += mmap_boot.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c new file mode 100644 index 0000000..3625924 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> + +/* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */ +#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB) +#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START) +#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START) + +/* + * If Apollo Lake is configured to boot from SPI flash "BIOS" region + * (as defined in descriptor) is mapped below 4GiB. Form a pointer for + * the base. + */ +#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE)) + +static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT( + VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED +); + +/* + * This is how we translate physical SPI flash address space into CPU memory-mapped space. In + * essence this means "BIOS" region (usually starts at flash physical 0x1000 is mapped to + * 4G - IFD_BIOS_SIZE. + */ +static const struct xlate_region_device real_dev = XLATE_REGION_INIT( + &shadow_dev.rdev, CONFIG_IFD_BIOS_START, + IFD_MAPPED_SIZE, CONFIG_ROM_SIZE +); + +const struct region_device *boot_device_ro(void) +{ + return &real_dev.rdev; +} + +static int iafw_boot_region_properties(struct cbfs_props *props) +{ + struct region regn; + + /* use fmap to locate CBFS area */ + if (fmap_locate_area("COREBOOT", &regn)) + return -1; + + props->offset = region_offset(&regn); + props->size = region_sz(&regn); + + printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} + +/* + * Named cbfs_master_header_locator so that it overrides the default, but + * incompatible locator in cbfs.c + */ +const struct cbfs_locator cbfs_master_header_locator = { + .name = "IAFW Locator", + .locate = iafw_boot_region_properties, +};

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Patch set updated for coreboot: northbridge/intel/i440bx: Unify UDELAY selection
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13781 -gerrit commit 06bffdb299ba5d6fac1bcd5134f3a0d438444e21 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 11:01:54 2016 -0800 northbridge/intel/i440bx: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/intel/socket_PGA370/Kconfig | 1 - src/drivers/pc80/Makefile.inc | 1 + src/mainboard/a-trend/atc-6220/Kconfig | 1 - src/mainboard/a-trend/atc-6220/romstage.c | 1 - src/mainboard/a-trend/atc-6240/Kconfig | 1 - src/mainboard/a-trend/atc-6240/romstage.c | 1 - src/mainboard/abit/be6-ii_v2_0/Kconfig | 1 - src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/asus/p2b-d/Kconfig | 1 - src/mainboard/asus/p2b-d/romstage.c | 1 - src/mainboard/asus/p2b-ds/Kconfig | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-f/Kconfig | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/asus/p2b-ls/Kconfig | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/Kconfig | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/Kconfig | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/azza/pt-6ibd/Kconfig | 1 - src/mainboard/azza/pt-6ibd/romstage.c | 1 - src/mainboard/biostar/m6tba/Kconfig | 1 - src/mainboard/biostar/m6tba/romstage.c | 1 - src/mainboard/compaq/deskpro_en_sff_p600/Kconfig | 1 - src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 1 - src/mainboard/emulation/qemu-i440fx/romstage.c | 1 - src/mainboard/emulation/qemu-q35/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxc/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxc/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxe/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxe/romstage.c | 1 - src/mainboard/lanner/em8510/romstage.c | 1 - src/mainboard/msi/ms6119/Kconfig | 2 +- src/mainboard/msi/ms6119/romstage.c | 1 - src/mainboard/msi/ms6147/Kconfig | 1 - src/mainboard/msi/ms6147/romstage.c | 1 - src/mainboard/msi/ms6156/Kconfig | 1 - src/mainboard/msi/ms6156/romstage.c | 1 - src/mainboard/msi/ms6178/romstage.c | 1 - src/mainboard/nokia/ip530/Kconfig | 1 - src/mainboard/nokia/ip530/romstage.c | 1 - src/mainboard/soyo/sy-6ba-plus-iii/Kconfig | 1 - src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 - src/mainboard/tyan/s1846/Kconfig | 1 - src/mainboard/tyan/s1846/romstage.c | 1 - src/northbridge/intel/i440bx/Kconfig | 1 + 47 files changed, 3 insertions(+), 45 deletions(-) diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 9e7bdae..b23308c 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -17,7 +17,6 @@ config CPU_INTEL_SOCKET_PGA370 bool select CPU_INTEL_MODEL_6XX select MMX - select UDELAY_TSC if CPU_INTEL_SOCKET_PGA370 diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 0788cc7..f468318 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -5,6 +5,7 @@ ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c +romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/mainboard/a-trend/atc-6220/Kconfig b/src/mainboard/a-trend/atc-6220/Kconfig index 4f1966b..626f743 100644 --- a/src/mainboard/a-trend/atc-6220/Kconfig +++ b/src/mainboard/a-trend/atc-6220/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 35ee9bf..f075b4e 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig index 6051b76..5d0d4f6 100644 --- a/src/mainboard/a-trend/atc-6240/Kconfig +++ b/src/mainboard/a-trend/atc-6240/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 1de647e..8c73824 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig index b5eaff6..acb5f3a 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Kconfig +++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 08c4b4d..e38d846 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index 7a13a45..ba2e7e0 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SMP select IOAPIC - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index c83ca6d..b46646d 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 53e4bdb..7d69d1f 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SMP select IOAPIC - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 65f8cea..4464f29 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig index 2c78ba7..b702c1b 100644 --- a/src/mainboard/asus/p2b-f/Kconfig +++ b/src/mainboard/asus/p2b-f/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index aa350f0..521ddbd 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index 9045f61..967ebd9 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index e5f66e9..5808bb8 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 46bff7c..6b934a5 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 35ee9bf..f075b4e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig index e6fab97..212aa93 100644 --- a/src/mainboard/asus/p3b-f/Kconfig +++ b/src/mainboard/asus/p3b-f/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 7a4108d..89e3795 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/azza/pt-6ibd/Kconfig b/src/mainboard/azza/pt-6ibd/Kconfig index 24809cc..67c9fa4 100644 --- a/src/mainboard/azza/pt-6ibd/Kconfig +++ b/src/mainboard/azza/pt-6ibd/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index eeb8a8c..8ed2fb1 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/biostar/m6tba/Kconfig b/src/mainboard/biostar/m6tba/Kconfig index 66e270c..6cb07e2 100644 --- a/src/mainboard/biostar/m6tba/Kconfig +++ b/src/mainboard/biostar/m6tba/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index d2900c1..eb7ef25 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig index 61fbb7d..bdb2157 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # should be SUPERIO_NSC_PC97307! select SUPERIO_NSC_PC97317 select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 89578b3..bf12a34 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index f16f8dd..d03c8ab 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index d54d8b0..fb0bccf 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -23,7 +23,6 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/gigabyte/ga-6bxc/Kconfig b/src/mainboard/gigabyte/ga-6bxc/Kconfig index 239e704..7e57819 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxc/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 8c36f6f..4128d30 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig index 4e12b93..b225ed0 100644 --- a/src/mainboard/gigabyte/ga-6bxe/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 58360c6..fac7416 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 76d9b94..0a8c4d7 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -23,7 +23,6 @@ #include <stdlib.h> #include <lib.h> #include <spd.h> -#include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801dx/i82801dx.h> diff --git a/src/mainboard/msi/ms6119/Kconfig b/src/mainboard/msi/ms6119/Kconfig index 0a25e80..efd5757 100644 --- a/src/mainboard/msi/ms6119/Kconfig +++ b/src/mainboard/msi/ms6119/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC +#select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 3031149..55e2eee 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6147/Kconfig b/src/mainboard/msi/ms6147/Kconfig index 6697c50..814855b 100644 --- a/src/mainboard/msi/ms6147/Kconfig +++ b/src/mainboard/msi/ms6147/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 53e14b3..00ad38c 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6156/Kconfig b/src/mainboard/msi/ms6156/Kconfig index e48505d..892d45c 100644 --- a/src/mainboard/msi/ms6156/Kconfig +++ b/src/mainboard/msi/ms6156/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 0a289d3..4ad2c50 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index d83bc02..aaad2ea 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index d5bc669..8d86257 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select PIRQ_ROUTE select HAVE_PIRQ_TABLE - select UDELAY_TSC select SDRAMPWR_4DIMM config MAINBOARD_DIR diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 9d9b680..42a5ac2 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig index d09a6ea..1b5931a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 9a8f0f8..1e25602 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/tyan/s1846/Kconfig b/src/mainboard/tyan/s1846/Kconfig index 9d2ad1e..2d6eeb7 100644 --- a/src/mainboard/tyan/s1846/Kconfig +++ b/src/mainboard/tyan/s1846/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 2783dbe..5cdc56d 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 828c693..3f574a4 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT + select UDELAY_IO config SDRAMPWR_4DIMM bool

1 0

New patch to review for coreboot: crossgcc: Build make per default
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13923 -gerrit commit 44c664fabd80ec9f3d544dbbacb5b28b49b7ef6d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 6 02:18:47 2016 -0800 crossgcc: Build make per default Build make with the rest of the toolchain, since the targets using a Chromium EC need make 4.x Change-Id: I7efb0c25f605f16c2d9a1e7c4b203f3bcdae671b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 0831f18..917301c 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -10,12 +10,12 @@ DEST ?= $(CURDIR)/xgcc all all_with_gdb: $(MAKE) build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-power8 build-nds32le \ - build_clang build_iasl + build_clang build_iasl build_make all_without_gdb: $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-power8 build-nds32le \ - build_clang build_iasl + build_clang build_iasl build_make build_tools: build_gcc build_gdb @@ -40,6 +40,9 @@ ifeq ($(SKIP_CLANG),) bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) endif +build_make: + bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) + ########################################################### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf

1 0

Patch set updated for coreboot: mainboard/lanner/em8150: Remove unneeded udelay_io.c include
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13787 -gerrit commit a6c0a80d5284440527330519fbece3a0ab6f8046 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 14:05:30 2016 -0800 mainboard/lanner/em8150: Remove unneeded udelay_io.c include Change-Id: I8001e2ab020a132fce4351ce08cc078e385ca686 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

1 0

Patch set updated for coreboot: northbridge/intel/i3100: Unify UDELAY selection
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13786 -gerrit commit 79bb4d2ea426c359a10739a8ca8be3115f979e01 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 14:01:59 2016 -0800 northbridge/intel/i3100: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/intel/truxton/Kconfig | 1 - src/mainboard/intel/truxton/romstage.c | 1 - src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i3100/raminit_ep80579.c | 1 + 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig index 11058e6..cd8e478 100644 --- a/src/mainboard/intel/truxton/Kconfig +++ b/src/mainboard/intel/truxton/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_2048 config MAINBOARD_DIR diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index c637d24..3ea6542 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -21,7 +21,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "drivers/pc80/udelay_io.c" #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index cb0bd38..2260664 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I3100 bool select LATE_CBMEM_INIT + select UDELAY_IO if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 7996e11..497339c 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -19,6 +19,7 @@ #include <cpu/x86/cache.h> #include <cpu/intel/speedstep.h> #include <lib.h> +#include <delay.h> #include "raminit_ep80579.h" #include "ep80579.h"

1 0

Patch set updated for coreboot: mainboard/emulation/qemu-q35: remove unneeded udelay include
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13785 -gerrit commit b2230a7e14ea161abee57877216127f588a5a3d6 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 14:00:24 2016 -0800 mainboard/emulation/qemu-q35: remove unneeded udelay include Change-Id: Ibf3671f4e876d97da9b1ca47507c21893f4d5e54 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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Patch set updated for coreboot: northbridge/intel/i82810: Unify UDELAY selection
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13784 -gerrit commit 9ec05268e37f4b9b9590f072e4374ec455a70885 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 13:33:45 2016 -0800 northbridge/intel/i82810: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/romstage.c | 1 - src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/romstage.c | 1 - src/mainboard/intel/d810e2cb/Kconfig | 1 - src/mainboard/intel/d810e2cb/romstage.c | 1 - src/mainboard/mitac/6513wu/Kconfig | 1 - src/mainboard/mitac/6513wu/romstage.c | 1 - src/mainboard/msi/ms6178/romstage.c | 1 - src/mainboard/nec/powermate2000/Kconfig | 1 - src/mainboard/nec/powermate2000/romstage.c | 1 - src/northbridge/intel/i82810/Kconfig | 1 + 12 files changed, 1 insertion(+), 11 deletions(-) diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 9098362..9afae9a 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 73176e8..3e8a084 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index b3ba155..28594f0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 58dd5e7..a04542f 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> /* TODO: It's a PC87364 actually! */ diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 55a6bc6..8695da9 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select USE_WATCHDOG_ON_BOOT - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 2f31a0d..934cb17 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82801bx/i82801bx.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index e54ca33..0266016 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 4af2216..2d99aca 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index d83bc02..aaad2ea 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 60135e7..fe546fa 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 0bed855..037ad04 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 72f94d6..428505c 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_I82810 bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT + select UDELAY_IO choice prompt "Onboard graphics"

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Patch set updated for coreboot: northbridge/intel/i82830: Unify UDELAY selection
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13783 -gerrit commit 3e846367a33834308487ea3ec2b202f92ec55ac8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 13:25:42 2016 -0800 northbridge/intel/i82830: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/rca/rm4100/romstage.c | 1 - src/mainboard/thomson/ip1000/Kconfig | 1 - src/mainboard/thomson/ip1000/romstage.c | 1 - src/northbridge/intel/i82830/Kconfig | 1 + 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index a6f216e..81cfc7b 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index bec4be8..296d072 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include "drivers/pc80/udelay_io.c" #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index f775e2b..1c21ace 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select INTEL_INT15 diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 2c69791..5bb7718 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include "drivers/pc80/udelay_io.c" #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 25a9e97..344dfed 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_INTEL_I82830 bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT + select UDELAY_IO choice prompt "Onboard graphics"

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Patch set updated for coreboot: VIA: Don't manually include udelay_io.c
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13782 -gerrit commit 513e5f3b818aa665b737081102d42bae2884cf5d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 11:08:53 2016 -0800 VIA: Don't manually include udelay_io.c UDELAY_IO is already selected by CPU_VIA_C7, so no manual inclusion (or secondary UDELAY implementation) is needed Change-Id: Ib086a1bfe8ffca5757bf553c5a62a45da7a410b6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/bcom/winnetp680/Kconfig | 1 - src/mainboard/bcom/winnetp680/romstage.c | 1 - src/mainboard/via/epia-cn/romstage.c | 1 - src/mainboard/via/epia-m700/romstage.c | 1 - src/mainboard/via/pc2500e/Kconfig | 1 - src/mainboard/via/pc2500e/romstage.c | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig index f6a80af..c328c3f 100644 --- a/src/mainboard/bcom/winnetp680/Kconfig +++ b/src/mainboard/bcom/winnetp680/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 179148a..40c87b6 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <lib.h> #include <spd.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 7ec9dfb..b71fe1c 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -24,7 +24,6 @@ #include <lib.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8237r/early_serial.c" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index e30441b..6878623 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -30,7 +30,6 @@ #include <lib.h> #include <northbridge/via/vx800/vx800.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <string.h> /* This file contains the board-special SI value for raminit.c. */ diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index 97f2088..d5e1133 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 2bf525a..17efa38 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -24,7 +24,6 @@ #include <lib.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/ite/common/ite.h>

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New patch to review for coreboot: northbridge/intel/gm45: Use TSC for ramstage timer per default
by Stefan Reinauer 06 Mar '16

06 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13922 -gerrit commit 8fb3d9c0493193e5ba5a41d66a95f361fdb47aae Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 6 01:49:27 2016 -0800 northbridge/intel/gm45: Use TSC for ramstage timer per default This is a step towards isolating the timer drivers. Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/northbridge/intel/gm45/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 6ee6558..d254b9e 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI + select UDELAY_TSC config CBFS_SIZE hex

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coreboot-gerrit March 2016