coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

Patch merged into coreboot/master: Skylake: Support Intel Speed Shift Technology based on config
by gerrit＠coreboot.org 01 Mar '16

01 Mar '16

the following patch was just integrated into master: commit b7e69a2e561d557a7d243a15d91a5cede56e5eb8 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:15:29 2016 +0530 Skylake: Support Intel Speed Shift Technology based on config Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: https://review.coreboot.org/13835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13835 for details. -gerrit

1 0

Patch merged into coreboot/master: Skylake boards: Enabling HWP (hardware P state control)
by gerrit＠coreboot.org 01 Mar '16

01 Mar '16

the following patch was just integrated into master: commit 2a696c07b9cdcd484800596fb850f95260419d11 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:19:10 2016 +0530 Skylake boards: Enabling HWP (hardware P state control) This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13843 for details. -gerrit

1 0

Patch set updated for coreboot: Skylake boards: Enabling HWP (hardware P state control)
by Patrick Georgi 01 Mar '16

01 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13843 -gerrit commit 51c949dba3b8301171113c043008834417b357e4 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:19:10 2016 +0530 Skylake boards: Enabling HWP (hardware P state control) This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 3 +++ src/mainboard/google/glados/devicetree.cb | 3 +++ src/mainboard/google/lars/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ 4 files changed, 12 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ac3a5c1..bb925ce 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 894f0e1..89fcff8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index cf3649a..50b3e1e 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index d2a70c8..62a0c26 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1"

1 0

Patch merged into coreboot/master: Makefile.inc: Add dependency on util/kconfig/conf for config.h
by gerrit＠coreboot.org 01 Mar '16

01 Mar '16

the following patch was just integrated into master: commit f4b7f2258405389be43ae0690914df67b83ae163 Author: Martin Roth <martinroth(a)google.com> Date: Sun Feb 28 21:04:15 2016 -0700 Makefile.inc: Add dependency on util/kconfig/conf for config.h This dependency wasn't called out before, and when building with enough threads, the build would fail due to a collision trying to build build/util/kconfig/conf. Fixes this failure: make[1]: execvp: build/util/kconfig/conf: Permission denied /home/martin/git/coreboot/util/kconfig/Makefile:40: recipe for target 'oldconfig' failed make[1]: *** [oldconfig] Error 127 Makefile:167: recipe for target 'build/config.h' failed Change-Id: Ib78d36bab0ba469796d89877bbe6a61e05196e87 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13859 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13859 for details. -gerrit

1 0

Patch set updated for coreboot: toolchain.inc: test IASL by version string instead of number
by Martin Roth 01 Mar '16

01 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12847 -gerrit commit ca42e61018f433fd1b8094c4afd01ba6c8b55a04 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 5 16:14:12 2016 -0700 toolchain.inc: test IASL by version string instead of number Test that the coreboot toolchain version of IASL is being used by looking for the string 'coreboot toolchain' instead of a specific version number. While this may cause people to have to rebuild their toolchains again now, it helps to prevent toolchain failures when bisecting in the future. Change-Id: I9913eeae8f29ddc3ec8c70077c05d898595eb283 Signed-off-by: Martin Roth <martinroth(a)google.com> --- toolchain.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index 2289b78..c891193 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -174,7 +174,7 @@ $(foreach arch,$(sort $(foreach stage,\ # If iasl doesn't match the current coreboot version, fail the test # TODO: Figure out if iasl is even needed for the build. $(if $(shell if [ -n "$(IASL)" ]; then \ - $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || \ + $(IASL) -v 2>&1 | grep -q "coreboot toolchain" || \ echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)\ $(warning The coreboot toolchain version of iasl \

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add romstage that calls FSP2.0 driver
by Andrey Petrov 01 Mar '16

01 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13805 -gerrit commit 46ba9d73defe6e8cdf868784b9f102517f0f0855 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:42:25 2016 -0800 soc/intel/apollolake: Add romstage that calls FSP2.0 driver This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 7 + src/soc/intel/apollolake/Makefile.inc | 2 + src/soc/intel/apollolake/include/fsp/FspUpd.h | 37 ++ src/soc/intel/apollolake/include/fsp/FspmUpd.h | 568 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/fsp/FspsUpd.h | 565 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/iomap.h | 27 ++ src/soc/intel/apollolake/include/soc/romstage.h | 22 + src/soc/intel/apollolake/romstage.c | 158 +++++++ 8 files changed, 1386 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 401535f..2ff93c9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -83,4 +83,11 @@ config C_ENV_BOOTBLOCK_SIZE config X86_TOP4G_BOOTMEDIA_MAP bool default n + +config ROMSTAGE_ADDR + hex + default 0xfef2e000 + help + The base address (in CAR) where romstage should be linked + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 17ddaec..cad2a2c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -16,7 +16,9 @@ bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-y += uart_early.c +cpu_incs-$(CONFIG_PLATFORM_USES_FSP2_0) += $(src)/arch/x86/carstage_entry.S romstage-y += placeholders.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-y += mmap_boot.c romstage-y += uart_early.c diff --git a/src/soc/intel/apollolake/include/fsp/FspUpd.h b/src/soc/intel/apollolake/include/fsp/FspUpd.h new file mode 100644 index 0000000..da3486d --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspUpd.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +/** FSP UPD Header +**/ +struct FSP_UPD_HEADER { + +/** Offset 0x00 to 0x07 - UPD Region Signature + The signature will be + "FSPT_UPD" for FSP-T + "FSPM_UPD" for FSP-M + "FSPS_UPD" for FSP-S +**/ + uint64_t Signature; + +/** Offset 0x08 - Revision +**/ + uint8_t Revision; + +/** Offset 0x09 to 0x1F - ReservedUpd +**/ + uint8_t ReservedUpd[23]; +} __attribute__((packed)); + +#endif /* _FSP_API_H_ */ diff --git a/src/soc/intel/apollolake/include/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/fsp/FspmUpd.h new file mode 100644 index 0000000..e55b42b --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspmUpd.h @@ -0,0 +1,568 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include "FspUpd.h" + + +typedef union { + uint32_t PadCnf0; + struct { + uint32_t GPIOTxState:1; ///< 0 GPIO TX State + uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO + uint32_t Reserved1:6; ///< 2-7 Reserved, RO + uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] + uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. + uint32_t Reserved2:4; ///< 13-16 Reserved, RO + uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] + uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO + uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion + uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT + uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge + uint32_t Reserved3:1; ///< 27 RO + uint32_t RXRAW1:1; ///< 28 Override the RX to 1 + uint32_t RXPadStSel:1; ///< 29 RX Pad State Select + uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config + } r; +} BL_CONF_PAD0; + +typedef union { + uint32_t PadCnf1; + struct { + uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO + uint32_t Reserved:1; ///< 7 Reserved. + uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW + uint32_t Term:4; ///< 10-13 Termination, + ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; + ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination + uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW + uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO + } r; +} BL_CONF_PAD1; + +struct BL_GPIO_PAD_INIT { + BL_CONF_PAD0 PadConfg0; + BL_CONF_PAD1 PadConfg1; + uint8_t Community; + uint16_t MmioAddress; + bool HostSw; + bool WakeEnabled; + wchar_t *PadName; +} __attribute__((packed)); + +/** Fsp M Architectural UPD +**/ +struct FSP_M_ARCH_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + void* NvsBufferPtr; + +/** Offset 0x0028 - StackBase + To hold the stack base. +**/ + void* StackBase; + +/** Offset 0x002C - StackSize + To hold the stack size. +**/ + uint32_t StackSize; + +/** Offset 0x0030 - BootLoaderTolumSize + To pass Bootloader Tolum size. +**/ + uint32_t BootLoaderTolumSize; + +/** Offset 0x0034 - Bootmode + To maintain Bootmode details. +**/ + uint32_t Bootmode; + +/** Offset 0x0038 +**/ + uint8_t ReservedFspmArchUpd[8]; +} __attribute__((packed)); + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - Debug Serial Port Base + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. +**/ + uint32_t SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0:NONE, 1:I/O, 2:MMIO +**/ + uint8_t SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + uint8_t SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. + 0:1, 2:4 +**/ + uint8_t SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. + $EN_DIS +**/ + uint8_t MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. + $EN_DIS +**/ + uint8_t Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB +**/ + uint8_t IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + uint8_t IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + uint8_t GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + uint8_t PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. + 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD +**/ + uint8_t Package; + +/** Offset 0x004E - Profile + Profile list + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + uint8_t Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + uint8_t MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. + 0x1:1KB, 0x2:2KB +**/ + uint8_t DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. + 0x0:Not Supported, 0x1:Supported +**/ + uint8_t DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support. + $EN_DIS +**/ + uint8_t ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + Channel Hash Mask. +**/ + uint16_t ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + Slice Hash Mask. +**/ + uint16_t SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + Interleaved Mode. + $EN_DIS +**/ + uint8_t InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + Channels Slices Enable. + $EN_DIS +**/ + uint8_t ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. + $EN_DIS +**/ + uint8_t MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. + $EN_DIS +**/ + uint8_t DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. + $EN_DIS +**/ + uint8_t RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. + $EN_DIS +**/ + uint8_t DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\n Boolean value. +**/ + uint8_t Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + [0] 2N Mode.\n Boolean value. +**/ + uint8_t Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint16_t RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint32_t MsgLevelMask; + +/** Offset 0x010C - FIT Table Pointer + FIT table pointer. +**/ + uint32_t FitTablePtr; + +/** Offset 0x0110 - GPIO Table Pointer + GPIO table pointer to a BL_GPIO_PAD_INIT structure. +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; + +/** Offset 0x0114 +**/ + uint8_t ReservedFspmUpd[60]; +} __attribute__((packed)); + +/** Fsp M Test Configuration +**/ +struct FSP_M_TEST_CONFIG { + +/** Offset 0x0150 +**/ + uint32_t Signature; + +/** Offset 0x0154 +**/ + uint8_t ReservedFspmTestUpd[28]; +} __attribute__((packed)); + +/** Fsp M Restricted Configuration +**/ +struct FSP_M_RESTRICTED_CONFIG { + +/** Offset 0x0170 +**/ + uint32_t Signature; + +/** Offset 0x0174 +**/ + uint8_t ReservedFspmRestrictedUpd[138]; +} __attribute__((packed)); + +#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ + +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_M_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; + +/** Offset 0x0150 +**/ + struct FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0170 +**/ + struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x01FE +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/fsp/FspsUpd.h new file mode 100644 index 0000000..f2f867b --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspsUpd.h @@ -0,0 +1,565 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include "FspUpd.h" + + +/** Fsp S Configuration +**/ +struct FSP_S_CONFIG { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. +**/ + uint8_t ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. + $EN_DIS +**/ + uint8_t DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. + $EN_DIS +**/ + uint8_t DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. + $EN_DIS +**/ + uint8_t DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. + $EN_DIS +**/ + uint8_t VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable. +**/ + uint8_t ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. + $EN_DIS +**/ + uint8_t ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. + $EN_DIS +**/ + uint8_t Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0: HFM; 1: LFM. +**/ + uint8_t BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. +**/ + uint8_t PkgCStateLimit; + +/** Offset 0x002D +**/ + uint8_t UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. +**/ + uint8_t CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. +**/ + uint8_t CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. +**/ + uint8_t MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t TurboMode; + +/** Offset 0x0034 +**/ + uint8_t UnusedUpdSpace1[12]; + +/** Offset 0x0040 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + uint8_t HdAudioIoBufferOwnership; + +/** Offset 0x0041 +**/ + uint8_t UnusedUpdSpace2[5]; + +/** Offset 0x0046 - Enable SD controller + Enable/disable SD Card controller. + $EN_DIS +**/ + uint8_t SdcardEnabled; + +/** Offset 0x0047 - Enable SDIO controller + Enable/disable SDIO controller. + $EN_DIS +**/ + uint8_t SdioEnabled; + +/** Offset 0x0048 - Enable eMMC controller + Enable/disable eMMC controller. + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x0049 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + uint8_t EnableSata; + +/** Offset 0x004A - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x004B - Aggressive SATA LPM Support + Enable SOC to aggressively enter link power state for SATA. + $EN_DIS +**/ + uint8_t SataSalpSupport; + +/** Offset 0x004C - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x004E - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x0050 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRootPortEn[6]; + +/** Offset 0x0056 - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x005C +**/ + uint8_t UnusedUpdSpace3[16]; + +/** Offset 0x006C - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb20Enable[8]; + +/** Offset 0x0074 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x007A - Enable XHCI SSIC ports + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x007C - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + uint8_t SmbusEnable; + +/** Offset 0x007D - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x007E - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0082 +**/ + uint8_t UnusedUpdSpace4[14]; + +/** Offset 0x0090 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. + $EN_DIS +**/ + uint8_t HideP2sb; + +/** Offset 0x0091 - Ufs Enable/Disable + Enable/Disable Ufs. + $EN_DIS +**/ + uint8_t UfsEnabled; + +/** Offset 0x0092 - IPU Enable/Disable + Enable/Disable IPU Device. + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x0093 - IMGU ACPI mode selection + 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x0094 - ResetSelect + ResetSelect. 0x6:warm reset; 0xE:cold reset +**/ + uint8_t ResetSelect; + +/** Offset 0x0095 - CRIDSettings + PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +**/ + uint8_t CRIDSettings; + +/** Offset 0x0096 - Enable HPET + Enable/disable HPET. + $EN_DIS +**/ + uint8_t Hpet; + +/** Offset 0x0097 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating.0:Enable;1:Disable + $EN_DIS +**/ + uint8_t PcieClockGatingDisabled; + +/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPort8xhDecode; + +/** Offset 0x0099 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. +**/ + uint8_t Pcie8xhDecodePortIndex; + +/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x009B - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x009C - GttMmAdr + GttMmAdr structure for initialization. +**/ + uint32_t GttMmAdr; + +/** Offset 0x00A0 +**/ + uint8_t UnusedUpdSpace5[96]; + +/** Offset 0x0100 - Enable S0ix + Enable/disable S0ix.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t S0ix; + +/** Offset 0x0101 - GmAdr + GmAdr structure for initialization. +**/ + uint32_t GmAdr; + +/** Offset 0x0105 - Enable ForceWake + Enable/disable ForceWake Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0106 - Enable PavpLock + Enable/disable PavpLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0107 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0108 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0109 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x010A - Enable PmLock + Enable/disable PmLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x010B +**/ + uint8_t UnusedUpdSpace6[5]; + +/** Offset 0x0110 - Enable DopClockGating + Enable/disable DopClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x0111 - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x0112 - Enable WOPCMSupport + Enable/disable WOPCMSupport.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x0113 - Enable WOPCMSize + Enable/disable WOPCMSize.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x0114 - Enable PowerGating + Enable/disable PowerGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x0115 - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0116 - Enable FastBoot + Enable/disable FastBoot.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0117 - Enable DynSR + Enable/disable DynSR.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0118 - Enable SaIpuEnable + Enable/disable SaIpuEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0119 - Enable VtdEnable + Enable/disable VtdEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t VtdEnable; + +/** Offset 0x011A - BMP Logo Data Size + BMP logo data buffer size. +**/ + uint32_t LogoSize; + +/** Offset 0x011E - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. +**/ + uint32_t LogoPtr; + +/** Offset 0x0122 - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x0126 - GT PM Support + Enable/Disable GT power management support. + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0127 - RC6(Render Standby) + Enable/Disable render standby support. + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0128 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0129 - PAVP PR3 + Enable/Disable PAVP PR3 + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x012A - CdClock Frequency selection + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock + $EN_DIS +**/ + uint8_t Timer8254ClkSetting; + +/** Offset 0x012D +**/ + uint8_t ReservedFspsUpd[211]; +} __attribute__((packed)); + +/** Fsp S Test Configuration +**/ +struct FSP_S_TEST_CONFIG { + +/** Offset 0x0200 +**/ + uint32_t Signature; + +/** Offset 0x0204 +**/ + uint8_t ReservedFspsTestUpd[12]; +} __attribute__((packed)); + +/** Fsp S Restricted Configuration +**/ +struct FSP_S_RESTRICTED_CONFIG { + +/** Offset 0x0210 +**/ + uint32_t Signature; + +/** Offset 0x0214 +**/ + uint8_t ReservedFspsRestrictedUpd[12]; +} __attribute__((packed)); + +#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_S_CONFIG FspsConfig; + +/** Offset 0x0200 +**/ + struct FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0210 +**/ + struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x0220 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h new file mode 100644 index 0000000..d12eb19 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOMAP_H_ +#define _SOC_APOLLOLAKE_IOMAP_H_ + +#define P2SB_BAR 0xd0000000 +#define MCH_BASE_ADDR 0xfed10000 +#define MCH_BASE_SIZE (32 * KiB) + +#define ACPI_PMIO_BASE 0x400 +#define R_ACPI_PM1_TMR 0x8 + +/* Accesses to these BARs are hardcoded in FSP */ +#define PMC_BAR0 0xfe042000 +#define PMC_BAR1 0xfe044000 + +#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h new file mode 100644 index 0000000..a6bf540 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_ +#define _SOC_APOLLOLAKE_ROMSTAGE_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +asmlinkage void romstage_car_entry(void); +void mainboard_memory_init_params(struct FSP_M_CONFIG *m_config); + +#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c new file mode 100644 index 0000000..7f3de22 --- /dev/null +++ b/src/soc/intel/apollolake/romstage.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/symbols.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/FspmUpd.h> +#include <fsp/util.h> +#include <device/resource.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/northbridge.h> +#include <soc/romstage.h> +#include <soc/uart.h> + +#define FIT_POINTER (0x100000000ULL - 0x40) + +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + device_t pmc = PMC_DEV; + + /* Set MCH base address and enable bit */ + pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set earlier, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET. Needed for FSP global pointer storage */ + pci_write_config32(P2SB_DEV, 0x60, 1<<7); +} + +static void disable_watchdog(void) +{ + uint32_t reg; + device_t dev = PMC_DEV; + + /* Open up an IO window */ + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* Stop TCO timer */ + reg = inl(ACPI_PMIO_BASE + 0x68); + reg |= 1 << 11; + outl(reg, ACPI_PMIO_BASE + 0x68); +} + + +asmlinkage void romstage_car_entry(void) +{ + void *hob_list_ptr; + struct resource fsp_mem; + struct range_entry reg_car; + + /* Be careful. Bootblock might already have initialized the console */ + if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + + printk(BIOS_DEBUG, "Starting romstage...\n"); + + disable_watchdog(); + + soc_early_romstage_init(); + + /* We will load FSP blob into CAR, but only in the free region */ + reg_car.begin = (uint32_t) _car_data_end; + reg_car.end = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE ; + + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { + die("FSP memory init failed. Giving up."); + } + + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + + /* initialize cbmem by adding FSP reserved memory first thing */ + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_mem.size); + + /* make sure FSP memory is reserved in cbmem */ + if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) + die("Failed to accommodate FSP reserved memory request"); + + /* Now that CBMEM is up, save the list so ramstage can use it */ + fsp_save_hob_list(hob_list_ptr); + + run_ramstage(); +} + +static void fill_console_params(struct FSP_M_CONFIG *m_config) +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + m_config->SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + m_config->SerialDebugPortType = 2; + m_config->SerialDebugPortStrideSize = 2; + m_config->SerialDebugPortAddress = 0; + } else { + m_config->SerialDebugPortType = 0; + } +} + +void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd, + struct FSP_M_CONFIG *m_config) +{ + fill_console_params(m_config); + mainboard_memory_init_params(m_config); + + /* Do NOT let FSP do any GPIO pad configuration */ + m_config->GpioPadInitTablePtr = NULL; + /* At FIT_POINTER there is an address that points to FIT */ + m_config->FitTablePtr = read32((void*) FIT_POINTER); + /* Reserve enough memory under TOLUD to save CBMEM header */ + archupd->bootloader_tolumsz = cbmem_overhead_size(); + /* + * It has nothing to with our stack size. We just ask FSP not to + * tromp over our car data. FSP thinks coreboot only has stack, + * so we pretend all our car data+stack is 'stack'. + */ + archupd->stack_base = (uint32_t) CONFIG_DCACHE_RAM_BASE; + archupd->stack_size = _car_data_end - _car_data_start; +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct FSP_M_CONFIG *m_config) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

1 0

Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR
by Andrey Petrov 01 Mar '16

01 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861 -gerrit commit f3f124d0b0a6fc942c12a0f3d3d7588068f33f48 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:37:15 2016 -0800 arch/x86: Add common assembly code for stages that run in CAR This adds a few assembly lines that are generic enought to be shared between romstage and verstage that are ran in CAR. Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/arch/x86/carstage_entry.S | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/src/arch/x86/carstage_entry.S b/src/arch/x86/carstage_entry.S new file mode 100644 index 0000000..4a601a7 --- /dev/null +++ b/src/arch/x86/carstage_entry.S @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.global _start +_start: + +#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ + /* + * This code is meant to be used for stages that are ran in CAR. + * The assumption is that gdt is already loaded. So in order to + * continue with C code execution we needed to set stack pointer + * and clear CAR_GLOBAL variables that are stage-specific. + */ + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp romstage_car_entry + movb $0x69, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable using FSP 2.0 driver
by Andrey Petrov 01 Mar '16

01 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13806 -gerrit commit c75b4174527dd804cc53d8d9d3ac9ae8b648ab81 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2ff93c9..bd64ea3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 + select PLATFORM_USES_FSP2_0 + select ADD_FSP_BINARIES config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

1 0

Patch set updated for coreboot: FSP2.0: Add hand-off-block parsers
by Andrey Petrov 01 Mar '16

01 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13801 -gerrit commit 2a884313781d26770b6dd275f29c304d51fb8310 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 FSP2.0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 294 ++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c new file mode 100644 index 0000000..3bc33af --- /dev/null +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -0,0 +1,294 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fsp/util.h> +#include <inttypes.h> +#include <lib.h> +#include <string.h> + +#define HOB_HEADER_LEN 8 + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + +static const char *resource_names[] = { + [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY", + [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO", + [EFI_RESOURCE_IO] = "IO", + [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE", + [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT", + [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED", + [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + +static const uint8_t uuid_owner_fsp[16] = { + 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, +}; + +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + +static const uint8_t empty_uuid[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + +static const char *resource_name(enum resource_type type) +{ + if (type >= ARRAY_SIZE(resource_names)) + return "UNKNOWN"; + return resource_names[type]; +} + +/* + * Utilities for walking HOBs + */ + +static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +{ + return !memcmp(uuid1, uuid2, 16); +} + +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + +static const struct hob_header *next_hob(const struct hob_header *parent) +{ + union { + const struct hob_header *hob; + uintptr_t addr; + } hob_walker; + + hob_walker.hob = parent; + hob_walker.addr += parent->length; + return hob_walker.hob; +} + +static const void *hob_header_to_struct(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN; + return hob_walker.hob_descr; +} + +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + +static const +struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +{ + return hob_header_to_struct(hob); +} + +/* + * Utilities for locating and identifying HOBs + */ + +void fsp_save_hob_list(void *hob_list_ptr) +{ + void **cbmem_loc; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr)); + *cbmem_loc = hob_list_ptr; +} + +const void *fsp_get_hob_list(void) +{ + void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); + + return (list_loc) ? (*list_loc) : NULL; +} + +static const +struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, + const uint8_t uuid[16]) +{ + const struct hob_resource *res; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = hob_header_to_resource(hob); + if (uuid_compare(res->owner_guid, uuid)) + return res; + } + return NULL; +} + +void fsp_find_reserved_memory(struct resource *res, const void *hob_list) +{ + const struct hob_resource *fsp_mem; + + memset(res, 0, sizeof(*res)); + + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + + if (!fsp_mem) { + return; + } + + res->base = fsp_mem->addr; + res->size = fsp_mem->length; +} + +/* + * Utilities for printing HOB information + */ + +static void print_guid(const void *base) +{ + uint32_t big; + uint16_t mid[2]; + + const uint8_t *id = base; + big = read32(id + 0); + mid[0] = read16(id + 4); + mid[1] = read16(id + 6); + + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + big, mid[0], mid[1], + id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); +} + +static void print_resource_descriptor(const void *base) +{ + const struct hob_resource *res; + + res = hob_header_to_resource(base); + + printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + resource_name(res->type), res->attribute_type); + printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + if (!uuid_compare(res->owner_guid, empty_uuid)) { + printk(BIOS_DEBUG, "\tOwner GUID: "); + print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + } +} + + +void fsp_print_memory_resource_hobs(const void *hob_list) +{ + const struct hob_header *hob = hob_list; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) + print_resource_descriptor(hob); + } +} + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +}

1 0

Patch set updated for coreboot: FSP2.0: Add Notify Phase API
by Andrey Petrov 01 Mar '16

01 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13800 -gerrit commit 3d6a3c87c80d17a477a93b23f0e76bb30a0f4a68 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:19:07 2016 -0800 FSP2.0: Add Notify Phase API This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/notify.c | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..e9e2780 --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +typedef struct fsp_notify_params { + enum fsp_notify_phase phase; +} NOTIFY_PHASE_PARAMS; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify; + NOTIFY_PHASE_PARAMS NotifyPhaseParam = { .phase = phase }; + + if (!fsps_hdr.silicon_init_entry_offset) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr.image_base + + fsps_hdr.notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify(&NotifyPhaseParam); +}

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016