coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: rockchip/rk3399: dram: improve dram stability when run high frequency
by Patrick Georgi 07 Oct '16

07 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16722 -gerrit commit 49bd5471b62adddb5c1ce725196f5a7e4ea93a82 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 18:19:24 2016 +0800 rockchip/rk3399: dram: improve dram stability when run high frequency there are two modify in the driver: 1. correctly set speeds base on DDR frequency. Controls the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. config the number of cycles phy clock pll wait time after locking base on ddr config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9211895..1021c6b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -322,6 +322,7 @@ static void phy_io_config(u32 channel, u32 mode_sel = 0; u32 reg_value; u32 drv_value, odt_value; + u32 speed; /* vref setting */ if (sdram_params->dramtype == LPDDR4) { @@ -436,22 +437,33 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + /* speed setting */ + if (sdram_params->ddr_freq < 400*MHz) + speed = 0x0; + else if (sdram_params->ddr_freq < 800*MHz) + speed = 0x1; + else if (sdram_params->ddr_freq < 1200*MHz) + speed = 0x2; + else + speed = 0x3; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21); + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); } static void pctl_cfg(u32 channel, @@ -477,9 +489,10 @@ static void pctl_cfg(u32 channel, /* rank count need to set for init */ set_memory_map(channel, sdram_params); - write32(&denali_phy[910], 0x6400); - write32(&denali_phy[911], 0x01221102); - write32(&denali_phy[912], 0x0); + write32(&denali_phy[910], sdram_params->phy_regs.denali_phy[910]); + write32(&denali_phy[911], sdram_params->phy_regs.denali_phy[911]); + write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); + pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

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New patch to review for coreboot: mainboard/emulation: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16916 -gerrit commit d0044e0c5625d90cb2af11fac4147a4c3632adc2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 13:02:31 2016 +0200 mainboard/emulation: Use C89 comments style & remove commented code Change-Id: I627338505fe1273366bc8f6f528d829b3162b371 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/emulation/qemu-i440fx/romstage.c | 3 --- src/mainboard/emulation/qemu-power8/bootblock.c | 4 ++-- src/mainboard/emulation/qemu-power8/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/acpi_tables.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 3 --- src/mainboard/emulation/qemu-riscv/bootblock.c | 4 ++-- src/mainboard/emulation/qemu-riscv/qemu_util.c | 18 +++++++----------- src/mainboard/emulation/spike-riscv/bootblock.c | 4 ++-- src/mainboard/emulation/spike-riscv/spike_util.c | 5 ++--- 9 files changed, 17 insertions(+), 28 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index bc23929..1676fb0 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -40,9 +40,6 @@ void * asmlinkage romstage_main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - //print_pci_devices(); - //dump_pci_devices(); - cbmem_was_initted = !cbmem_recovery(0); timestamp_init(timestamp_get()); diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index d92c169..9927fdc 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -17,8 +17,8 @@ #include <console/console.h> #include <program_loading.h> -// the qemu part of all this is very, very non-hardware like. -// so it gets its own bootblock. +/* the qemu part of all this is very, very non-hardware like. */ +/* so it gets its own bootblock. */ void main(void) { if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c index 102f54c..41df2ca 100644 --- a/src/mainboard/emulation/qemu-power8/mainboard.c +++ b/src/mainboard/emulation/qemu-power8/mainboard.c @@ -26,7 +26,7 @@ static void mainboard_enable(device_t dev) ; } - // Where does RAM live? + /* Where does RAM live? */ ram_resource(dev, 0, 2048, 32768); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 07589e1..1b32c02 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -204,7 +204,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; reg = pci_read_config32(dev, 0x60); - if ((reg & 0x07) != 0x01) // require enabled + 256MB size + if ((reg & 0x07) != 0x01) /* require enabled + 256MB size */ return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 1bb51da..870dd07 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -42,9 +42,6 @@ void * asmlinkage romstage_main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - //print_pci_devices(); - //dump_pci_devices(); - cbmem_was_initted = !cbmem_recovery(0); timestamp_init(timestamp_get()); diff --git a/src/mainboard/emulation/qemu-riscv/bootblock.c b/src/mainboard/emulation/qemu-riscv/bootblock.c index 3e88620..14286e3 100644 --- a/src/mainboard/emulation/qemu-riscv/bootblock.c +++ b/src/mainboard/emulation/qemu-riscv/bootblock.c @@ -18,8 +18,8 @@ #include <console/console.h> #include <program_loading.h> -// the qemu part of all this is very, very non-hardware like. -// so it gets its own bootblock. +/* the qemu part of all this is very, very non-hardware like. */ +/* so it gets its own bootblock. */ void main(void) { if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index 216eea9..01a4c61 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -33,8 +33,7 @@ #include <string.h> uintptr_t translate_address(uintptr_t vAddr) { - // TODO: implement the page table translation algorithm - //uintptr_t pageTableRoot = read_csr(sptbr); + /* TODO: implement the page table translation algorithm */ uintptr_t physAddrMask = 0xfffffff; uintptr_t translationResult = vAddr & physAddrMask; printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult); @@ -46,7 +45,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t physicalAddr = translate_address((uintptr_t) p); memory_block_info *info = (memory_block_info*) physicalAddr; if (id == 0) { - info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later + info->base = 0x1000000; /* hard coded for now, but we can put these values somewhere later */ info->size = 0x7F000000 - info->base; return 0; } @@ -62,7 +61,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient) uintptr_t mcall_clear_ipi(void) { - // only clear SSIP if no other events are pending + /* only clear SSIP if no other events are pending */ if (HLS()->device_response_queue_head == NULL) { clear_csr(mip, MIP_SSIP); mb(); @@ -104,13 +103,12 @@ uintptr_t mcall_dev_resp(void) sbi_device_message* m = HLS()->device_response_queue_head; if (m) { - //printm("resp %p\n", m); sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); HLS()->device_response_queue_head = next; if (!next) { HLS()->device_response_queue_tail = 0; - // only clear SSIP if no other events are pending + /* only clear SSIP if no other events are pending */ clear_csr(mip, MIP_SSIP); mb(); if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); @@ -153,7 +151,7 @@ uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { if (m->dev == dev && m->cmd == cmd) { m->data = data; - // dequeue from request queue + /* dequeue from request queue */ if (prev) prev->sbi_private_data = (uintptr_t)next; else @@ -161,7 +159,7 @@ uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { HLS()->device_request_queue_size = n-1; m->sbi_private_data = 0; - // enqueue to response queue + /* enqueue to response queue */ if (HLS()->device_response_queue_tail) { HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; @@ -172,7 +170,7 @@ uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { } HLS()->device_response_queue_tail = m; - // signal software interrupt + /* signal software interrupt */ set_csr(mip, MIP_SSIP); return 0; } @@ -180,9 +178,7 @@ uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { prev = m; m = (void*)atomic_read(&m->sbi_private_data); } - //HLT(); return 0; - //panic("htif: no record"); } uintptr_t mcall_console_putchar(uint8_t ch) diff --git a/src/mainboard/emulation/spike-riscv/bootblock.c b/src/mainboard/emulation/spike-riscv/bootblock.c index 40a7de1..c4c886c 100644 --- a/src/mainboard/emulation/spike-riscv/bootblock.c +++ b/src/mainboard/emulation/spike-riscv/bootblock.c @@ -18,8 +18,8 @@ #include <console/console.h> #include <program_loading.h> -// the qemu part of all this is very, very non-hardware like. -// so it gets its own bootblock. +/* the qemu part of all this is very, very non-hardware like. */ +/* so it gets its own bootblock. */ void main(void) { if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index 7ddf16b..26789b4 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -34,8 +34,7 @@ #include <vm.h> uintptr_t translate_address(uintptr_t vAddr) { - // TODO: implement the page table translation algorithm - //uintptr_t pageTableRoot = read_csr(sptbr); + /* TODO: implement the page table translation algorithm */ uintptr_t physAddrMask = 0xfffffff; uintptr_t translationResult = vAddr & physAddrMask; printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult); @@ -63,7 +62,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient) uintptr_t mcall_clear_ipi(void) { - // only clear SSIP if no other events are pending + /* only clear SSIP if no other events are pending */ if (HLS()->device_response_queue_head == NULL) { clear_csr(mip, MIP_SSIP); mb();

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Patch set updated for coreboot: mainboard/hp: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16915 -gerrit commit 1e873cd83599e82698515fb4da256eab25db0f5f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 12:51:08 2016 +0200 mainboard/hp: Use C89 comments style & remove commented code Change-Id: I6a38b923a1a2e701cae31d3a6eeacb0eec3e581e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/hp/abm/BiosCallOuts.c | 2 +- src/mainboard/hp/abm/OptionsIds.h | 10 -- src/mainboard/hp/abm/buildOpts.c | 147 +++++---------------- src/mainboard/hp/abm/mptable.c | 4 - src/mainboard/hp/abm/romstage.c | 6 +- src/mainboard/hp/dl145_g1/acpi_tables.c | 47 ------- src/mainboard/hp/dl145_g1/fadt.c | 49 ++----- src/mainboard/hp/dl145_g1/get_bus_conf.c | 26 +--- src/mainboard/hp/dl145_g1/irq_tables.c | 8 +- src/mainboard/hp/dl145_g1/mptable.c | 32 ++--- src/mainboard/hp/dl145_g1/resourcemap.c | 2 - src/mainboard/hp/dl145_g1/romstage.c | 19 +-- src/mainboard/hp/dl145_g3/get_bus_conf.c | 27 ++-- src/mainboard/hp/dl145_g3/irq_tables.c | 35 +++-- src/mainboard/hp/dl145_g3/mptable.c | 37 ++---- src/mainboard/hp/dl145_g3/romstage.c | 45 ++----- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 1 - src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 8 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 14 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 15 +-- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 +- src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 10 -- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 139 ++++++------------- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - 24 files changed, 187 insertions(+), 507 deletions(-) diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 70573be..c0487b5 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -52,7 +52,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index 544ac53..f8977f5 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -48,17 +48,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif /* _OPTION_IDS_H_ */ diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 2f31c5e..e90bca0 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -58,36 +58,22 @@ #endif #endif -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -109,11 +95,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -154,15 +140,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -179,43 +160,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -249,40 +193,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */ /* * Agesa optional capabilities selection. @@ -327,26 +252,26 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL hp_abm_gpio[] = { - { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED - { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID - { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH - { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT - { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L - { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC - { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L - { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT - { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT - { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R + { 45, Function2, GpioOutEnB | Sticky }, /* Signal input APU_SD_LED */ + { 49, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_UID */ + { 50, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_HEALTH */ + { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_FAULT */ + { 57, Function2, GpioOutEnB | Sticky }, /* Signal input SATA_PRSNT_L */ + { 58, Function2, GpioOutEnB | Sticky }, /* Signal i/o APU_HDMI_CEC */ + { 64, Function2, GpioOutEnB | Sticky }, /* Signal input SWC_APU_INT_L */ + { 68, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL1_PRSNT */ + { 69, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL2_PRSNT */ + { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_PROCHOT_L_R */ {-1} }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 6241282..4ff8ea1 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -113,9 +112,6 @@ static void *smp_write_config_table(void *v) outb(0x48, 0xCD6); outb(0xF2, 0xCD7); - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - outb(0xED, 0xCD6); outb(0x17, 0xCD7); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 6e77c57..4d3daed 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -60,14 +60,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz + t32 &= 0xffc0ffff; /* Clr bits [21:19] & [18:16] */ + t32 |= 0x00010000; /* Set bit 16 for 25MHz */ *addr32 = t32; /* Enable Auxiliary OSCOUT1/OSCOUT2 */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; - t32 &= 0xffffff7b; // clear 2, 7 + t32 &= 0xffffff7b; /* clear 2, 7 */ *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index 47e0a3a..d5dd1dc 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -63,53 +63,6 @@ unsigned long acpi_fill_madt(unsigned long current) gsi_base+=4; } } - - /* - int i; - int j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { - unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 - - switch (sysconf.hcid[i]) { - case 1: - d = 7; - break; - case 3: - d = 4; - break; - } - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - */ - } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c index 877cb5b..fd7a807 100644 --- a/src/mainboard/hp/dl145_g1/fadt.c +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -28,12 +28,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x04; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f; */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; @@ -57,47 +57,27 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_base = 16; fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state - fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state - fadt->flush_size = 0; // ignored if wbindv = 1 in flags - fadt->flush_stride = 0; // ignored if wbindv = 1 in flags + fadt->p_lvl2_lat = 101; /* 100 means system doesnt support C2 state */ + fadt->p_lvl3_lat = 1001; /* 1000 means system doesnt support C3 state */ + fadt->flush_size = 0; /* ignored if wbindv = 1 in flags */ + fadt->flush_stride = 0; /* ignored if wbindv = 1 in flags */ fadt->duty_offset = 1; - fadt->duty_width = 3; // 0 means duty cycle not supported - // _alrm value 0 means RTC alarm feature not supported - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work + fadt->duty_width = 3; /* 0 means duty cycle not supported */ + /* _alrm value 0 means RTC alarm feature not supported */ + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042 | - // ACPI_FADT_VGA_NOT_PRESENT | - // ACPI_FADT_MSI_NOT_SUPPORTED| - // ACPI_FADT_NO_PCIE_ASPM_CONTROL| 0; fadt->res2 = 0; fadt->flags = ACPI_FADT_WBINVD | - // ACPI_FADT_WBINVD_FLUSH | ACPI_FADT_C1_SUPPORTED | - // ACPI_FADT_C2_MP_SUPPORTED | - // ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON | - // ACPI_FADT_FIXED_RTC | - // ACPI_FADT_S4_RTC_WAKE | - // ACPI_FADT_32BIT_TIMER | - // ACPI_FADT_DOCKING_SUPPORTED| - // ACPI_FADT_RESET_REGISTER | - // ACPI_FADT_SEALED_CASE | - // ACPI_FADT_HEADLESS | - // ACPI_FADT_SLEEP_TYPE | - // ACPI_FADT_PCI_EXPRESS_WAKE | - // ACPI_FADT_PLATFORM_CLOCK | - // ACPI_FADT_S4_RTC_VALID | - // ACPI_FADT_REMOTE_POWER_ON | - // ACPI_FADT_APIC_CLUSTER | - // ACPI_FADT_APIC_PHYSICAL | 0; fadt->reset_reg.space_id = 1; @@ -146,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -154,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm2_cnt_blk.addrl = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -162,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm_tmr_blk.addrl = pm_base+0x08; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; @@ -170,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe0_blk.addrl = pm_base+0x20; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 64; fadt->x_gpe1_blk.bit_offset = 16; @@ -179,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - } diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index da02095..a52e3ab 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -14,31 +14,17 @@ #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +{ /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; @@ -52,7 +38,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -101,7 +87,7 @@ void get_bus_conf(void) } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index 597acca..88275c8 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -38,7 +38,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t sum = 0; int i; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ /* Align the table to be 16 byte aligned. */ addr += 15; @@ -67,15 +67,12 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//pci bridge +/* pci bridge */ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; pirq_info++; slot_num++; @@ -94,5 +91,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 1a9132e..c4bc0db 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR); { device_t dev; @@ -54,31 +54,23 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); - // - // The commented-out lines are auto-detected on my servers. - // -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); - // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); - // Integrated AMD USB + /* The commented-out lines are auto-detected on my servers. */ + +/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Integrated SMBus 2.0 */ + + /* Integrated AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); - // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); - // On board Broadcom nics + /* On board ATI Rage XL */ + + /* On board Broadcom nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); - // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); + /* On board LSI SCSI */ - // PCIX-133 Slot + /* PCIX-133 Slot */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c index 65a4610..8a43841 100644 --- a/src/mainboard/hp/dl145_g1/resourcemap.c +++ b/src/mainboard/hp/dl145_g1/resourcemap.c @@ -120,7 +120,6 @@ static void setup_dl145g1_resource_map(void) PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, @@ -156,7 +155,6 @@ static void setup_dl145g1_resource_map(void) PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index ea0b60c..b295ca7 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -97,11 +97,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - //first node + /* first node */ RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, #endif @@ -123,12 +123,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); - //setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif @@ -150,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -180,22 +179,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) change_i2c_mux(i); } - //dump_spd_registers(&sysinfo->ctrl[0]); - //dump_spd_registers(&sysinfo->ctrl[1]); - //dump_smbus_registers(); - allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl now; + /* It's the time to set ctrl now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); #if CONFIG_SET_FIDVID - init_timer(); // Need to use TMICT to synchronize FID/VID + init_timer(); /* Need to use TMICT to synchronize FID/VID */ #endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - //dump_pci_devices(); - post_cache_as_ram(); } diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index d69e224..12f7b89 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -17,6 +17,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -28,31 +29,19 @@ #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +{ /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; @@ -68,7 +57,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -86,7 +75,7 @@ void get_bus_conf(void) get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */ m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_bcm5780[0] = m->bus_bcm5785_0; @@ -120,7 +109,7 @@ void get_bus_conf(void) } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c index 6ec1fd8..f2937b1 100644 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ b/src/mainboard/hp/dl145_g3/irq_tables.c @@ -20,26 +20,21 @@ static const struct irq_routing_table intel_irq_routing_table = { bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge - {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb - {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr - {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge - {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA - {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge - //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, - {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, - {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */ + {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 legacy southbridge */ + {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 usb */ + {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* VGA Contr */ + {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 pci/pci-x bridge */ + {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom BCM5785 [HT1000] SATA */ + {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5785 [HT1000] PCI/PCI-X Bridge */ + {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5715 Gigabit Ethernet */ + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */ + {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* HTX slot */ } }; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 3a784e7..c7ab385 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /*I/O APICs: APIC ID Version State Address*/ + /* I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; int i; @@ -74,15 +74,12 @@ static void *smp_write_config_table(void *v) /* IRQ routing as factory BIOS */ outb(0x01, 0xc00); outb(0x0A, 0xc01); outb(0x17, 0xc00); outb(0x05, 0xc01); -/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */ -/* outb(0x07, 0xc00); outb(0x07, 0xc01); */ outb(0x07, 0xc00); outb(0x0b, 0xc01); outb(0x24, 0xc00); outb(0x05, 0xc01); - //outb(0x00, 0xc00); outb(0x09, 0xc01); outb(0x02, 0xc00); outb(0x0E, 0xc01); - // 8259 registers... + /* 8259 registers... */ outb(0xa0, 0x4d0); outb(0x0e, 0x4d1); @@ -92,16 +89,16 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */ pci_write_config32(dev, 0x64, dword); } - // set GEVENT pins to NO OP + /* set GEVENT pins to NO OP */ outb(0x33, 0xcd6); outb(0x00, 0xcd7); outb(0x34, 0xcd6); outb(0x00, 0xcd7); outb(0x35, 0xcd6); outb(0x00, 0xcd7); } - // hide XIOAPIC PCI configuration space + /* hide XIOAPIC PCI configuration space */ { device_t dev; dev = dev_find_device(0x1166, 0x205, 0); @@ -115,31 +112,26 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); - //SATA -/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ -/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ + /* SATA */ printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); - //USB + /* USB */ printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa); - //VGA + /* VGA */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7); - //PCIE + /* PCIE */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe); - //IDE -// outb(0x02, 0xc00); outb(0x0e, 0xc01); -// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); -// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe); + /* IDE */ - //onboard Broadcom GbE + /* onboard Broadcom GbE */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4); @@ -153,17 +145,17 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts + dword |= (1 << 4); /* enable interrupts */ printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } } -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ +/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa); mptable_lintsrc(mc, bus_isa); - //extended table entries + /* extended table entries */ smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); @@ -174,7 +166,6 @@ static void *smp_write_config_table(void *v) smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); - /* Compute the checksums */ return mptable_finalize(mc); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 1d1195a..af9793e 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -85,28 +85,9 @@ static void setup_early_ipmi_serial() char serial_mux2[]={0x0c << 2,0x12,0x04,0x03}; char serial_mux3[]={0x0c << 2,0x12,0x04,0x07}; -// earlydbg(0x0d); - //set channel access system only - ipmi_request(5,channel_access); -// earlydbg(result); -/* - //Set serial/modem config - result = ipmi_request(6,serialmodem_conf); - earlydbg(result); - - //Set serial mux 1 - result = ipmi_request(4,serial_mux1); - earlydbg(result); - //Set serial mux 2 - result = ipmi_request(4,serial_mux2); - earlydbg(result); - - //Set serial mux 3 - result = ipmi_request(4,serial_mux3); - earlydbg(result); -*/ -// earlydbg(0x0e); + /* set channel access system only */ + ipmi_request(5,channel_access); } #endif @@ -114,10 +95,10 @@ static void setup_early_ipmi_serial() void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // first node + /* first node */ DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // second node + /* second node */ DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; @@ -144,17 +125,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -// setup_early_ipmi_serial(); - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -164,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ bcm5785_early_setup(); #if CONFIG_SET_FIDVID @@ -176,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -187,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); @@ -195,13 +175,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /*It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output + /*do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ - // init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 479e0b6..4286cac 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -28,7 +28,6 @@ void shc4307_init(void) pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); - /* pnp_set_enable(CMOS_DEV, 3); */ pnp_write_config(CMOS_DEV, 0x30, 3); pnp_set_logical_device(KBD_DEV); /* Keyboard */ diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 68c3881..a20cd7b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; /* Here you only need to set value in pci1234 for HT-IO that could be @@ -69,7 +69,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -88,7 +88,7 @@ void get_bus_conf(void) get_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */ m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff; m->bus_bcm5780[0] = m->bus_bcm5785_0; @@ -122,7 +122,7 @@ void get_bus_conf(void) } } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ apicid_base = 0x10; for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 17e42e4..b7aab80 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) outb(0x03, 0xc00); outb(0x07, 0xc01); outb(0x07, 0xc00); outb(0x05, 0xc01); - // 8259 registers... + /* 8259 registers... */ outb(0xa0, 0x4d0); outb(0x0e, 0x4d1); @@ -89,16 +89,12 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */ pci_write_config32(dev, 0x64, dword); } - // set GEVENT pins to NO OP - /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); - outb(0x34, 0xcd6); outb(0x00, 0xcd7); - outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ } - // hide XIOAPIC PCI configuration space + /* hide XIOAPIC PCI configuration space */ { device_t dev; dev = dev_find_device(0x1166, 0x205, 0); @@ -132,7 +128,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts + dword |= (1 << 4); /* enable interrupts */ printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } @@ -141,7 +137,7 @@ static void *smp_write_config_table(void *v) /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); - //extended table entries + /* extended table entries */ smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 39cd0e3..5a98c23 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -78,11 +78,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr - //first node + /* switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr */ + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; @@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); @@ -172,10 +172,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -198,9 +198,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 87d6eae..231a188 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -122,8 +122,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /*BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /*6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -134,7 +134,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -157,7 +157,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;/*BIT0 | BIT4 |BIT8; */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -186,7 +186,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 48258ca..7763b80 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -65,35 +65,21 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -141,7 +127,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -153,16 +139,10 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. */ +/* If not specified, the values used for the core VRM will be applied */ + #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -172,17 +152,13 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -190,43 +166,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -246,40 +185,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -324,7 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 /* * The GPIO control is not well documented in AGESA, but is in the BKDG @@ -376,9 +314,10 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = { }; #define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 9e63caf..23c0485 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02;

1 0

Patch set updated for coreboot: mainboard/apple: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16913 -gerrit commit 9f44fc02f254f4a8be088281dc6ca5922e485e97 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 12:46:28 2016 +0200 mainboard/apple: Use C89 comments style & remove commented code Change-Id: I81c32c618627507cc3a83f60f565a73e5e6d7a13 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/apple/macbook21/romstage.c | 200 ++++++++++++++++--------------- src/mainboard/apple/macbookair4_2/gnvs.c | 2 +- 2 files changed, 103 insertions(+), 99 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 695f1cd..391b09f 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -89,110 +89,116 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // I/O Decode Ranges - // X60: 0x0210 == 00000010 00010000 - // Macbook21: 0x0010 == 00000000 00010000 - // Bit 9:8 LPT Decode Range. This field determines which range to - // decode for the LPT Port. - // 00 = 378h - 37Fh and 778h - 77Fh - // 10 = 3BCh - 3BEh and 7BCh - 7BEh + /* I/O Decode Ranges + * X60: 0x0210 == 00000010 00010000 + * Macbook21: 0x0010 == 00000000 00010000 + * Bit 9:8 LPT Decode Range. This field determines which range to + * decode for the LPT Port. + * 00 = 378h - 37Fh and 778h - 77Fh + * 10 = 3BCh - 3BEh and 7BCh - 7BEh + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // LPC_EN--LPC I/F Enables Register - // X60: 0x1f0d == 00011111 00001101 - // Macbook21: 0x3807 == 00111000 00000111 - // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - // to the LPC interface. This range is used for - // Super I/O devices. - // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 62h and 66h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 60h and 64h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 208h to 20Fh - // to the LPC interface. This range is used for a gameport. - // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 200h to 207h - // to the LPC interface. This range is used for a gameport. - // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - // 0 = Disable. - // 1 = Enables the decoding of the FDD range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 12). - // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - // 0 = Disable. - // 1 = Enables the decoding of the LPT range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 9:8). - // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMB range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 6:4). - // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMA range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 3:2). + /* LPC_EN--LPC I/F Enables Register + * X60: 0x1f0d == 00011111 00001101 + * Macbook21: 0x3807 == 00111000 00000111 + * Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + * to the LPC interface. This range is used for + * Super I/O devices. + * Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 62h and 66h + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 60h and 64h + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 208h to 20Fh + * to the LPC interface. This range is used for a gameport. + * Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 200h to 207h + * to the LPC interface. This range is used for a gameport. + * Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + * 0 = Disable. + * 1 = Enables the decoding of the FDD range to the LPC + * interface. This range is selected in the LPC_FDD/LPT + * Decode Range Register (D31:F0:80h, bit 12). + * Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + * 0 = Disable. + * 1 = Enables the decoding of the LPT range to the LPC + * interface. This range is selected in the LPC_FDD/LPT + * Decode Range Register (D31:F0:80h, bit 9:8). + * Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + * 0 = Disable. + * 1 = Enables the decoding of the COMB range to the LPC + * interface. This range is selected in the LPC_COM Decode + * Range Register (D31:F0:80h, bits 6:4). + * Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + * 0 = Disable. + * 1 = Enables the decoding of the COMA range to the LPC + * interface. This range is selected in the LPC_COM Decode + * Range Register (D31:F0:80h, bits 3:2). + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); - /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ - // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - // Bit 31:24 Reserved. - // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - // bit position indicates that any value in the corresponding - // address bit in a received cycle will be treated as a - // match. The corresponding bit in the Address field, below, - // is ignored. The mask is only provided for the lower 6 bits - // of the DWord address, allowing for decoding blocks up to - // 256 bytes in size. - // Bit 17:16 Reserved. - // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - // address is aligned on a 128-byte boundary, and must have - // address lines 31:16 as 0. NOTE: The Intel ICH7 does not - // provide decode down to the word or byte level. - // Bit 1 Reserved. - // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - // 0 = Disable. - // 1 = Enable the GEN1 I/O range to be forwarded to the LPC - // I/F + /* GEN1_DEC, LPC Interface Generic Decode Range 1 + * X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + * Bit 31:24 Reserved. + * Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + * bit position indicates that any value in the corresponding + * address bit in a received cycle will be treated as a + * match. The corresponding bit in the Address field, below, + * is ignored. The mask is only provided for the lower 6 bits + * of the DWord address, allowing for decoding blocks up to + * 256 bytes in size. + * Bit 17:16 Reserved. + * Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + * address is aligned on a 128-byte boundary, and must have + * address lines 31:16 as 0. NOTE: The Intel ICH7 does not + * provide decode down to the word or byte level. + * Bit 1 Reserved. + * Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + * 0 = Disable. + * 1 = Enable the GEN1 I/O range to be forwarded to the LPC + * I/F + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); - /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ - // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + /* GEN2_DEC, LPC Interface Generic Decode Range 2 + * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); - /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ - // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 - // Macbook21: 0x0000 0x0000 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + /* GEN3_DEC, LPC Interface Generic Decode Range 3 + * X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + * Macbook21: 0x0000 0x0000 + */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); /* obsolete, because it writes zeros? */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); - /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ - // X60: 0x0000 0x0000 - // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + /* GEN4_DEC, LPC Interface Generic Decode Range 4 + * X60: 0x0000 0x0000 + * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); } @@ -225,11 +231,9 @@ static void rcba_config(void) /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. + RCBA32(0x3418) |= (1 << 0); /* Required. */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - // RCBA32(0x1e84) = 0x00020001; - // RCBA32(0x1e80) = 0x0000fe01; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ RCBA32(0x1e9c) = 0x000200f0; @@ -241,15 +245,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -283,7 +287,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 06f47cd..def9e5f 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -23,7 +23,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. + /* the lid is open by default. */ gnvs->lids = 1; gnvs->tcrt = 100;

1 0

New patch to review for coreboot: mainboard/hp: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16915 -gerrit commit 1a488d6f6592969b8133ef41c1a4dbff04921ad5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 12:51:08 2016 +0200 mainboard/hp: Use C89 comments style & remove commented code Change-Id: I6a38b923a1a2e701cae31d3a6eeacb0eec3e581e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/hp/abm/BiosCallOuts.c | 2 +- src/mainboard/hp/abm/OptionsIds.h | 10 -- src/mainboard/hp/abm/buildOpts.c | 147 +++++---------------- src/mainboard/hp/abm/mptable.c | 4 - src/mainboard/hp/abm/romstage.c | 6 +- src/mainboard/hp/dl145_g1/acpi_tables.c | 47 ------- src/mainboard/hp/dl145_g1/fadt.c | 49 ++----- src/mainboard/hp/dl145_g1/get_bus_conf.c | 26 +--- src/mainboard/hp/dl145_g1/irq_tables.c | 8 +- src/mainboard/hp/dl145_g1/mptable.c | 32 ++--- src/mainboard/hp/dl145_g1/resourcemap.c | 2 - src/mainboard/hp/dl145_g1/romstage.c | 19 +-- src/mainboard/hp/dl145_g3/get_bus_conf.c | 27 ++-- src/mainboard/hp/dl145_g3/irq_tables.c | 35 +++-- src/mainboard/hp/dl145_g3/mptable.c | 37 ++---- src/mainboard/hp/dl145_g3/romstage.c | 45 ++----- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 1 - src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 8 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 14 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 15 +-- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 +- src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 10 -- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 139 ++++++------------- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - 24 files changed, 187 insertions(+), 507 deletions(-) diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 70573be..c0487b5 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -52,7 +52,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index 544ac53..f8977f5 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -48,17 +48,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif /* _OPTION_IDS_H_ */ diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 2f31c5e..e90bca0 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -58,36 +58,22 @@ #endif #endif -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -109,11 +95,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -154,15 +140,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -179,43 +160,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -249,40 +193,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */ /* * Agesa optional capabilities selection. @@ -327,26 +252,26 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL hp_abm_gpio[] = { - { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED - { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID - { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH - { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT - { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L - { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC - { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L - { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT - { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT - { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R + { 45, Function2, GpioOutEnB | Sticky }, /* Signal input APU_SD_LED */ + { 49, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_UID */ + { 50, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_HEALTH */ + { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_FAULT */ + { 57, Function2, GpioOutEnB | Sticky }, /* Signal input SATA_PRSNT_L */ + { 58, Function2, GpioOutEnB | Sticky }, /* Signal i/o APU_HDMI_CEC */ + { 64, Function2, GpioOutEnB | Sticky }, /* Signal input SWC_APU_INT_L */ + { 68, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL1_PRSNT */ + { 69, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL2_PRSNT */ + { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_PROCHOT_L_R */ {-1} }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 6241282..4ff8ea1 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -113,9 +112,6 @@ static void *smp_write_config_table(void *v) outb(0x48, 0xCD6); outb(0xF2, 0xCD7); - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - outb(0xED, 0xCD6); outb(0x17, 0xCD7); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 6e77c57..4d3daed 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -60,14 +60,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz + t32 &= 0xffc0ffff; /* Clr bits [21:19] & [18:16] */ + t32 |= 0x00010000; /* Set bit 16 for 25MHz */ *addr32 = t32; /* Enable Auxiliary OSCOUT1/OSCOUT2 */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; - t32 &= 0xffffff7b; // clear 2, 7 + t32 &= 0xffffff7b; /* clear 2, 7 */ *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index 47e0a3a..d5dd1dc 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -63,53 +63,6 @@ unsigned long acpi_fill_madt(unsigned long current) gsi_base+=4; } } - - /* - int i; - int j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { - unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 - - switch (sysconf.hcid[i]) { - case 1: - d = 7; - break; - case 3: - d = 4; - break; - } - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - */ - } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c index 877cb5b..fd7a807 100644 --- a/src/mainboard/hp/dl145_g1/fadt.c +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -28,12 +28,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x04; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f; */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; @@ -57,47 +57,27 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_base = 16; fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state - fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state - fadt->flush_size = 0; // ignored if wbindv = 1 in flags - fadt->flush_stride = 0; // ignored if wbindv = 1 in flags + fadt->p_lvl2_lat = 101; /* 100 means system doesnt support C2 state */ + fadt->p_lvl3_lat = 1001; /* 1000 means system doesnt support C3 state */ + fadt->flush_size = 0; /* ignored if wbindv = 1 in flags */ + fadt->flush_stride = 0; /* ignored if wbindv = 1 in flags */ fadt->duty_offset = 1; - fadt->duty_width = 3; // 0 means duty cycle not supported - // _alrm value 0 means RTC alarm feature not supported - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work + fadt->duty_width = 3; /* 0 means duty cycle not supported */ + /* _alrm value 0 means RTC alarm feature not supported */ + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042 | - // ACPI_FADT_VGA_NOT_PRESENT | - // ACPI_FADT_MSI_NOT_SUPPORTED| - // ACPI_FADT_NO_PCIE_ASPM_CONTROL| 0; fadt->res2 = 0; fadt->flags = ACPI_FADT_WBINVD | - // ACPI_FADT_WBINVD_FLUSH | ACPI_FADT_C1_SUPPORTED | - // ACPI_FADT_C2_MP_SUPPORTED | - // ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON | - // ACPI_FADT_FIXED_RTC | - // ACPI_FADT_S4_RTC_WAKE | - // ACPI_FADT_32BIT_TIMER | - // ACPI_FADT_DOCKING_SUPPORTED| - // ACPI_FADT_RESET_REGISTER | - // ACPI_FADT_SEALED_CASE | - // ACPI_FADT_HEADLESS | - // ACPI_FADT_SLEEP_TYPE | - // ACPI_FADT_PCI_EXPRESS_WAKE | - // ACPI_FADT_PLATFORM_CLOCK | - // ACPI_FADT_S4_RTC_VALID | - // ACPI_FADT_REMOTE_POWER_ON | - // ACPI_FADT_APIC_CLUSTER | - // ACPI_FADT_APIC_PHYSICAL | 0; fadt->reset_reg.space_id = 1; @@ -146,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -154,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm2_cnt_blk.addrl = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -162,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm_tmr_blk.addrl = pm_base+0x08; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; @@ -170,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe0_blk.addrl = pm_base+0x20; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 64; fadt->x_gpe1_blk.bit_offset = 16; @@ -179,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - } diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index da02095..a52e3ab 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -14,31 +14,17 @@ #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +{ /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; @@ -52,7 +38,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -101,7 +87,7 @@ void get_bus_conf(void) } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index 597acca..88275c8 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -38,7 +38,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t sum = 0; int i; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ /* Align the table to be 16 byte aligned. */ addr += 15; @@ -67,15 +67,12 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//pci bridge +/* pci bridge */ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; pirq_info++; slot_num++; @@ -94,5 +91,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 1a9132e..7b6cece 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR); { device_t dev; @@ -54,31 +54,23 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); - // - // The commented-out lines are auto-detected on my servers. - // -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); - // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); - // Integrated AMD USB + /* The commented-out lines are auto-detected on my servers. */ + +/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Integrated SMBus 2.0 */ + + /* Integrated AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); - // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); - // On board Broadcom nics + /* On board ATI Rage XL */ + + /* On board Broadcom nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); - // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); + /* On board LSI SCSI */ - // PCIX-133 Slot + /* PCIX-133 Slot */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c index 65a4610..8a43841 100644 --- a/src/mainboard/hp/dl145_g1/resourcemap.c +++ b/src/mainboard/hp/dl145_g1/resourcemap.c @@ -120,7 +120,6 @@ static void setup_dl145g1_resource_map(void) PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, @@ -156,7 +155,6 @@ static void setup_dl145g1_resource_map(void) PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index ea0b60c..b295ca7 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -97,11 +97,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - //first node + /* first node */ RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, #endif @@ -123,12 +123,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); - //setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif @@ -150,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -180,22 +179,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) change_i2c_mux(i); } - //dump_spd_registers(&sysinfo->ctrl[0]); - //dump_spd_registers(&sysinfo->ctrl[1]); - //dump_smbus_registers(); - allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl now; + /* It's the time to set ctrl now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); #if CONFIG_SET_FIDVID - init_timer(); // Need to use TMICT to synchronize FID/VID + init_timer(); /* Need to use TMICT to synchronize FID/VID */ #endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - //dump_pci_devices(); - post_cache_as_ram(); } diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index d69e224..0f393d0 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -17,6 +17,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -28,31 +29,19 @@ #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +{ /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; @@ -68,7 +57,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -86,7 +75,7 @@ void get_bus_conf(void) get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */ m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_bcm5780[0] = m->bus_bcm5785_0; @@ -120,7 +109,7 @@ void get_bus_conf(void) } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c index 6ec1fd8..f2937b1 100644 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ b/src/mainboard/hp/dl145_g3/irq_tables.c @@ -20,26 +20,21 @@ static const struct irq_routing_table intel_irq_routing_table = { bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge - {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb - {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr - {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge - {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA - {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge - //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, - {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, - {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */ + {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 legacy southbridge */ + {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 usb */ + {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* VGA Contr */ + {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 pci/pci-x bridge */ + {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom BCM5785 [HT1000] SATA */ + {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5785 [HT1000] PCI/PCI-X Bridge */ + {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */ + {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5715 Gigabit Ethernet */ + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */ + {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* HTX slot */ } }; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 3a784e7..c7ab385 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /*I/O APICs: APIC ID Version State Address*/ + /* I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; int i; @@ -74,15 +74,12 @@ static void *smp_write_config_table(void *v) /* IRQ routing as factory BIOS */ outb(0x01, 0xc00); outb(0x0A, 0xc01); outb(0x17, 0xc00); outb(0x05, 0xc01); -/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */ -/* outb(0x07, 0xc00); outb(0x07, 0xc01); */ outb(0x07, 0xc00); outb(0x0b, 0xc01); outb(0x24, 0xc00); outb(0x05, 0xc01); - //outb(0x00, 0xc00); outb(0x09, 0xc01); outb(0x02, 0xc00); outb(0x0E, 0xc01); - // 8259 registers... + /* 8259 registers... */ outb(0xa0, 0x4d0); outb(0x0e, 0x4d1); @@ -92,16 +89,16 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */ pci_write_config32(dev, 0x64, dword); } - // set GEVENT pins to NO OP + /* set GEVENT pins to NO OP */ outb(0x33, 0xcd6); outb(0x00, 0xcd7); outb(0x34, 0xcd6); outb(0x00, 0xcd7); outb(0x35, 0xcd6); outb(0x00, 0xcd7); } - // hide XIOAPIC PCI configuration space + /* hide XIOAPIC PCI configuration space */ { device_t dev; dev = dev_find_device(0x1166, 0x205, 0); @@ -115,31 +112,26 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); - //SATA -/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ -/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ + /* SATA */ printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); - //USB + /* USB */ printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa); - //VGA + /* VGA */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7); - //PCIE + /* PCIE */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe); - //IDE -// outb(0x02, 0xc00); outb(0x0e, 0xc01); -// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); -// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe); + /* IDE */ - //onboard Broadcom GbE + /* onboard Broadcom GbE */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4); @@ -153,17 +145,17 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts + dword |= (1 << 4); /* enable interrupts */ printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } } -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ +/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa); mptable_lintsrc(mc, bus_isa); - //extended table entries + /* extended table entries */ smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); @@ -174,7 +166,6 @@ static void *smp_write_config_table(void *v) smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); - /* Compute the checksums */ return mptable_finalize(mc); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 1d1195a..af9793e 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -85,28 +85,9 @@ static void setup_early_ipmi_serial() char serial_mux2[]={0x0c << 2,0x12,0x04,0x03}; char serial_mux3[]={0x0c << 2,0x12,0x04,0x07}; -// earlydbg(0x0d); - //set channel access system only - ipmi_request(5,channel_access); -// earlydbg(result); -/* - //Set serial/modem config - result = ipmi_request(6,serialmodem_conf); - earlydbg(result); - - //Set serial mux 1 - result = ipmi_request(4,serial_mux1); - earlydbg(result); - //Set serial mux 2 - result = ipmi_request(4,serial_mux2); - earlydbg(result); - - //Set serial mux 3 - result = ipmi_request(4,serial_mux3); - earlydbg(result); -*/ -// earlydbg(0x0e); + /* set channel access system only */ + ipmi_request(5,channel_access); } #endif @@ -114,10 +95,10 @@ static void setup_early_ipmi_serial() void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // first node + /* first node */ DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // second node + /* second node */ DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; @@ -144,17 +125,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -// setup_early_ipmi_serial(); - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -164,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ bcm5785_early_setup(); #if CONFIG_SET_FIDVID @@ -176,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -187,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); @@ -195,13 +175,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /*It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output + /*do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ - // init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 479e0b6..4286cac 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -28,7 +28,6 @@ void shc4307_init(void) pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); - /* pnp_set_enable(CMOS_DEV, 3); */ pnp_write_config(CMOS_DEV, 0x30, 3); pnp_set_logical_device(KBD_DEV); /* Keyboard */ diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 68c3881..a20cd7b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; /* Here you only need to set value in pci1234 for HT-IO that could be @@ -69,7 +69,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if(get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -88,7 +88,7 @@ void get_bus_conf(void) get_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */ m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff; m->bus_bcm5780[0] = m->bus_bcm5785_0; @@ -122,7 +122,7 @@ void get_bus_conf(void) } } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ apicid_base = 0x10; for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 17e42e4..b7aab80 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) outb(0x03, 0xc00); outb(0x07, 0xc01); outb(0x07, 0xc00); outb(0x05, 0xc01); - // 8259 registers... + /* 8259 registers... */ outb(0xa0, 0x4d0); outb(0x0e, 0x4d1); @@ -89,16 +89,12 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */ pci_write_config32(dev, 0x64, dword); } - // set GEVENT pins to NO OP - /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); - outb(0x34, 0xcd6); outb(0x00, 0xcd7); - outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ } - // hide XIOAPIC PCI configuration space + /* hide XIOAPIC PCI configuration space */ { device_t dev; dev = dev_find_device(0x1166, 0x205, 0); @@ -132,7 +128,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts + dword |= (1 << 4); /* enable interrupts */ printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } @@ -141,7 +137,7 @@ static void *smp_write_config_table(void *v) /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); - //extended table entries + /* extended table entries */ smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 39cd0e3..5a98c23 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -78,11 +78,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr - //first node + /* switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr */ + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; @@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); @@ -172,10 +172,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -198,9 +198,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 87d6eae..231a188 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -122,8 +122,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /*BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /*6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -134,7 +134,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -157,7 +157,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;/*BIT0 | BIT4 |BIT8; */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -186,7 +186,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 48258ca..7763b80 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -65,35 +65,21 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -141,7 +127,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -153,16 +139,10 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. */ +/* If not specified, the values used for the core VRM will be applied */ + #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -172,17 +152,13 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -190,43 +166,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -246,40 +185,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -324,7 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 /* * The GPIO control is not well documented in AGESA, but is in the BKDG @@ -376,9 +314,10 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = { }; #define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 9e63caf..23c0485 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02;

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New patch to review for coreboot: mainboard/gigabyte: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16914 -gerrit commit 8e8b83f47e086b5e48ced76e9a7a00bce7dd75a6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 12:48:42 2016 +0200 mainboard/gigabyte: Use C89 comments style & remove commented code Change-Id: Ib71aa8ff5ebe709b8884aeaabef6e4aa1a401d6d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 4 +- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 94 ++++------------------- src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 24 +++--- src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 4 +- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 6 +- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 32 +++----- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 22 +++--- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 18 ++--- src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 6 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 23 +++--- src/mainboard/gigabyte/m57sli/fanctl.c | 4 - src/mainboard/gigabyte/m57sli/get_bus_conf.c | 32 +++----- src/mainboard/gigabyte/m57sli/irq_tables.c | 6 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/resourcemap.c | 6 +- src/mainboard/gigabyte/m57sli/romstage.c | 39 +++------- src/mainboard/gigabyte/ma785gm/mainboard.c | 3 +- src/mainboard/gigabyte/ma785gm/resourcemap.c | 12 +-- src/mainboard/gigabyte/ma785gm/romstage.c | 25 ++---- src/mainboard/gigabyte/ma785gmt/mainboard.c | 20 +---- src/mainboard/gigabyte/ma785gmt/resourcemap.c | 12 +-- src/mainboard/gigabyte/ma785gmt/romstage.c | 25 ++---- src/mainboard/gigabyte/ma78gm/mainboard.c | 1 - src/mainboard/gigabyte/ma78gm/resourcemap.c | 12 +-- src/mainboard/gigabyte/ma78gm/romstage.c | 25 ++---- 27 files changed, 129 insertions(+), 332 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index 978ce55..2fa4f6f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -52,7 +52,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. + /* the lid is open by default. */ gnvs->lids = 1; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 7b1c506..7dd0a09 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -69,8 +69,8 @@ static void mainboard_init(device_t dev) RCBA32(0x3848) = 0x0000000e; } -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 06fee7e..cc6c196 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -36,19 +36,19 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ - ite_reg_write(dev, 0xEF, 0x7E); // magic - - ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 - ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 - ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port - ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 - ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! - ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! - ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in - ite_reg_write(dev, 0xe9, 0x27); // bus select disable - ite_reg_write(dev, 0xf0, 0x10); // ? - ite_reg_write(dev, 0xf1, 0x42); // ? - ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + ite_reg_write(dev, 0xEF, 0x7E); /* magic */ + + ite_reg_write(dev, 0x25, 0x40); /* gpio pin function -> gp16 */ + ite_reg_write(dev, 0x27, 0x10); /* gpio pin function -> gp34 */ + ite_reg_write(dev, 0x2c, 0x80); /* smbus isolation on parallel port */ + ite_reg_write(dev, 0x62, 0x0a); /* simple iobase 0xa00 */ + ite_reg_write(dev, 0x72, 0x20); /* watchdog timeout clear! */ + ite_reg_write(dev, 0x73, 0x00); /* watchdog timeout clear! */ + ite_reg_write(dev, 0xcb, 0x00); /* simple io set4 direction -> in */ + ite_reg_write(dev, 0xe9, 0x27); /* bus select disable */ + ite_reg_write(dev, 0xf0, 0x10); /* ? */ + ite_reg_write(dev, 0xf1, 0x42); /* ? */ + ite_reg_write(dev, 0xf6, 0x1c); /* hardware monitor alert beep -> gp36(pin12) */ /* EC SIO settings */ ite_reg_write(IT8728F_EC, 0xf1, 0xc0); @@ -63,74 +63,6 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev) void rcba_config(void) { -/* - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); - - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - RCBA32(0x3500) = 0x2000035f; - RCBA32(0x3504) = 0x2000035f; - RCBA32(0x3508) = 0x2000035f; - RCBA32(0x350c) = 0x2000035f; - RCBA32(0x3510) = 0x2000035f; - RCBA32(0x3514) = 0x2000035f; - RCBA32(0x3518) = 0x2000035f; - RCBA32(0x351c) = 0x2000035f; - RCBA32(0x3520) = 0x2000035f; - RCBA32(0x3524) = 0x2000035f; - RCBA32(0x3528) = 0x2000035f; - RCBA32(0x352c) = 0x2000035f; - RCBA32(0x3530) = 0x2000035f; - RCBA32(0x3534) = 0x2000035f; - RCBA32(0x3560) = 0x024c8001; - RCBA32(0x3564) = 0x000024a3; - RCBA32(0x3568) = 0x00040002; - RCBA32(0x356c) = 0x01000050; - RCBA32(0x3570) = 0x02000662; - RCBA32(0x3574) = 0x18000f9f; - RCBA32(0x3578) = 0x1800ff4f; - RCBA32(0x357c) = 0x0001d530; - RCBA32(0x35a0) = 0xc0300c03; - RCBA32(0x35a4) = 0x00241803; - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - outw (0x0000, DEFAULT_PMBASE | 0x003c); - - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; -// RCBA32(0x3418) = 0x1fee1fe1; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -*/ /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17ee1fe1; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c index 978ce55..2fa4f6f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c @@ -52,7 +52,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. + /* the lid is open by default. */ gnvs->lids = 1; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 83a53d0..5a2e469 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -36,19 +36,19 @@ static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ - ite_reg_write(dev, 0xEF, 0x7E); // magic + ite_reg_write(dev, 0xEF, 0x7E); /* magic */ - ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 - ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 - ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port - ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 - ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! - ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! - ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in - ite_reg_write(dev, 0xe9, 0x27); // bus select disable - ite_reg_write(dev, 0xf0, 0x10); // ? - ite_reg_write(dev, 0xf1, 0x42); // ? - ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + ite_reg_write(dev, 0x25, 0x40); /* gpio pin function -> gp16 */ + ite_reg_write(dev, 0x27, 0x10); /* gpio pin function -> gp34 */ + ite_reg_write(dev, 0x2c, 0x80); /* smbus isolation on parallel port */ + ite_reg_write(dev, 0x62, 0x0a); /* simple iobase 0xa00 */ + ite_reg_write(dev, 0x72, 0x20); /* watchdog timeout clear! */ + ite_reg_write(dev, 0x73, 0x00); /* watchdog timeout clear! */ + ite_reg_write(dev, 0xcb, 0x00); /* simple io set4 direction -> in */ + ite_reg_write(dev, 0xe9, 0x27); /* bus select disable */ + ite_reg_write(dev, 0xf0, 0x10); /* ? */ + ite_reg_write(dev, 0xf1, 0x42); /* ? */ + ite_reg_write(dev, 0xf6, 0x1c); /* hardware monitor alert beep -> gp36(pin12) */ /* EC SIO settings */ ite_reg_write(IT8728F_EC, 0xf1, 0xc0); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c index d606582..eddca21 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -19,8 +19,8 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0887, - 0x1458a002, // Subsystem ID - 0x0000000e, // Number of entries + 0x1458a002, /* Subsystem ID */ + 0x0000000e, /* Number of entries */ /* Pin Widget Verb Table */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9..e217d9c 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -89,8 +89,8 @@ static void mb_gpio_init(void) ite_reg_write(EC_DEV, 0xf1, 0x00); ite_reg_write(EC_DEV, 0xf2, 0x0a); ite_reg_write(EC_DEV, 0xf3, 0x80); - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + ite_reg_write(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */ + ite_reg_write(EC_DEV, 0x30, 0x01); /* Enable */ /* IRQ routing */ RCBA32(0x3100) = 0x00002210; @@ -134,7 +134,7 @@ static void ich7_enable_lpc(void) void mainboard_romstage_entry(unsigned long bist) { - // ch0 ch1 + /* ch0 ch1 */ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; /* Disable watchdog timer */ diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 53171c2..496b916 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -27,32 +27,18 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_sis966[8]; //1 +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ +/*busnum is default */ +unsigned char bus_sis966[8]; /*1 */ unsigned apicid_sis966; -unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /*You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +unsigned hcdnx[] = { /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; static unsigned get_bus_conf_done = 0; @@ -67,7 +53,7 @@ void get_bus_conf(void) int i; if (get_bus_conf_done == 1) - return; //do it only once + return; /*do it only once */ get_bus_conf_done = 1; @@ -79,7 +65,7 @@ void get_bus_conf(void) get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */ sbdn = sysconf.sbdn; for (i = 0; i < 8; i++) { @@ -113,7 +99,7 @@ void get_bus_conf(void) } } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c index d1168a7..37a0f7e 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c @@ -45,7 +45,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, pirq_info->rfu = rfu; } -extern unsigned char bus_sis966[8]; //1 +extern unsigned char bus_sis966[8]; /* 1 */ unsigned long write_pirq_routing_table(unsigned long addr) { @@ -59,7 +59,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t sum = 0; int i; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ @@ -138,23 +138,23 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n"); - dev = dev_find_slot(0, PCI_DEVFN(2, 5)); // 5513 (IDE) + dev = dev_find_slot(0, PCI_DEVFN(2, 5)); /* 5513 (IDE) */ pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(3, 0)); // USB 1.1 + dev = dev_find_slot(0, PCI_DEVFN(3, 0)); /* USB 1.1 */ pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(3, 1)); // USB 1.1 + dev = dev_find_slot(0, PCI_DEVFN(3, 1)); /* USB 1.1 */ pci_write_config8(dev, 0x3C, 0x05); - dev = dev_find_slot(0, PCI_DEVFN(3, 3)); // USB 2.0 + dev = dev_find_slot(0, PCI_DEVFN(3, 3)); /* USB 2.0 */ pci_write_config8(dev, 0x3C, 0x07); - dev = dev_find_slot(0, PCI_DEVFN(4, 0)); // 191 (LAN) + dev = dev_find_slot(0, PCI_DEVFN(4, 0)); /* 191 (LAN) */ pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(5, 0)); // 1183 (SATA) + dev = dev_find_slot(0, PCI_DEVFN(5, 0)); /* 1183 (SATA) */ pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(6, 0)); // PCI-E + dev = dev_find_slot(0, PCI_DEVFN(6, 0)); /* PCI-E */ pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(7, 0)); // PCI-E + dev = dev_find_slot(0, PCI_DEVFN(7, 0)); /* PCI-E */ pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(15, 0)); // Azalia + dev = dev_find_slot(0, PCI_DEVFN(15, 0)); /* Azalia */ pci_write_config8(dev, 0x3C, 0x05); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 1544205..6783bbd 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -24,7 +24,7 @@ #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_sis966[8]; //1 +extern unsigned char bus_sis966[8]; /* 1 */ extern unsigned apicid_sis966; @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; @@ -80,13 +80,13 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin)) PCI_INT(0, sbdn+1, 1, 0xa); - PCI_INT(0, sbdn+2, 0, 0x16); // 22 - PCI_INT(0, sbdn+2, 1, 0x17); // 23 - PCI_INT(0, sbdn+6, 1, 0x17); // 23 - PCI_INT(0, sbdn+5, 0, 0x14); // 20 - PCI_INT(0, sbdn+5, 1, 0x17); // 23 - PCI_INT(0, sbdn+5, 2, 0x15); // 21 - PCI_INT(0, sbdn+8, 0, 0x16); // 22 + PCI_INT(0, sbdn+2, 0, 0x16); /* 22 */ + PCI_INT(0, sbdn+2, 1, 0x17); /* 23 */ + PCI_INT(0, sbdn+6, 1, 0x17); /* 23 */ + PCI_INT(0, sbdn+5, 0, 0x14); /* 20 */ + PCI_INT(0, sbdn+5, 1, 0x17); /* 23 */ + PCI_INT(0, sbdn+5, 2, 0x15); /* 21 */ + PCI_INT(0, sbdn+8, 0, 0x16); /* 22 */ for(j = 7; j >= 2; j--) { if(!bus_sis966[j]) continue; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c index 35c54c8..3ca111b 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c @@ -132,7 +132,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -167,7 +166,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -194,7 +192,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -224,7 +221,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -265,7 +261,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ + /* link 0 of CPU 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 337423f..d542bf5 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -100,10 +100,10 @@ static void sio_setup(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 + /* Node 0 */ DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // Node 1 + /* Node 1 */ DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; @@ -136,12 +136,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ + setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ #if CONFIG_SET_FIDVID { @@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -173,25 +173,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); sis_init_stage1(); enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sis_init_stage2(); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */ } diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c index cc0cdca..dca02d2 100644 --- a/src/mainboard/gigabyte/m57sli/fanctl.c +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -32,8 +32,6 @@ static const struct { { 0x51, 0x1c}, /* set the 'zero' voltage for diode type sensor 3 */ { 0x5c, 0x80}, -// { 0x56, 0xe5}, -// { 0x57, 0xe5}, { 0x59, 0xec}, { 0x5c, 0x00}, /* fan1 (controlled by temp3) control parameters */ @@ -41,8 +39,6 @@ static const struct { { 0x60, 0xff}, /* fan start limit */ { 0x61, 0x14}, - /* ???? */ -// { 0x62, 0x00}, /* start PWM */ { 0x63, 0x27}, /* smooth and slope PWM */ diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index 9d13b0c..2b32bc4 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -25,32 +25,18 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_mcp55[8]; //1 +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ +/* busnum is default */ +unsigned char bus_mcp55[8]; /* 1 */ unsigned apicid_mcp55; -unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +unsigned pci1234x[] = { /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; static unsigned get_bus_conf_done = 0; @@ -65,7 +51,7 @@ void get_bus_conf(void) int i; if (get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -77,7 +63,7 @@ void get_bus_conf(void) get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */ sbdn = sysconf.sbdn; for (i = 0; i < 8; i++) { @@ -110,7 +96,7 @@ void get_bus_conf(void) } } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index 4d42d74..cd8663e 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -43,7 +43,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, pirq_info->rfu = rfu; } -extern unsigned char bus_mcp55[8]; //1 +extern unsigned char bus_mcp55[8]; /* 1 */ unsigned long write_pirq_routing_table(unsigned long addr) { @@ -57,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t sum = 0; int i; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ @@ -87,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//pci bridge +/* pci bridge */ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 019a7f5..66021ea 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -23,7 +23,7 @@ #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_mcp55[8]; //1 +extern unsigned char bus_mcp55[8]; /* 1 */ extern unsigned apicid_mcp55; diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c index 35c54c8..3ca111b 100644 --- a/src/mainboard/gigabyte/m57sli/resourcemap.c +++ b/src/mainboard/gigabyte/m57sli/resourcemap.c @@ -132,7 +132,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -167,7 +166,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -194,7 +192,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -224,7 +221,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -265,7 +261,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ + /* link 0 of CPU 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b12b12c..81659fa 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -91,10 +91,10 @@ static void sio_setup(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 + /* Node 0 */ DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // Node 1 + /* Node 1 */ DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; @@ -113,23 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); -#if 0 - uint8_t tmp = 0; - pnp_enter_ext_func_mode(SERIAL_DEV); - /* The following line will set CLKIN to 24 MHz, external */ - pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); - tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); - /* Is serial flash enabled? Then enable writing to serial flash. */ - if (tmp & 0x0e) { - pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); - pnp_set_logical_device(GPIO_DEV); - /* Set Serial Flash interface to 0x0820 */ - pnp_write_config(GPIO_DEV, 0x64, 0x08); - pnp_write_config(GPIO_DEV, 0x65, 0x20); - } - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); -#endif ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -143,12 +126,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ + setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -158,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ #if CONFIG_SET_FIDVID { @@ -169,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -177,20 +160,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); // Need to use TMICT to synchronize FID/VID + init_timer(); /* Need to use TMICT to synchronize FID/VID */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -199,5 +182,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */ } diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index ac53c43..82bdf63 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -92,7 +92,7 @@ int is_dev3_present(void) static void set_gpio40_gfx(void) { u8 byte; -// u16 word; +/* u16 word; */ u32 dword; device_t sm_dev; /* disable the GPIO40 as CLKREQ2# function */ @@ -135,7 +135,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ set_gpio40_gfx(); } diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 06eaa8c..ca2f4c7 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ #include <stdint.h> #include <string.h> @@ -99,12 +97,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -163,10 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -193,8 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -205,21 +199,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 187c30e..43cbe52 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -122,7 +122,7 @@ int is_dev3_present(void) static void set_gpio40_gfx(void) { u8 byte; -// u16 word; +/* u16 word; */ u32 dword; device_t sm_dev; /* disable the GPIO40 as CLKREQ2# function */ @@ -143,8 +143,8 @@ static void set_gpio40_gfx(void) /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ + /* if the dev3 is present, set the gfx to 2x8 lanes*/ + /* otherwise set the gfx to 1x16 lanes*/ if(is_dev3_present()){ printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); @@ -221,19 +221,6 @@ static void set_thermal_config(void) byte &= 0xf3; pm_iowrite(0x3c, byte); - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ } /************************************************* @@ -245,7 +232,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ set_thermal_config(); set_gpio40_gfx(); } diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 860b1f1..2496148 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ #include <stdint.h> #include <string.h> @@ -99,12 +97,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -163,10 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -193,8 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -205,21 +199,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 505ba3e..c0dda77 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -72,7 +72,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9efda6f..039470e 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -107,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +164,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +194,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +204,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /**

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New patch to review for coreboot: mainboard/apple: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Oct '16

07 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16913 -gerrit commit 5a2b00c0b412fe619bccfe13a44c64151e03bf7f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 12:46:28 2016 +0200 mainboard/apple: Use C89 comments style & remove commented code Change-Id: I81c32c618627507cc3a83f60f565a73e5e6d7a13 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/apple/macbook21/romstage.c | 199 ++++++++++++++++--------------- src/mainboard/apple/macbookair4_2/gnvs.c | 2 +- 2 files changed, 102 insertions(+), 99 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 695f1cd..ae8b45a 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -89,110 +89,115 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // I/O Decode Ranges - // X60: 0x0210 == 00000010 00010000 - // Macbook21: 0x0010 == 00000000 00010000 - // Bit 9:8 LPT Decode Range. This field determines which range to - // decode for the LPT Port. - // 00 = 378h - 37Fh and 778h - 77Fh - // 10 = 3BCh - 3BEh and 7BCh - 7BEh + /* I/O Decode Ranges + * X60: 0x0210 == 00000010 00010000 + * Macbook21: 0x0010 == 00000000 00010000 + * Bit 9:8 LPT Decode Range. This field determines which range to + * decode for the LPT Port. + * 00 = 378h - 37Fh and 778h - 77Fh + * 10 = 3BCh - 3BEh and 7BCh - 7BEh + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // LPC_EN--LPC I/F Enables Register - // X60: 0x1f0d == 00011111 00001101 - // Macbook21: 0x3807 == 00111000 00000111 - // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - // to the LPC interface. This range is used for - // Super I/O devices. - // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 62h and 66h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 60h and 64h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 208h to 20Fh - // to the LPC interface. This range is used for a gameport. - // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 200h to 207h - // to the LPC interface. This range is used for a gameport. - // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - // 0 = Disable. - // 1 = Enables the decoding of the FDD range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 12). - // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - // 0 = Disable. - // 1 = Enables the decoding of the LPT range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 9:8). - // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMB range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 6:4). - // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMA range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 3:2). + /* LPC_EN--LPC I/F Enables Register + * X60: 0x1f0d == 00011111 00001101 + * Macbook21: 0x3807 == 00111000 00000111 + * Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + * to the LPC interface. This range is used for + * Super I/O devices. + * Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 62h and 66h + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 60h and 64h + * to the LPC interface. This range is used for a + * microcontroller. + * Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 208h to 20Fh + * to the LPC interface. This range is used for a gameport. + * Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + * 0 = Disable. + * 1 = Enables the decoding of the I/O locations 200h to 207h + * to the LPC interface. This range is used for a gameport. + * Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + * 0 = Disable. + * 1 = Enables the decoding of the FDD range to the LPC + * interface. This range is selected in the LPC_FDD/LPT + * Decode Range Register (D31:F0:80h, bit 12). + * Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + * 0 = Disable. + * 1 = Enables the decoding of the LPT range to the LPC + * interface. This range is selected in the LPC_FDD/LPT + * Decode Range Register (D31:F0:80h, bit 9:8). + * Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + * 0 = Disable. + * 1 = Enables the decoding of the COMB range to the LPC + * interface. This range is selected in the LPC_COM Decode + * Range Register (D31:F0:80h, bits 6:4). + * Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + * 0 = Disable. + * 1 = Enables the decoding of the COMA range to the LPC + * interface. This range is selected in the LPC_COM Decode + * Range Register (D31:F0:80h, bits 3:2). + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); - /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ - // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - // Bit 31:24 Reserved. - // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - // bit position indicates that any value in the corresponding - // address bit in a received cycle will be treated as a - // match. The corresponding bit in the Address field, below, - // is ignored. The mask is only provided for the lower 6 bits - // of the DWord address, allowing for decoding blocks up to - // 256 bytes in size. - // Bit 17:16 Reserved. - // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - // address is aligned on a 128-byte boundary, and must have - // address lines 31:16 as 0. NOTE: The Intel ICH7 does not - // provide decode down to the word or byte level. - // Bit 1 Reserved. - // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - // 0 = Disable. - // 1 = Enable the GEN1 I/O range to be forwarded to the LPC - // I/F + /* GEN1_DEC, LPC Interface Generic Decode Range 1 + * X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + * Bit 31:24 Reserved. + * Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + * bit position indicates that any value in the corresponding + * address bit in a received cycle will be treated as a + * match. The corresponding bit in the Address field, below, + * is ignored. The mask is only provided for the lower 6 bits + * of the DWord address, allowing for decoding blocks up to + * 256 bytes in size. + * Bit 17:16 Reserved. + * Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + * address is aligned on a 128-byte boundary, and must have + * address lines 31:16 as 0. NOTE: The Intel ICH7 does not + * provide decode down to the word or byte level. + * Bit 1 Reserved. + * Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + * 0 = Disable. + * 1 = Enable the GEN1 I/O range to be forwarded to the LPC + */ I/F pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); - /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ - // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + /* GEN2_DEC, LPC Interface Generic Decode Range 2 + * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); - /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ - // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 - // Macbook21: 0x0000 0x0000 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + /* GEN3_DEC, LPC Interface Generic Decode Range 3 + * X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + * Macbook21: 0x0000 0x0000 + */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); /* obsolete, because it writes zeros? */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); - /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ - // X60: 0x0000 0x0000 - // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + /* GEN4_DEC, LPC Interface Generic Decode Range 4 + * X60: 0x0000 0x0000 + * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); } @@ -225,11 +230,9 @@ static void rcba_config(void) /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. + RCBA32(0x3418) |= (1 << 0); /* Required. */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - // RCBA32(0x1e84) = 0x00020001; - // RCBA32(0x1e80) = 0x0000fe01; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ RCBA32(0x1e9c) = 0x000200f0; @@ -241,15 +244,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -283,7 +286,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 06f47cd..def9e5f 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -23,7 +23,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. + /* the lid is open by default. */ gnvs->lids = 1; gnvs->tcrt = 100;

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Patch set updated for coreboot: soc/intel/apollolake: Set package power limits for RAPL registers
by Sumeet R Pawnikar 07 Oct '16

07 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16884 -gerrit commit a7a3117b9cdbae07a8446c98f82e02fd90c6343b Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Sep 27 23:18:35 2016 +0530 soc/intel/apollolake: Set package power limits for RAPL registers This patch sets the package power limit values in RAPL MSR and MMIO registers after boot and suspend-resume cycle. BUG=chrome-os-partner:56922 TEST=Built, booted and tested these package power limits before and after boot and suspend-resume cycle. Before suspend and after resume, read RAPL MSR and MMIO register. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 130 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 9 ++ 2 files changed, 139 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eeac6ce..993f010 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -38,6 +38,39 @@ #include "chip.h" +#define MAX_NUM_ENTRY (sizeof(lookup_table) / sizeof(lookup_table[0])) + +static const struct { + uint8_t time; + uint8_t msr_val; +} lookup_table[] = { + {0, 0}, + {1, 0x0a}, + {2, 0x0b}, + {3, 0x4b}, + {4, 0x0c}, + {5, 0x2c}, + {6, 0x4c}, + {7, 0x6c}, + {8, 0x0d}, + {10, 0x2d}, + {12, 0x4d}, + {14, 0x6d}, + {16, 0x0e}, + {20, 0x2e}, + {24, 0x4e}, + {28, 0x6e}, + {32, 0x0f}, + {40, 0x2f}, + {48, 0x4f}, + {56, 0x6f}, + {64, 0x10}, + {80, 0x30}, + {96, 0x50}, + {112, 0x70}, + {128, 0x11} +}; + static void *vbt; static struct region_device vbt_rdev; @@ -193,6 +226,100 @@ static void pcie_override_devicetree_after_silicon_init(void) pcie_update_device_tree(PCIEB0_DEVFN, 2); } +static uint8_t find_lookup_time(u8 in_msr) +{ + uint8_t index = 0; + + while (in_msr != lookup_table[index].msr_val && index < MAX_NUM_ENTRY) + index++; + + /* + * If some value is not part of this lookup table, + * assinging the default time value for PL1. + */ + if (index >= MAX_NUM_ENTRY) + return MB_POWER_LIMIT1_TIME_DEFAULT; + + return lookup_table[index].time; +} + +static uint8_t find_lookup_msr(u8 in_time) +{ + uint8_t index = 0; + + while (in_time != lookup_table[index].time && index < MAX_NUM_ENTRY) + index++; + + /* + * If some value is not part of this lookup table, + * assinging the default time value for PL1. + */ + if (index >= MAX_NUM_ENTRY) + return find_lookup_msr(MB_POWER_LIMIT1_TIME_DEFAULT); + + return lookup_table[index].msr_val; +} + +/* Configure package power limits */ +static void set_power_limits(u8 power_limit_1_time) +{ + uint32_t *rapl_mmio_reg; + msr_t rapl_msr_reg, limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time; + uint8_t power_limit_1_val; + + rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); + + if (power_limit_1_time > MAX_NUM_ENTRY) + power_limit_1_time = MB_POWER_LIMIT1_TIME_DEFAULT; + + /* Get units */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (rapl_msr_reg.lo & 0xf); + + /* Get power defaults for this SKU */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); + tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; + min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; + max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + max_time = (rapl_msr_reg.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (find_lookup_time(max_time) > power_limit_1_time) + power_limit_1_time = find_lookup_time(max_time); + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = find_lookup_msr(power_limit_1_time); + + /* Set long term power limit to TDP */ + limit.lo = tdp & PKG_POWER_LIMIT_MASK; + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit PL2 to 15W */ + limit.hi = 0xf00 & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Program package power limits in RAPL MSR */ + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Setting RAPL MMIO register for Power limits */ + write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); + write32(rapl_mmio_reg + 1, limit.hi); +} + static void rapl_update(void) { uint32_t *rapl_reg; @@ -241,6 +368,9 @@ static void soc_init(void *data) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + /* Set RAPL MSR for Package power limits*/ + set_power_limits(MB_POWER_LIMIT1_TIME_DEFAULT); + /* Update RAPL package power limit */ rapl_update(); } diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..0195249 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -39,6 +39,15 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L2_DISABLE (1 << 2) #define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +/* For Mobile, default PL1 time window value is 28 seconds */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 28 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f

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Patch merged into coreboot/master: mainboard/google/reef: add pyro variant.
by gerrit＠coreboot.org 07 Oct '16

07 Oct '16

the following patch was just integrated into master: commit 0b1a90da76cc1e81b6a1a43a8ffc2ddd97b84377 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google/reef: add pyro variant. Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16855 for details. -gerrit

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New patch to review for coreboot: gitconfig: Allow user name and email to be in includes
by Daisuke Nojiri 06 Oct '16

06 Oct '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16912 -gerrit commit 8c02db4345928901708e44d7dbca65f6b31239dc Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 6 13:21:17 2016 -0700 gitconfig: Allow user name and email to be in includes This patch adds '--includes' option to 'git config --global' command to allow user name and email to be defined in a file included from the global gitconfig (~/.gitconfig) file. BUG=none BRANCH=none TEST=make gitconfig with ~/.gitconfig including another file which defines user.name and email. Change-Id: I4fe61078b143c3a2e26b0be69c3ca8e6f069d8b0 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index d6c7476..24f99cb 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -573,7 +573,7 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master git config alias.sup '!git submodule update --remote --rebase && git submodule update --init --checkout' git config alias.sup-destroy '!git submodule deinit --force "$$(git rev-parse --show-toplevel)"; git submodule init && git submodule update --checkout' - (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) + (git config --global --includes user.name >/dev/null && git config --global --includes user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) include util/crossgcc/Makefile.inc

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coreboot-gerrit October 2016