coreboot-gerrit September 2015

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Patch set updated for coreboot: pcengines/apu1: Add CMOS/NVRAM support
by Maxime de Roucy 30 Sep '15

30 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730 -gerrit commit e93a8f5531a1ce0eff56de6b6b664d8c65099759 Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:45:35 2015 +0200 pcengines/apu1: Add CMOS/NVRAM support Inspired by the Sage source code (itself from coreboot). Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 2 ++ src/mainboard/pcengines/apu1/cmos.default | 5 ++++ src/mainboard/pcengines/apu1/cmos.layout | 46 +++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index b1b19c9..7ea1821 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default new file mode 100644 index 0000000..bca3115 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -0,0 +1,5 @@ +last_boot=Fallback +boot_option=Fallback +multi_core=Enable +debug_level=Emerg +baud_rate=115200 diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout new file mode 100644 index 0000000..0cf145f --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -0,0 +1,46 @@ +entries + +# <start-bit> <bit-length> <config> <config-id> <parameter-name> +0 384 r 0 reserved_memory +384 4 r 0 reboot_bits +388 1 e 2 last_boot +# leave 3 bits to make checksummed area start byte-aligned +392 1 e 2 boot_option +393 1 e 1 multi_core +394 3 e 3 baud_rate +397 4 e 4 debug_level +# leave 7 bits to make checksummed area end byte-aligned +408 16 h 0 check_sum + +enumerations + +#<config-id> <value> <label> +## for multi_core +1 0 Enable +1 1 Disable +## for last_boot, boot_option +2 0 Fallback +2 1 Normal +## for baud_rate +3 0 115200 +3 1 57600 +3 2 38400 +3 3 19200 +3 4 9600 +3 5 4800 +3 6 2400 +3 7 1200 +## for debug_level +4 0 Emerg +4 1 Alert +4 2 Crit +4 3 Err +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +checksums + +checksum 392 407 408

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Patch set updated for coreboot: pcengines/apu1: Add CMOS/NVRAM support
by Maxime de Roucy 30 Sep '15

30 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730 -gerrit commit 956be703463a66bd4d153c31888a67ba7dd8cc5c Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:45:35 2015 +0200 pcengines/apu1: Add CMOS/NVRAM support Inspired by the Sage source code (itself from coreboot). Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 2 ++ src/mainboard/pcengines/apu1/cmos.default | 5 ++++ src/mainboard/pcengines/apu1/cmos.layout | 44 +++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index b1b19c9..7ea1821 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default new file mode 100644 index 0000000..bca3115 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -0,0 +1,5 @@ +last_boot=Fallback +boot_option=Fallback +multi_core=Enable +debug_level=Emerg +baud_rate=115200 diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout new file mode 100644 index 0000000..6172f35 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -0,0 +1,44 @@ +entries + +# <start-bit> <bit-length> <config> <config-id> <parameter-name> +0 384 r 0 reserved_memory +384 4 r 0 reboot_bits +388 1 e 2 last_boot +389 1 e 2 boot_option +390 1 e 1 multi_core +391 3 e 3 baud_rate +394 4 e 4 debug_level +398 16 h 0 check_sum + +enumerations + +#<config-id> <value> <label> +## for multi_core +1 0 Enable +1 1 Disable +## for last_boot, boot_option +2 0 Fallback +2 1 Normal +## for baud_rate +3 0 115200 +3 1 57600 +3 2 38400 +3 3 19200 +3 4 9600 +3 5 4800 +3 6 2400 +3 7 1200 +## for debug_level +4 0 Emerg +4 1 Alert +4 2 Crit +4 3 Err +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +checksums + +checksum 389 397 398

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Patch merged into coreboot/master: chromeos: vboot-related functions move to common vboot code
by gerrit＠coreboot.org 30 Sep '15

30 Sep '15

the following patch was just integrated into master: commit 115360fdb36be77e86dfa1208f3c1e3dca649685 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:41:14 2015 +0200 chromeos: vboot-related functions move to common vboot code This moves a few vboot-prefixed functions that were defined in chromeos.c to vboot_common.c, since those are only relevant to vboot and depend on the vboot handoff data. This allows more separation between CONFIG_CHROMEOS and what CONFIG_CHROMEOS selects, so that each separate option (such as CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately. Thus, the actual definitions of these functions will only be declared when CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling vboot_skip_display_init in bootmode was also adapted. Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11497 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11497 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp1.0: Get size of microcode during build time
by gerrit＠coreboot.org 29 Sep '15

29 Sep '15

the following patch was just integrated into master: commit c947fee4791a8274ebb9128c43b0052d5cabe1b4 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11709 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11709 for details. -gerrit

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New patch to review for coreboot: Add EM100 'hyper term' spi console support in ramstage & smm
by Martin Roth 29 Sep '15

29 Sep '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11743 -gerrit commit cb6af20fab9ab254b673a41334b8677919fc1d21 Author: Martin Roth <martinroth(a)google.com> Date: Mon Sep 28 15:27:24 2015 -0600 Add EM100 'hyper term' spi console support in ramstage & smm The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 1 + src/console/Kconfig | 8 ++++ src/console/console.c | 3 ++ src/drivers/spi/Kconfig | 4 ++ src/drivers/spi/Makefile.inc | 5 +++ src/drivers/spi/spiconsole.c | 71 ++++++++++++++++++++++++++++++++ src/include/console/spi.h | 72 +++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 + src/southbridge/intel/lynxpoint/Kconfig | 1 + 12 files changed, 169 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 2c75750..868ed08 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -777,6 +777,7 @@ config DEBUG_SMI bool "Output verbose SMI debug messages" default n depends on HAVE_SMI_HANDLER + select SPI_FLASH_SMM if SPI_CONSOLE help This option enables additional SMI related debug messages. diff --git a/src/console/Kconfig b/src/console/Kconfig index 7d6fa0e..d9a5521 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -211,6 +211,14 @@ config CONSOLE_QEMU_DEBUGCON_PORT depends on CONSOLE_QEMU_DEBUGCON default 0x402 +config SPI_CONSOLE + bool "SPI debug console output" + depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH + help + Enable support for the debug console on the dediprog EM100Pro. + This is currently working only in ramstage due to how the spi + drivers are written. + choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 diff --git a/src/console/console.c b/src/console/console.c index 00c0f1c..855de64 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,6 +24,7 @@ #include <console/streams.h> #include <console/uart.h> #include <console/usb.h> +#include <console/spi.h> #include <rules.h> void console_hw_init(void) @@ -35,6 +36,7 @@ void console_hw_init(void) __uart_init(); __ne2k_init(); __usbdebug_init(); + __spiconsole_init(); } void console_tx_byte(unsigned char byte) @@ -54,6 +56,7 @@ void console_tx_byte(unsigned char byte) __uart_tx_byte(byte); __ne2k_tx_byte(byte); __usb_tx_byte(byte); + __spiconsole_tx_byte(byte); } void console_tx_flush(void) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 4052bb4..dedb88f 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -137,3 +137,7 @@ config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B to the chip on MOSI and data is received on both MOSI and MISO. endif # SPI_FLASH + +config HAVE_SPI_CONSOLE_SUPPORT + def_bool n + diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index ade34a2..6697c70 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -1,5 +1,10 @@ # SPI flash driver interface +ifeq ($(CONFIG_SPI_CONSOLE),y) +ramstage-y += spiconsole.c +smm-$(CONFIG_DEBUG_SMI) += spiconsole.c +endif + ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y) bootblock-y += spi_flash.c bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c new file mode 100644 index 0000000..39a574c --- /dev/null +++ b/src/drivers/spi/spiconsole.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <console/spi.h> + +void spiconsole_init(void) { + spi_init(); + return; +} + +/* + * The EM100 'hyper terminal' specification defines a header of 9 characters. + * Because of this, devices with a spi_crop_chunk of less than 10 characters + * can't be supported by this standard. + * + * To add support in romstage, the static struct here and the ones used by + * spi_xfer will need to be modified - removed, or mapped into cbmem. + * + * Because the Dediprog software expects strings, not single characters, and + * because of the header overhead, this builds up a buffer to send. + */ +void spiconsole_tx_byte(unsigned char c) { + static struct em100_msg msg = { + .header.spi_command = EM100_DEDICATED_CMD, + .header.em100_command = EM100_UFIFO_CMD, + .header.msg_signature = EM100_MSG_SIGNATURE, + .header.msg_type = EM100_MSG_ASCII, + .header.msg_length = 0 + }; + + /* Verify the spi buffer is big enough to send even a single byte */ + if (spi_crop_chunk(0,MAX_MSG_LENGTH) < + sizeof(struct em100_msg_header) + 1) + return; + + msg.data[msg.header.msg_length] = c; + msg.header.msg_length++; + + /* Send the data on newline or when the max spi length is reached */ + if (c == '\n' || (sizeof(struct em100_msg_header) + + msg.header.msg_length == spi_crop_chunk(0, + MAX_MSG_LENGTH))) { + struct spi_slave spi = {.rw = SPI_READ_FLAG}; + + spi_xfer(&spi, &msg, sizeof(struct em100_msg_header) + + msg.header.msg_length, NULL, 0); + + msg.header.msg_length = 0; + } + + return; +} + diff --git a/src/include/console/spi.h b/src/include/console/spi.h new file mode 100644 index 0000000..c47fec5 --- /dev/null +++ b/src/include/console/spi.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef CONSOLE_SPI_H +#define CONSOLE_SPI_H 1 + +#include <rules.h> +#include <stdint.h> + +void spiconsole_init(void); +void spiconsole_tx_byte(unsigned char c); + +#define __CONSOLE_SPI_ENABLE__ CONFIG_SPI_CONSOLE && \ + (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + +#if __CONSOLE_SPI_ENABLE__ +static inline void __spiconsole_init(void) { spiconsole_init(); } +static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); } +#else +static inline void __spiconsole_init(void) {} +static inline void __spiconsole_tx_byte(u8 data) {} +#endif /* __CONSOLE_SPI_ENABLE__ */ + +#define MAX_MSG_LENGTH 128 + +#define EM100_DEDICATED_CMD 0x11 +#define EM100_UFIFO_CMD 0xC0 +#define EM100_MSG_SIGNATURE 0x47364440 + +enum em100_message_types { + EM100_MSG_CHECKPOINT_1B = 0x01, + EM100_MSG_CHECKPOINT_2B, + EM100_MSG_CHECKPOINT_4B, + EM100_MSG_HEX, + EM100_MSG_ASCII, + EM100_MSG_TIMESTAMP, + EM100_MSG_LOOKUP +}; + +struct em100_msg_header { + uint8_t spi_command; + uint8_t reserved; + uint8_t em100_command; + uint32_t msg_signature; + uint8_t msg_type; + uint8_t msg_length; +} __attribute__ ((packed)); + +struct em100_msg { + struct em100_msg_header header; + char data[MAX_MSG_LENGTH]; +} __attribute__ ((packed)); + + + +#endif /* CONSOLE_SPI_H */ diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 921f568..8de32de 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f76b9b2..5a41056 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6561fe2..33644e8 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index d51a238..cc09e1f 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config SOC_INTEL_FSP_BAYTRAIL_MD bool diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 3c8ae11..3221cff 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config INTEL_LYNXPOINT_LP bool

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New patch to review for coreboot: x86: prepare cache-as-ram to allow multiple stages
by Aaron Durbin 29 Sep '15

29 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11740 -gerrit commit aa3e6ab0b12ce7b6fee96c8655d81fa682fa2c8f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 24 12:18:07 2015 -0500 x86: prepare cache-as-ram to allow multiple stages In order to do a verification of romstage on x86 one needs to run verstage which verifies romstage (and the memory init code). However, x86 doesn't have SRAM like every other modern SoC so managing the cache-as-ram region is especially critical. First move all of the "shared" objects to the beginning of the .car.data section. This change then ensures that each stage using car.ld to link has the same consistent view of the addresses of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can be unique per stage. However, these variables are expected to have a value of zero at the start of each stage. In order to allow a stage to provide those semantics outside of the initial cache-as-arm setup routine add _car_global_start and _car_global_end symbols. Those symbols can be used to clear the CAR_GLOBALs for that stage. Note that the timestamp region can't be moved out similarly to the pre-ram cbmem console because the object storage of the timestamp cache is used *after* cache-as-ram is torn down to indicate if the cache should be used or not. Therefore, that timestamp needs to migrated to ram. A logic change in src/lib/timestamp.c could alleviate this requirement, but that task wasn't tackled in this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/car.ld | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c30c802..5da9dcf 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -22,15 +22,29 @@ /* This file is included inside a SECTIONS block */ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { + /* The pre-ram cbmem console as well as the timestamp region are fixed + * in size. Therefore place them at the beginning .car.data section + * so that multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) _car_data_start = .; + /* The timestamp implementation relies on this storage to be around + * after migration. One of the fields indicates not to use it as the + * backing store once cbmem comes online. Therefore, this data needs + * to reside in the migrated area (between _car_data_start and + * _car_data_end). */ #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) TIMESTAMP(., 0x100) #endif + /* _car_global_start and _car_global_end provide symbols to per-stage + * variables that are not shared like the timestamp and the pre-ram + * cbmem console. This is useful for clearing this area on a per-stage + * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ + _car_global_start = .; *(.car.global_data); . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _car_global_end = .; _car_data_end = .; - - PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage @@ -48,4 +62,4 @@ *(.sbss.*) } -_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); +_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");

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New patch to review for coreboot: x86: provide common macro for linking early stages
by Aaron Durbin 29 Sep '15

29 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11739 -gerrit commit 2fe6e8dd907fb0019b41a4e8f2e9d12ca979cb13 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 29 14:54:25 2015 -0500 x86: provide common macro for linking early stages In order to support verstage on x86 one needs to link verstage like romstage since it needs all the cache-as-ram goodies. Therefore, provide a macro that one can invoke that provides the necessary recipes for linking that particular stage in such an environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I12f4872df09fff6715829de68fc374e230350c2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 49 ++++++++++++++++++++++++------------------- src/arch/x86/assembly_entry.S | 37 ++++++++++++++++++++++++++++++++ src/arch/x86/romstage.S | 37 -------------------------------- 3 files changed, 65 insertions(+), 58 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1779099..f16edcd 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -115,27 +115,44 @@ endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### -# romstage +# common support for early assembly includes ############################################################################### -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) - -romstage-y += memlayout.ld - # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them # into a single generated file. crt0s = $(cpu_incs-y) -$(objgenerated)/romstage.inc: $$(crt0s) +$(objgenerated)/assembly.inc: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ +define early_x86_stage +# $1 stage name +# $2 oformat +$(1)-y += memlayout.ld # Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated romstage.inc is a proper +# the right order. Make sure the auto generated assembly.inc is a proper # dependency. -romstage-y += romstage.S -$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc +$(1)-y += assembly_entry.S +$$(obj)/arch/x86/assembly_entry.$(1).o: $(objgenerated)/assembly.inc + +$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) + @printf " LINK $$(subst $$(obj)/,,$$(@))\n" + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $$(obj)/arch/x86/memlayout.$(1).ld --oformat $(2) + LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders 2>&1 | \ + grep -v "Empty loadable segment detected" && \ + $$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders | grep -q ""; if [ $$$$? -eq 0 ]; then \ + echo "Forbidden global variables in "$(1)":"; \ + $$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders; false; \ + else true; fi +endef + +############################################################################### +# romstage +############################################################################### + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) ifneq ($(CONFIG_ROMCC),y) @@ -180,21 +197,11 @@ endif romstage-libs ?= ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) -romstage-oformat=elf32-i386 +$(eval $(call early_x86_stage,romstage,elf32-i386)) else -romstage-oformat=elf64-x86-64 +$(eval $(call early_x86_stage,romstage,elf64-x86-64)) endif -$(objcbfs)/romstage.debug: $$(romstage-objs) $$(romstage-libs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(obj)/arch/x86/memlayout.romstage.ld --oformat $(romstage-oformat) - LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \ - grep -v "Empty loadable segment detected" && \ - if [ -n "`$(NM_romstage) $(objcbfs)/romstage_null.offenders 2>/dev/null`" ]; then \ - echo "Forbidden global variables in romstage:"; \ - $(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \ - else true; fi - # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S new file mode 100644 index 0000000..c23d177 --- /dev/null +++ b/src/arch/x86/assembly_entry.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/assembly.inc> diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S deleted file mode 100644 index b19b954..0000000 --- a/src/arch/x86/romstage.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The romstage.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/romstage.inc>

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Patch set updated for coreboot: [NOTFORMERGE] src/Kconfig: Enable code coverage by default
by Paul Menzel 29 Sep '15

29 Sep '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11728 -gerrit commit d5e885e86cfe861f98d419fb2fb5f9ac58ecf9c1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Sep 26 13:15:15 2015 +0200 [NOTFORMERGE] src/Kconfig: Enable code coverage by default Change-Id: I3f1860004ccdaa429cfa0b531764e7e9027f0044 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 2c75750..74a032e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -210,7 +210,7 @@ config USE_BLOBS config COVERAGE bool "Code coverage support" depends on COMPILER_GCC - default n + default y help Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. @@ -1028,7 +1028,7 @@ config TRACE config DEBUG_COVERAGE bool "Debug code coverage" - default n + default y depends on COVERAGE help If enabled, the code coverage hooks in coreboot will output some

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New patch to review for coreboot: northbridge/intel/gm45: Fixed FTBFS on Lenovo X200
by Audrey Pearson 29 Sep '15

29 Sep '15

Audrey Pearson (apearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11738 -gerrit commit 953e2a1630fe606edf92c9bfcd5e1eebebe77dea Author: Audrey Pearson <apearson(a)raptorengineeringinc.com> Date: Tue Sep 29 12:36:52 2015 -0500 northbridge/intel/gm45: Fixed FTBFS on Lenovo X200 Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25 Signed-off-by: Audrey Pearson <apearson(a)raptorengineeringinc.com> --- src/northbridge/intel/gm45/gma.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index f29b9b1..ffe3019 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -161,19 +161,19 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hactive = edid.x_resolution; vactive = edid.y_resolution; - right_border = edid.hborder; - bottom_border = edid.vborder; - hpolarity = (edid.phsync == '-'); - vpolarity = (edid.pvsync == '-'); - vsync = edid.vspw; - hsync = edid.hspw; - vblank = edid.vbl; - hblank = edid.hbl; - hfront_porch = edid.hso; - vfront_porch = edid.vso; - - target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock - : (2 * edid.pixel_clock); + right_border = edid.mode.hborder; + bottom_border = edid.mode.vborder; + hpolarity = (edid.mode.phsync == '-'); + vpolarity = (edid.mode.pvsync == '-'); + vsync = edid.mode.vspw; + hsync = edid.mode.hspw; + vblank = edid.mode.vbl; + hblank = edid.mode.hbl; + hfront_porch = edid.mode.hso; + vfront_porch = edid.mode.vso; + + target_frequency = info->gfx.lvds_dual_channel ? edid.mode.pixel_clock + : (2 * edid.mode.pixel_clock); #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_sr_write(1, 1); vga_sr_write(0x2, 0xf); @@ -240,8 +240,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock) / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",

1 0

Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Alexandru Gagniuc 29 Sep '15

29 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit 47d4cb3b2db9944e85038d20b9486ceb7b0293b8 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/fsp1_0/Makefile.inc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..0ec52ec 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,15 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +ifneq ($(cpu_microcode-objs),) +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ + && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ + +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h +endif cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +52,4 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif +

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coreboot-gerrit September 2015