coreboot-gerrit June 2015

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New patch to review for coreboot: AMD binary PI: add southbridge support for fan control
by WANG Siyuan 30 Jun '15

30 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10720 -gerrit commit aa25561cb1e410efd49c791ab68893be24f1e0e4 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:28:17 2015 +0800 AMD binary PI: add southbridge support for fan control 1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is no enough space to add some formwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 11 +++- src/southbridge/amd/pi/hudson/acpi/fch.asl | 6 ++- src/southbridge/amd/pi/hudson/hudson.c | 9 ++++ src/southbridge/amd/pi/hudson/imc.c | 87 ++++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/imc.h | 26 +++++++++ 5 files changed, 136 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 235ce1e..30b5868 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -45,6 +45,10 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +romstage-y += imc.c +ramstage-y += imc.c +endif smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c @@ -100,10 +104,15 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_PSP_OFFSET=131072 +else +HUDSON_PSP_OFFSET=0 +endif HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ $(call int-add,\ $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ + $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(HUDSON_PSP_OFFSET)),\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 else diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index b4d6899..cee721f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -160,9 +160,11 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() +#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) /* TODO: It is unstable. */ - //#include "acpi/AmdImc.asl" /* Hudson IMC function */ - //ITZE() /* enable IMC Fan Control*/ + #include "acpi/AmdImc.asl" /* Hudson IMC function */ + ITZE() /* enable IMC Fan Control*/ +#endif } /* End Method(_SB._INI) */ Method(OSFL, 0){ diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 9b6e6a3..4ef65e9 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -30,6 +30,9 @@ #include "hudson.h" #include "smbus.h" #include "smi.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "fchec.h" +#endif /* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid @@ -130,6 +133,12 @@ static void hudson_init(void *chip_info) static void hudson_final(void *chip_info) { +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + agesawrapper_fchecfancontrolservice(); +#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) + enable_imc_thermal_zone(); +#endif +#endif } struct chip_operations southbridge_amd_pi_hudson_ops = { diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c new file mode 100644 index 0000000..c2c9138 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include "imc.h" +#include <arch/io.h> +#include <device/device.h> +#include <delay.h> +#include "Porting.h" +#include "AGESA.h" +#include <Lib/amdlib.h> +#include <Proc/Fch/Fch.h> +#include <Proc/Fch/Common/FchCommonCfg.h> +#include <Proc/Fch/FchPlatform.h> + +#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) + +void imc_reg_init(void) +{ + u8 reg8; + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); + + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); + + reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); + reg8 &= (UINT8)0x8F; + reg8 |= 0x10; + pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8); +} + +#ifndef __PRE_RAM__ +void enable_imc_thermal_zone(void) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT8 FunNum; + UINT8 regs[9]; + int i; + + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_80; + for (i=0; i<=1; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); + + for (i=2; i<=9; i++) + ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + + /* enable thermal zone 0 */ + regs[2] |= 1; + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_81; + for (i=0; i<=9; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/imc.h b/src/southbridge/amd/pi/hudson/imc.h new file mode 100644 index 0000000..d348319 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/imc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef HUDSON_IMC_H +#define HUDSON_IMC_H + +void imc_reg_init(void); +void enable_imc_thermal_zone(void); + +#endif

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New patch to review for coreboot: AMD binary PI: add vendorcode support for fan control
by WANG Siyuan 30 Jun '15

30 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10719 -gerrit commit 84906ed8b78dd8a83190fa7552860f438d271538 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:14:33 2015 +0800 AMD binary PI: add vendorcode support for fan control Binary PI doesn't provide fan control lib. HwmLateService.c and ImcLib.c are ported from Kabini PI. I have tested on AMD Bettong. The two files work. Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/vendorcode/amd/pi/Lib/imc/HwmLateService.c | 189 +++++++++++++++ src/vendorcode/amd/pi/Lib/imc/ImcLib.c | 314 +++++++++++++++++++++++++ src/vendorcode/amd/pi/Makefile.inc | 3 + 3 files changed, 506 insertions(+) diff --git a/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c b/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c new file mode 100644 index 0000000..f26dfc9 --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c @@ -0,0 +1,189 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE + +/** + * Table for Function Number + * + * + * + * + */ +STATIC UINT8 FunctionNumber[] = +{ + Fun_81, + Fun_83, + Fun_85, + Fun_89, +}; + +/** + * Table for Max Thermal Zone + * + * + * + * + */ +UINT8 MaxZone[] = +{ + 4, + 4, + 4, + 4, +}; + + +/** + * Table for Max Register + * + * + * + * + */ +UINT8 MaxRegister[] = +{ + MSG_REG9, + MSG_REGB, + MSG_REG9, + MSG_REGA, +}; + +/*------------------------------------------------------------------------------- +;Procedure: IsZoneFuncEnable +; +;Description: This routine will check every zone support function with BitMap from user define +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +STATIC BOOLEAN +IsZoneFuncEnable ( + IN UINT16 Flag, + IN UINT8 func, + IN UINT8 Zone + ) +{ + return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); +} + +/*------------------------------------------------------------------------------- +;Procedure: FchECfancontrolservice +; +;Description: This routine service EC fan policy +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +FchECfancontrolservice ( + IN VOID *FchDataPtr + ) +{ + UINT8 ZoneNum; + UINT8 FunNum; + UINT8 RegNum; + UINT8 *CurPoint; + UINT8 FunIndex; + BOOLEAN IsSendEcMsg; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if (!IsImcEnabled (StdHeader)) { + return; //IMC is not enabled + } + + CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); + + for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + if (IsSendEcMsg) { + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); + CurPoint += 1; + } + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number + WaitForEcLDN9MailboxCmdAck (StdHeader); + } else { + CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); + } + } + } + + CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0; + for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + if (IsSendEcMsg) { + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (RegNum == MSG_REG2) { + *CurPoint &= 0xFE; + } + WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); + CurPoint += 1; + } + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number + WaitForEcLDN9MailboxCmdAck (StdHeader); + } else { + CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); + } + } + } +} + diff --git a/src/vendorcode/amd/pi/Lib/imc/ImcLib.c b/src/vendorcode/amd/pi/Lib/imc/ImcLib.c new file mode 100644 index 0000000..5f192f3 --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/imc/ImcLib.c @@ -0,0 +1,314 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IMC lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 87213 $ @e \$Date: 2013-01-30 15:37:54 -0600 (Wed, 30 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE + +/** + * WriteECmsg + * + * + * + * @param[in] Address - Address + * @param[in] OpFlag - Access width + * @param[in] *Value - Out Value pointer + * @param[in] StdHeader + * + */ +VOID +WriteECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + + ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */ + OpFlag = (OpFlag & 0x7f) - 1; + if (OpFlag == 0x02) { + OpFlag = 0x03; + } + + for (Index = 0; Index <= OpFlag; Index++) { + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); + Address++; + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader); + } +} + +/** + * ReadECmsg + * + * + * + * @param[in] Address - Address + * @param[in] OpFlag - Access width + * @param[out] *Value - Out Value pointer + * @param[in] StdHeader + * + */ +VOID +ReadECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + + ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */ + OpFlag = (OpFlag & 0x7f) - 1; + if (OpFlag == 0x02) { + OpFlag = 0x03; + } + + for (Index = 0; Index <= OpFlag; Index++) { + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); + Address++; + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoRead (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader); + } +} + +/** + * WaitForEcLDN9MailboxCmdAck + * + * + * @param[in] StdHeader + * + */ +VOID +WaitForEcLDN9MailboxCmdAck ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Msgdata; + UINT16 Delaytime; + + Msgdata = 0; + + for (Delaytime = 0; Delaytime < 0xFFFF; Delaytime++) { + ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + if ( Msgdata == 0xfa) { + break; + } + + FchStall (5, StdHeader); /// Wait for 1ms + } +} + +/** + * ImcSleep - IMC Sleep. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcSleep ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0xB4; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x96; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} + +/** + * SoftwareDisableImc - Software disable IMC strap + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SoftwareDisableImc ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + UINT8 PortStatusByte; + UINT32 AbValue; + UINT32 ABStrapOverrideReg; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + GetChipSysMode (&PortStatusByte, StdHeader); + + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); + ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader); + + ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue); + ABStrapOverrideReg = AbValue; + ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap + WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg); + + ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); + ValueByte |= BIT1; + WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); + + ValueByte = 06; + LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader); + FchStall (0xffffffff, StdHeader); +} + +/** + * ImcDisableSurebootTimer - IMC Disable Sureboot Timer. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcDisableSurebootTimer ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + ImcWakeup (FchDataPtr); + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x01; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x94; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); + ImcSleep (FchDataPtr); +} + +/** + * ImcWakeup - IMC Wakeup. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcWakeup ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0xB5; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x96; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} + +/** + * ImcIdle - IMC Idle. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcIdle ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x01; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x98; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 42452f2..9353b82 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -103,6 +103,9 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS]) agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) endif +ifeq ($(CONFIG_HUDSON_IMC_FWM),y) +agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c) +endif classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa $(eval $(call create_class_compiler,libagesa,x86_32))

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Patch merged into coreboot/master: libpayload: Swap the macros of VT100_CURSOR_ON and VT100_CURSOR_OFF
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit c8144f96ab8b936d9058c01eb39cb56aa89224ff Author: House Chou <hoare.tw(a)gmail.com> Date: Tue Jun 30 10:10:46 2015 +0800 libpayload: Swap the macros of VT100_CURSOR_ON and VT100_CURSOR_OFF The macros of VT100_CURSOR_ON and VT100_CURSOR_OFF are exchanged Change-Id: Ifdae186ae0503a915d695a9e3fd24bdf65d8428a Signed-off-by: House Chou <hoare.tw(a)gmail.com> Reviewed-on: http://review.coreboot.org/10718 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10718 for details. -gerrit

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Patch merged into coreboot/master: util/scripts: add some support scripts
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit 327036998649c62e11b2fbb5779582c3554203e1 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jun 26 23:23:21 2015 +0200 util/scripts: add some support scripts These scripts were bit-rotting on my box and may be useful for somebody else. no-fsf-addresses.sh removes various FSF addresses from license headers find-unused-kconfig-symbols.sh points out Kconfig variables that may be unused. There are some false positives, but it serves as a starting point. Change-Id: I8ddb5bea5fe87d39eed5f39f32077944b37d0665 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10675 for details. -gerrit

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Patch merged into coreboot/master: lib: add delay.c to bootblock if I2C_TPM driver is enabled
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit e1b832772d0096af8f7c61ab314fba69fb9ef2ba Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 23:11:21 2015 +0200 lib: add delay.c to bootblock if I2C_TPM driver is enabled Change-Id: I752fcc3b8687e4f861c3977322ebb6439f14fac4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10708 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/tpm: push tpm driver from verstage to libverstage
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit 091b4ae7dee500fc9c950c8a3667da4f99758c94 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 23:08:44 2015 +0200 drivers/i2c/tpm: push tpm driver from verstage to libverstage That way it's available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I0665e297f199acd60cff93e1b39812f183115d33 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10707 for details. -gerrit

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Patch merged into coreboot/master: chromeos: push vbnv_* accessors from verstage to libverstage
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit 5f2055d0d9e7f39e0d87e13e186716c6eda6e7a6 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 23:08:44 2015 +0200 chromeos: push vbnv_* accessors from verstage to libverstage That way they're available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I6e59a40761f95a98d96a9b72e3bbcc59caae9b1a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10706 for details. -gerrit

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Patch merged into coreboot/master: google/cosmos: romstage needs the accessor functions for buttons
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit f73f06cb73b1208bc0c4fdf6268349d9ed677f3b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 22:52:26 2015 +0200 google/cosmos: romstage needs the accessor functions for buttons In Chrome OS mode, the romstage tries to interpret the various buttons on the device, so it needs access to the accessor functions. Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10705 for details. -gerrit

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Patch merged into coreboot/master: google/storm: romstage needs the accessor functions for buttons
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit dea4bb676a48338ef272ef68706b7bc7bf1fa448 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 22:52:26 2015 +0200 google/storm: romstage needs the accessor functions for buttons In Chrome OS mode, the romstage tries to interpret the various buttons on the device, so it needs access to the accessor functions. Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10704 for details. -gerrit

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Patch merged into coreboot/master: qualcomm/ipq806x: Fix uart in verstage
by gerrit＠coreboot.org 30 Jun '15

30 Jun '15

the following patch was just integrated into master: commit 3cbbf1907584d831660794d135430f6c6b899231 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 29 22:50:45 2015 +0200 qualcomm/ipq806x: Fix uart in verstage An old Kconfig symbol from Chrome OS survived into the Makefile (but is nowhere declared or used). Use the same symbol as for uart.c in the other stages. Change-Id: I7a6f1b82254e888d6f2d65d6cff87c4d546ec097 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10703 for details. -gerrit

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coreboot-gerrit June 2015