coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

1 participants
1226 discussions

New patch to review for coreboot: google/nyan: remove timestamp leftovers from upstreaming
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10729 -gerrit commit fd59869ea90d86782163ed9d8e37f8429cafc7c7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 14:32:15 2015 +0200 google/nyan: remove timestamp leftovers from upstreaming Initializing timestamps and writing the "start romstage" timestamp already happens earlier. One question to sort out is what to do about the migration into cbmem, but at least this compiles again. Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/nyan/romstage.c | 4 +--- src/mainboard/google/nyan_big/romstage.c | 4 +--- src/mainboard/google/nyan_blaze/romstage.c | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index b9be62b..0f8e947 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -83,11 +83,9 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - early_mainboard_init(); run_ramstage(); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index b9be62b..0f8e947 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -83,11 +83,9 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - early_mainboard_init(); run_ramstage(); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 7ee2c6c..d62e303 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -87,11 +87,9 @@ static void __attribute__((noinline)) romstage(void) hard_reset(); } + /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - early_mainboard_init(); run_ramstage();

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New patch to review for coreboot: drivers/i2c/tpm: move tpm driver around a bit more.
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10728 -gerrit commit 2da161ea82465f4dd6b9bd9ae975785f0478e663 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:39:23 2015 +0200 drivers/i2c/tpm: move tpm driver around a bit more. The many different places to put vboot support in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: Idddb9f5e2ef7bcc273f429d9f432bd37b4573567 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/drivers/i2c/tpm/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/tpm/Makefile.inc b/src/drivers/i2c/tpm/Makefile.inc index 6b003ed..4f5913f 100644 --- a/src/drivers/i2c/tpm/Makefile.inc +++ b/src/drivers/i2c/tpm/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_I2C_TPM) += tis.c tpm.c romstage-$(CONFIG_I2C_TPM) += tis.c tpm.c -libverstage-$(CONFIG_I2C_TPM) += tis.c tpm.c +verstage-$(CONFIG_I2C_TPM) += tis.c tpm.c +bootblock-$(CONFIG_I2C_TPM) += tis.c tpm.c

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New patch to review for coreboot: google/link: implement get_write_protect_state
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10727 -gerrit commit c9308f73fb39342b8985a1e5071711dd04308db3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:49:50 2015 +0200 google/link: implement get_write_protect_state Current vboot wants that function. Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/link/chromeos.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index a020b06..bc8a96a 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -33,22 +33,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - //u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - - if (!gpio_base) - return; - - u32 gp_lvl2 = inl(gpio_base + 0x38); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; /* Write Protect: GPIO57 = PCH_SPI_WP_D */ gpios->gpios[0].port = 57; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = (gp_lvl2 >> (57 - 32)) & 1; + gpios->gpios[0].value = get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); /* Recovery: the "switch" comes from the EC */ @@ -84,6 +75,25 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + //u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + + if (!gpio_base) + return -1; + + u32 gp_lvl2 = inl(gpio_base + 0x38); + + return (gp_lvl2 >> (57 - 32)) & 1; +} + int get_lid_switch(void) { u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);

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New patch to review for coreboot: samsung/stumpy: implement get_write_protect_state
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10726 -gerrit commit c0f40654c36e3fc81e89fad9467ec00796807896 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:49:50 2015 +0200 samsung/stumpy: implement get_write_protect_state Current vboot wants that function. Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/samsung/stumpy/chromeos.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 8c24c80..d579c18 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -48,9 +48,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO68 = CHP3_SPI_WP */ gpios->gpios[0].port = GPIO_SPI_WP; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = - (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)), - SATA_SP) >> FLAG_SPI_WP) & 1; + gpios->gpios[0].value = get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -86,6 +84,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + int get_developer_mode_switch(void) { device_t dev;

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New patch to review for coreboot: samsung/lumpy: implement get_write_protect_state
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10725 -gerrit commit dc017005da7c9a6472c8f0f8332b12ea62d410d8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:49:50 2015 +0200 samsung/lumpy: implement get_write_protect_state Current vboot wants that function. Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/samsung/lumpy/chromeos.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 04ae5ff..8b772be 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -52,9 +52,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO24 = KBC3_SPI_WP# */ gpios->gpios[0].port = GPIO_SPI_WP; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = - (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)), - SATA_SP) >> FLAG_SPI_WP) & 1; + gpios->gpios[0].value = get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -89,6 +87,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + int get_developer_mode_switch(void) { device_t dev;

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New patch to review for coreboot: intel/sandybridge: initialize variable
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10724 -gerrit commit 85ada9c13d36ce9765af9825a5ca9aaf1e65513b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:48:45 2015 +0200 intel/sandybridge: initialize variable Otherwise cache_base may be uninitialized. Change-Id: Ie91f9567cea24114723a5362f52052d6ec22a6b8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/northbridge/intel/sandybridge/mrccache.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 94a7c39..f89fc0f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -72,7 +72,8 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { region_size = region_device_sz(&rdev); *mrc_region_ptr = rdev_mmap_full(&rdev); - } + } else + *mrc_region_ptr = NULL; } else { *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", CBFS_TYPE_MRC_CACHE,

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New patch to review for coreboot: google/jecht: Fix compiling GPIO table code
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10723 -gerrit commit 717b37c21e28269c264cc9c05c0aa11cc310d4fd Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:40:43 2015 +0200 google/jecht: Fix compiling GPIO table code A lot changed here between Chrome OS and upstream, and these changes are needed to reflect that. Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/jecht/chromeos.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 415db05..46c9871 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -39,19 +39,6 @@ #define GPIO_COUNT 6 -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; @@ -60,14 +47,15 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->count = GPIO_COUNT; gpio = gpios->gpios; - fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", + get_gpio(GPIO_SPI_WP)); fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", get_recovery_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", get_developer_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif

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New patch to review for coreboot: vboot: move vbnv_* sources around a bit more.
by Patrick Georgi 30 Jun '15

30 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10722 -gerrit commit b0ac76f78aa689e52124d6f8d70dff5228cc02ef Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 12:39:23 2015 +0200 vboot: move vbnv_* sources around a bit more. The many different places to put vboot verification in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: I9360face822ada7018a1cfdfced8da29b347cbb4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 5325bdd..a61bfb6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -22,13 +22,18 @@ verstage-y += chromeos.c romstage-y += chromeos.c ramstage-y += chromeos.c -libverstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c +bootblock-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c +verstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c -libverstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c + +bootblock-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c +verstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c romstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c ramstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c -libverstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c + +bootblock-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c +verstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c romstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c

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Patch set updated for coreboot: AMD Bettong: add fan control
by WANG Siyuan 30 Jun '15

30 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10721 -gerrit commit edde7eb891e9d4e5baf7f67c104577f0b551dd95 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:43:03 2015 +0800 AMD Bettong: add fan control 1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but not works on Windows 8, so I dindn't use it. After this issue is fiexed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. TEST: fan control works on Bettong. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 34 ++++++++++++++++ src/mainboard/amd/bettong/Makefile.inc | 3 ++ src/mainboard/amd/bettong/fchec.c | 67 ++++++++++++++++++++++++++++++++ src/mainboard/amd/bettong/fchec.h | 32 +++++++++++++++ src/vendorcode/amd/Kconfig | 2 +- 5 files changed, 137 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 1add1f5..1be7a85 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -51,6 +51,37 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); +/* Bettong Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control. the recommand way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + +#else /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + static const GPIO_CONTROL oem_bettong_gpio[] = { {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, @@ -76,6 +107,9 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + oem_fan_control(FchParams_env); +#endif /* XHCI configuration */ #if CONFIG_HUDSON_XHCI_ENABLE diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc index b9cd644..70722ee 100644 --- a/src/mainboard/amd/bettong/Makefile.inc +++ b/src/mainboard/amd/bettong/Makefile.inc @@ -22,3 +22,6 @@ romstage-y += PlatformGnbPcie.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +ramstage-y += fchec.c +endif diff --git a/src/mainboard/amd/bettong/fchec.c b/src/mainboard/amd/bettong/fchec.c new file mode 100644 index 0000000..3458f9b --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "fchec.h" + +void agesawrapper_fchecfancontrolservice() +{ + FCH_DATA_BLOCK LateParams; + + /* Thermal Zone Parameter */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111; + + FchECfancontrolservice(&LateParams); +} diff --git a/src/mainboard/amd/bettong/fchec.h b/src/mainboard/amd/bettong/fchec.h new file mode 100644 index 0000000..626ebb8 --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef FCHEC_H +#define FCHEC_H + +#include "imc.h" +//#include "FchPlatform.h" +#include "Porting.h" +#include "AGESA.h" +#include "FchCommonCfg.h" + +extern VOID FchECfancontrolservice (IN VOID *FchDataPtr); +void agesawrapper_fchecfancontrolservice(void); + +#endif diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 9720c79..2591cf9 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -34,7 +34,7 @@ choice config CPU_AMD_AGESA_BINARY_PI bool "binary PI" - select HUDSON_DISABLE_IMC + select HUDSON_DISABLE_IMC if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00630F01 help Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained

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New patch to review for coreboot: AMD Bettong: add fan control
by WANG Siyuan 30 Jun '15

30 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10721 -gerrit commit b2c09393643b7423eabbde6c318e22adae74975b Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:43:03 2015 +0800 AMD Bettong: add fan control 1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but not works on Windows 8, so I dindn't use it. After this issue is fiexed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 34 ++++++++++++++++ src/mainboard/amd/bettong/Makefile.inc | 3 ++ src/mainboard/amd/bettong/fchec.c | 67 ++++++++++++++++++++++++++++++++ src/mainboard/amd/bettong/fchec.h | 32 +++++++++++++++ src/vendorcode/amd/Kconfig | 2 +- 5 files changed, 137 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 1add1f5..1be7a85 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -51,6 +51,37 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); +/* Bettong Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control. the recommand way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + +#else /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + static const GPIO_CONTROL oem_bettong_gpio[] = { {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, @@ -76,6 +107,9 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + oem_fan_control(FchParams_env); +#endif /* XHCI configuration */ #if CONFIG_HUDSON_XHCI_ENABLE diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc index b9cd644..70722ee 100644 --- a/src/mainboard/amd/bettong/Makefile.inc +++ b/src/mainboard/amd/bettong/Makefile.inc @@ -22,3 +22,6 @@ romstage-y += PlatformGnbPcie.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +ramstage-y += fchec.c +endif diff --git a/src/mainboard/amd/bettong/fchec.c b/src/mainboard/amd/bettong/fchec.c new file mode 100644 index 0000000..3458f9b --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "fchec.h" + +void agesawrapper_fchecfancontrolservice() +{ + FCH_DATA_BLOCK LateParams; + + /* Thermal Zone Parameter */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111; + + FchECfancontrolservice(&LateParams); +} diff --git a/src/mainboard/amd/bettong/fchec.h b/src/mainboard/amd/bettong/fchec.h new file mode 100644 index 0000000..626ebb8 --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef FCHEC_H +#define FCHEC_H + +#include "imc.h" +//#include "FchPlatform.h" +#include "Porting.h" +#include "AGESA.h" +#include "FchCommonCfg.h" + +extern VOID FchECfancontrolservice (IN VOID *FchDataPtr); +void agesawrapper_fchecfancontrolservice(void); + +#endif diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 9720c79..2591cf9 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -34,7 +34,7 @@ choice config CPU_AMD_AGESA_BINARY_PI bool "binary PI" - select HUDSON_DISABLE_IMC + select HUDSON_DISABLE_IMC if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00630F01 help Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained

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coreboot-gerrit June 2015