coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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1299 discussions

New patch to review for coreboot: 3aca557 chromeos: add missing vboot functions
by Aaron Durbin 08 May '15

08 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10151 -gerrit commit 3aca557cb59241f962ccb3b3d52e419568b353be Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 8 15:54:31 2015 -0500 chromeos: add missing vboot functions Somewhere along the development path the following vboot functions were dropped: int vboot_enable_developer(void) int vboot_enable_recovery(void) Add them back, but also refactor the flag extraction so as not duplicate all that same logic. Change-Id: Id58f3b99f29caeff98b2d3111cfa28241d15b54f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index fb72673..1e49bd1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "vboot_handoff.h" -int vboot_skip_display_init(void) +static int vboot_handoff_flag(uint32_t flag) { struct vboot_handoff *vbho; @@ -35,7 +35,22 @@ int vboot_skip_display_init(void) if (vbho == NULL) return 0; - return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); + return !!(vbho->init_params.out_flags & flag); +} + +int vboot_skip_display_init(void) +{ + return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); +} + +int vboot_enable_developer(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); } int __attribute__((weak)) clear_recovery_mode_switch(void)

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New patch to review for coreboot: 02e00b6 arm: update verstage linking
by Aaron Durbin 08 May '15

08 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10150 -gerrit commit 02e00b65c2042cdb2f9fd63d9329e4a031331e36 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 8 15:52:52 2015 -0500 arm: update verstage linking The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Change-Id: Ib8427fe015b72e2282219f116a39949739a0af48 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/Makefile.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 3791ae7..8787d42 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -84,11 +84,12 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += ../../lib/memset.c

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New patch to review for coreboot: b014e5a arm: update verstage linking
by Aaron Durbin 08 May '15

08 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10149 -gerrit commit b014e5aaf13af8b728e07a66043fb8ed0ad1b1e3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 8 15:47:00 2015 -0500 arm: update verstage linking The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Lastly, VERSTAGE_LIB has no value so remove it. Change-Id: Ie53b42c4995a96006463ec5b358aa43a731cb1b8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/Makefile.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index c05b33e..0fd4fed 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,7 +61,7 @@ bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group @@ -73,10 +73,11 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += memset.S

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Patch merged into coreboot/master: ef33db0 cpu/amd/model_10xxx: Add missing ACPI _PSD object
by gerrit＠coreboot.org 08 May '15

08 May '15

the following patch was just integrated into master: commit ef33db01b31f49c82de3e740eb6a11fc1114f56a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri May 8 00:32:47 2015 -0500 cpu/amd/model_10xxx: Add missing ACPI _PSD object The ACPI power state generator for AMD 10xxx CPUs did not generate the _PSD object required for reliable PowerNow! operation. Without a correct _PSD object PowerNow! does not know the required core clock relationships, potentially causing unstable system operation. Generate the _PSD object in accordance with the BKDG Rev. 3.62. Change-Id: I255a4837ab29ff1b0874daf189ffb61798645795 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10142 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10142 for details. -gerrit

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Patch set updated for coreboot: db69764 northbridge/amd/amdfam10: Remove array to null comparison
by Timothy Pearson 08 May '15

08 May '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9596 -gerrit commit db69764399062b274d4d45e78941474ff9c0c4a5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 12 14:11:27 2015 -0500 northbridge/amd/amdfam10: Remove array to null comparison The address of array 'sysinfo->DCTstatA' will always evaluate to 'true'. Remove checking the base pointer of an array for validity. Found-by: Coverity (CID 1293135: Incorrect expression) Found-by: Clang (Wpointer-bool-conversion) Change-Id: I99c9c9f1564dfb997c60b2a895d664e3b06c117b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/raminit_amdmct.c | 50 +++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 6a71cd5..3471537 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -207,40 +207,40 @@ static void raminit_amdmct(struct sys_info *sysinfo) static void amdmct_cbmem_store_info(struct sys_info *sysinfo) { + if (!sysinfo) + return; + /* Save memory info structures for use in ramstage */ size_t i; struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); struct DCTStatStruc *pDCTstatA = NULL; - if (pMCTstat && sysinfo->DCTstatA) { - /* Allocate memory */ - struct amdmct_memory_info* mem_info; - mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); - if (!mem_info) - return; + /* Allocate memory */ + struct amdmct_memory_info* mem_info; + mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); + if (!mem_info) + return; - printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); + printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); - /* Initialize memory */ - memset(mem_info, 0, sizeof(struct amdmct_memory_info)); + /* Initialize memory */ + memset(mem_info, 0, sizeof(struct amdmct_memory_info)); - /* Copy data */ - memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc)); - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - pDCTstatA = sysinfo->DCTstatA + i; - memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); - } - mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); - mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); + /* Copy data */ + memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc)); + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + pDCTstatA = sysinfo->DCTstatA + i; + memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); + } + mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); + mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); - /* Zero out invalid/unused pointers */ + /* Zero out invalid/unused pointers */ #if IS_ENABLED(CONFIG_DIMM_DDR3) - - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - mem_info->dct_stat[i].C_MCTPtr = NULL; - mem_info->dct_stat[i].C_DCTPtr[0] = NULL; - mem_info->dct_stat[i].C_DCTPtr[1] = NULL; - } -#endif + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + mem_info->dct_stat[i].C_MCTPtr = NULL; + mem_info->dct_stat[i].C_DCTPtr[0] = NULL; + mem_info->dct_stat[i].C_DCTPtr[1] = NULL; } +#endif }

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New patch to review for coreboot: 8b326dc cbmem: Add initial allocation support
by Leroy P Leahy 08 May '15

08 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10148 -gerrit commit 8b326dcf7a2a62ca0f9f1b7f18510264754a0c38 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri May 8 11:33:55 2015 -0700 cbmem: Add initial allocation support Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/cbmem.h | 4 ++++ src/lib/imd_cbmem.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c5cd52a..8c6b096 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -144,12 +144,16 @@ struct cbmem_entry; */ #define DYN_CBMEM_ALIGN_SIZE (4096) +#define CBMEM_ROOT_SIZE DYN_CBMEM_ALIGN_SIZE /* By default cbmem is attempted to be recovered. Returns 0 if cbmem was * recovered or 1 if cbmem had to be reinitialized. */ int cbmem_initialize(void); +int cbmem_initialize_id_size(u32 id, u64 size); + /* Initialize cbmem to be empty. */ void cbmem_initialize_empty(void); +void cbmem_initialize_empty_id_size(u32 id, u64 size); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 0649bf3..bdef9d6 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -116,6 +116,11 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) void cbmem_initialize_empty(void) { + cbmem_initialize_empty_id_size(0, 0); +} + +void cbmem_initialize_empty_id_size(u32 id, u64 size) +{ struct imd *imd; struct imd imd_backing; @@ -133,6 +138,10 @@ void cbmem_initialize_empty(void) return; } + /* Add the specified range first */ + if (size) + cbmem_add(id, size); + /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); } @@ -146,6 +155,11 @@ static inline int cbmem_fail_recovery(void) int cbmem_initialize(void) { + return cbmem_initialize_id_size(0, 0); +} + +int cbmem_initialize_id_size(u32 id, u64 size) +{ struct imd *imd; struct imd imd_backing; @@ -167,6 +181,10 @@ int cbmem_initialize(void) imd_lockdown(imd); #endif + /* Add the specified range first */ + if (size) + cbmem_add(id, size); + /* Complete migration to CBMEM. */ cbmem_run_init_hooks();

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Patch merged into coreboot/master: 61942de northbridge/intel/gm45/gma: Minor cleanup
by gerrit＠coreboot.org 08 May '15

08 May '15

the following patch was just integrated into master: commit 61942de689ff8719573268c275a1aeabad403356 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Apr 6 21:54:56 2015 -0500 northbridge/intel/gm45/gma: Minor cleanup 1.) Removed invalid set of TRANS_STATE_MASK bit 2.) Used i915 register defines to clarify code Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9329 for details. -gerrit

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Patch merged into coreboot/master: f88b932 southbridge/i82801gx: Add x_EN defines for LPC_EN
by gerrit＠coreboot.org 08 May '15

08 May '15

the following patch was just integrated into master: commit f88b93214b68581e0c46d0108f3eec9f2fc21b2b Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 18:43:04 2015 +1000 southbridge/i82801gx: Add x_EN defines for LPC_EN A few hardcoded values could be fixed after this commit Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/10065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10065 for details. -gerrit

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Patch merged into coreboot/master: e7f7090 northbridge/intel/gm45/gma: Add backlight control register field
by gerrit＠coreboot.org 08 May '15

08 May '15

the following patch was just integrated into master: commit e7f70907bab2d511e94482eb606f6e3e629f52f9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Apr 6 22:01:23 2015 -0500 northbridge/intel/gm45/gma: Add backlight control register field This allows the backlight control register to be set via devicetree.cb Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9330 Tested-by: build bot (Jenkins) See http://review.coreboot.org/9330 for details. -gerrit

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Patch merged into coreboot/master: 59c2c8b checkpatch: fine tune checks
by gerrit＠coreboot.org 08 May '15

08 May '15

the following patch was just integrated into master: commit 59c2c8b07966a06fd742bc79efb960b8a900fbbc Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed May 6 11:10:18 2015 -0700 checkpatch: fine tune checks Fine tune the following two checks: - Check for incorrect file permissions This one had a linux path hard coded, so it would choke on some commits unnecessarily. - FILE_PATH_CHANGES seems to not be working correctly. It will choke on added / deleted files even if the MAINTAINERS file is touched. Hence, switch from WARN to CHK (as WARN currently blocks commits as well) Change-Id: I9fccfbd75e94f420de45cf8b58071e3198065cf3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10123 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10123 for details. -gerrit

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coreboot-gerrit May 2015