coreboot-gerrit May 2015

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Patch set updated for coreboot: b17abbc i945: Disable check for 2-dimm support.
by Vladimir Serbinenko 15 May '15

15 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7568 -gerrit commit b17abbc4e57c58719aee6cba9037fdc4fdedd80e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 22 21:12:14 2014 +0100 i945: Disable check for 2-dimm support. The check is wrong. On Acer Aspire One it returns 0 despite 2 DIMMs working fine on the same channel if this check is disabled (tested by memtest). On boards that have only 1 DIMM per channel, the code will simply find no SPD and skip empty slot. Change-Id: I5f2fdcd1d948ebf3eabebaea4441af4c19e47f8f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/i945/raminit.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c858cb8..e9c6956 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -208,16 +208,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -static int sdram_capabilities_two_dimms_per_channel(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */ - reg8 &= (1 << 0); - - return (reg8 != 0); -} - // TODO check if we ever need this function #if 0 static int sdram_capabilities_MEM4G_disable(void) @@ -382,10 +372,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (dimmno >> 1)) continue; - /* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (dimmno& 1)) - continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (dimmno >> 1), (dimmno & 1)); if (sysinfo->spd[dimmno][SPD_MEMORY_TYPE] != SPD_MEMORY_TYPE_SDRAM_DDR2) {

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Patch set updated for coreboot: 599fac5 i945: Merge romstage main().
by Vladimir Serbinenko 15 May '15

15 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7549 -gerrit commit 599fac5d79b01f43a7dd7894006d76811a1d2435 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Nov 19 19:59:56 2014 +0100 i945: Merge romstage main(). main() is pretty similar on all i945 boards. Main differences after this change: * mobo supplies standard hooks to do one thing at specific romstage point * instead of supplying a SPD map mainboard supplies an SPD retrieval function with standard library function to get SPD from one EEPROM. This allows to support machines like Acer Aspire One which have no EEPROM for soldered RAM. * PCI reset is controlled by Kconfig * Artec dongle init is controlled by Kconfig. Probably should be always done but I have no hardware to test. Change-Id: Iecae53a9e9e2183377fcd760641894f810e40118 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Kconfig | 1 + src/mainboard/apple/macbook21/romstage.c | 77 ++-------------- src/mainboard/getac/p470/romstage.c | 111 +++++++---------------- src/mainboard/ibase/mb899/romstage.c | 92 +++++--------------- src/mainboard/intel/d945gclf/romstage.c | 67 +++----------- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 113 +++++++----------------- src/mainboard/lenovo/t60/Kconfig | 2 + src/mainboard/lenovo/t60/romstage.c | 140 +++++++++--------------------- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 129 +++++++-------------------- src/mainboard/roda/rk886ex/Kconfig | 2 + src/mainboard/roda/rk886ex/romstage.c | 121 +++++++------------------- src/northbridge/intel/i945/Kconfig | 4 + src/northbridge/intel/i945/early_init.c | 87 +++++++++++++++++++ src/northbridge/intel/i945/raminit.c | 139 ++++++++++++++--------------- src/northbridge/intel/i945/raminit.h | 12 ++- 17 files changed, 376 insertions(+), 723 deletions(-) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 138ec87..6480097 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select VGA select MAINBOARD_DO_EDID select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index fa4276d..b990818 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -80,7 +78,7 @@ void setup_ich7_gpios(void) outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ } -static void ich7_enable_lpc(void) +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -190,7 +188,7 @@ static void ich7_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); } -static void rcba_config(void) +void rcba_config(void) { /* V0CTL Virtual Channel 0 Resource Control */ RCBA32(0x0014) = 0x80000001; @@ -210,7 +208,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -264,69 +262,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); - + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 0b98b4d..d71577d 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -30,8 +30,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -81,26 +79,6 @@ void setup_ich7_gpios(void) outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); - // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -170,7 +148,29 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 - 0x2ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); + // Enable 0x600 - 0x6ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // Enable 0x68 - 0x6f + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -194,7 +194,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -248,63 +248,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - -#if 0 - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); -#endif - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 6f3e943..3c26d89 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,8 +32,6 @@ #include <superio/winbond/w83627ehg/w83627ehg.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -57,20 +55,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -142,7 +126,23 @@ static void early_superio_config_w83627ehg(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0x290 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627ehg(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -152,7 +152,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -206,56 +206,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - early_superio_config_w83627ehg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 73e9843..09d7df6 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -31,7 +31,6 @@ #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -56,7 +55,7 @@ void setup_ich7_gpios(void) outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -66,9 +65,12 @@ static void ich7_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); // Enable SuperIO Power Management Events pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); + /* Enable SuperIO PM */ + lpc47m15x_enable_serial(PME_DEV, 0x680); + lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -84,7 +86,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -138,57 +140,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - /* Enable SuperIO PM */ - lpc47m15x_enable_serial(PME_DEV, 0x680); - lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 2a3cfe2..123222a 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 6a91e44..f0c5dbc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -31,8 +31,6 @@ #include <pc80/mc146818rtc.h> #include "option_table.h" #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -56,28 +54,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* TODO: superio code should really not be in mainboard */ static void pnp_enter_func_mode(device_t dev) { @@ -199,7 +175,31 @@ static void early_superio_config_w83627thg(void) pnp_exit_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); + // Enable HWM at 0xa00 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627thg(); +} + +void rcba_config(void) { u32 reg32; @@ -258,7 +258,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -312,61 +312,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config_w83627thg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 0cf19a1..3acee64 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index d84a495..8710d56 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -74,8 +72,26 @@ void setup_ich7_gpios(void) outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ } -static void ich7_enable_lpc(void) +static void early_superio_config(void) { + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0xa0); + + while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) +{ + int dock_err; + // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range @@ -94,25 +110,26 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -} -static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios(); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); + dock_err = dlpc_init(); - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -131,7 +148,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -185,87 +202,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); - setup_ich7_gpios(); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 0125d8c..ecbc9e8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 5bc2707..0d63218 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -81,7 +79,23 @@ void setup_ich7_gpios(void) outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) +static void early_superio_config(void) +{ + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); + + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -101,25 +115,19 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0x06); - - while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) - udelay(1000); - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -138,7 +146,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -192,81 +200,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); - + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index efe75a3..e0c7a15 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + select NORTHBRIDGE_INTEL_ARTEC_DONGLE config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 5f3fe9c..776e2ee 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -32,8 +32,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -68,27 +66,6 @@ void setup_ich7_gpios(void) // ------------------------------------------------------------ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -148,7 +125,30 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -173,7 +173,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -227,71 +227,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -static void init_artec_dongle(void) -{ - // Enable 4MB decoding - outb(0xf1, 0x88); - outb(0xf4, 0x88); -} - -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - /* This has to happen after i945_early_initialization() */ - init_artec_dongle(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 8a0cb5b..7f4ac17 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -35,6 +35,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n +config NORTHBRIDGE_INTEL_EARLY_PCI_RESET + def_bool n +config NORTHBRIDGE_INTEL_ARTEC_DONGLE + def_bool n config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index c73f094..a07481f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -26,6 +26,11 @@ #include <halt.h> #include <string.h> #include "i945.h" +#include <timestamp.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include "raminit.h" +#include <halt.h> int i945_silicon_revision(void) { @@ -980,3 +985,85 @@ void i945_late_initialization(int s3resume) i945_prepare_resume(s3resume); } + + +static void init_artec_dongle(void) +{ + // Enable 4MB decoding + outb(0xf1, 0x88); + outb(0xf4, 0x88); +} + +void main(unsigned long bist) +{ + int s3resume = 0; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_EARLY_PCI_RESET)) { + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + } + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + halt(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* This probably should be unconditional as artec dongle can + be used on any board but I have no hardware to test it. + */ + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_ARTEC_DONGLE)) { + /* This has to happen after i945_early_initialization() */ + init_artec_dongle(); + } + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c3f9bae..c858cb8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -51,18 +51,15 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) -static int get_dimm_spd_address(struct sys_info *sysinfo, int device) +void read_spd(spd_raw_data * spd, u8 addr) { - if (sysinfo->spd_addresses) - return sysinfo->spd_addresses[device]; - else - return DIMM0 + device; - -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); + int j; + int val; + val = smbus_read_byte(addr, 0); + if (val < 0) + return; + for (j = 1; j < 256; j++) + (*spd)[j] = smbus_read_byte(addr, j); } static __attribute__((noinline)) void do_ram_command(u32 command) @@ -330,7 +327,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int dimmno; /** * i945 supports two DIMMs, in two configurations: @@ -353,6 +350,9 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n"); } + memset(sysinfo->spd, 0, sizeof(sysinfo->spd)); + mainboard_get_spd(sysinfo->spd); + /** * Since we only support two DIMMs in total, there is a limited number * of combinations. This function returns the type of DIMMs. @@ -372,62 +372,61 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i=0; i<(2 * DIMM_SOCKETS); i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<(2 * DIMM_SOCKETS); dimmno++) { u8 reg8; /* Initialize the socket information with a sane value */ - sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_NOT_POPULATED; /* Dual Channel not supported, but Channel 1? Bail out */ - if (!sdram_capabilities_dual_channel() && (i >> 1)) + if (!sdram_capabilities_dual_channel() && (dimmno >> 1)) continue; /* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (i& 1)) + if (!sdram_capabilities_two_dimms_per_channel() && (dimmno& 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (dimmno >> 1), (dimmno & 1)); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { + if (sysinfo->spd[dimmno][SPD_MEMORY_TYPE] != SPD_MEMORY_TYPE_SDRAM_DDR2) { printk(BIOS_DEBUG, "N/A\n"); continue; } - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + reg8 = sysinfo->spd[dimmno][SPD_DIMM_CONFIG_TYPE]; if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + reg8 = sysinfo->spd[dimmno][SPD_MODULE_ATTRIBUTES]; if (reg8 & MODULE_BUFFERED) die("Error: Buffered memory not supported by this chipset\n"); if (reg8 & MODULE_REGISTERED) die("Error: Registered memory not supported by this chipset\n"); - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + switch (sysinfo->spd[dimmno][SPD_PRIMARY_SDRAM_WIDTH]) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x8DDS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DDS; break; case 0: printk(BIOS_DEBUG, "x8DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x16DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16DS; break; case 0: printk(BIOS_DEBUG, "x16SS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16SS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); @@ -437,7 +436,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); + dimm_mask |= (1 << dimmno); } if (!dimm_mask) { @@ -465,7 +464,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->spd[i][SPD_NUM_DIMM_BANKS] & (1 << 4)) sysinfo->package = 1; } } @@ -482,8 +481,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) for (i=0; i<2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); + cas_mask &= sysinfo->spd[i][SPD_ACCEPTABLE_CAS_LATENCIES]; } if(!cas_mask) { @@ -495,7 +493,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) { - int i, j, idx; + int dimmno, j, idx; int lowest_common_cas = 0; int max_ram_speed = 0; @@ -536,16 +534,15 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 int freq_cas_mask = cas_mask; PRINTK_DEBUG("Probing Speed %d\n", j); - for (i=0; i<2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<2*DIMM_SOCKETS; dimmno++) { int current_cas_mask; - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + PRINTK_DEBUG(" DIMM: %d\n", dimmno); + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); + current_cas_mask = sysinfo->spd[dimmno][SPD_ACCEPTABLE_CAS_LATENCIES]; while (current_cas_mask) { int highest_supported_cas = 0, current_cas = 0; @@ -571,11 +568,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 idx = highest_supported_cas - current_cas; PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); + PRINTK_DEBUG("tCLK=%x, ", sysinfo->spd[dimmno][spd_lookup_table[2*idx]]); + PRINTK_DEBUG("tAC=%x", sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]]); - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { + if (sysinfo->spd[dimmno][spd_lookup_table[2*idx]] <= ddr2_speeds_table[2*j] && + sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]] <= ddr2_speeds_table[(2*j)+1]) { PRINTK_DEBUG(": OK\n"); break; } @@ -587,7 +584,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 freq_cas_mask &= current_cas_mask; if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); + PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", dimmno); break; } } @@ -639,7 +636,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY]; if (!reg8) { die("Invalid tRAS value.\n"); } @@ -679,7 +676,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); + reg8 = sysinfo->spd[i][SPD_MIN_ROW_PRECHARGE_TIME]; if (!reg8) { die("Invalid tRP value.\n"); } @@ -720,7 +717,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_RAS_TO_CAS_DELAY]; if (!reg8) { die("Invalid tRCD value.\n"); } @@ -760,7 +757,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); + reg8 = sysinfo->spd[i][SPD_WRITE_RECOVERY_TIME]; if (!reg8) { die("Invalid tWR value.\n"); } @@ -841,8 +838,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); + refresh = sysinfo->spd[i][SPD_REFRESH] & ~(1 << 7); /* 15.6us */ if (!refresh) @@ -870,8 +866,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!(sysinfo->spd[i][SPD_SUPPORTED_BURST_LENGTHS] & SPD_BURST_LENGTH_8)) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1407,41 +1402,40 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, rows, columns, device; + int value, low, rows, columns; - device = get_dimm_spd_address(sysinfo, dimmno); sz.side1 = 0; sz.side2 = 0; - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + rows = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ if (rows < 0) goto hw_err; if ((rows & 0xf) == 0) goto val_err; sz.side1 += rows & 0xf; - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columns = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ if (columns < 0) goto hw_err; if ((columns & 0xf) == 0) goto val_err; sz.side1 += columns & 0xf; - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + value = sysinfo->spd[dimmno][SPD_NUM_BANKS_PER_SDRAM]; /* banks */ if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; sz.side1 += log2(value & 0xff); /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + value = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_MSB]; /* (high byte) */ if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ + low = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_LSB]; /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); if ((value != 72) && (value != 64)) goto val_err; sz.side1 += log2(value); /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ + value = sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS]; /* number of physical banks */ if (value < 0) goto hw_err; value &= 7; @@ -1494,8 +1488,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) sz = sdram_get_dimm_size(sysinfo, i); - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ + sysinfo->banks[i] = sysinfo->spd[i][SPD_NUM_BANKS_PER_SDRAM]; /* banks */ if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1575,24 +1568,21 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int dimmno, value; u16 dra0=0, dra1=0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes... \n"); - for(i=0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; + for(dimmno=0; dimmno < 2 * DIMM_SOCKETS; dimmno++) { u8 columnsrows; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + value = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ columnsrows = (value & 0x0f); - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + value = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ columnsrows |= (value & 0xf) << 4; switch (columnsrows) { @@ -1605,14 +1595,14 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo) } /* Double Sided DIMMs? */ - if (sysinfo->banksize[(2 * i) + 1] != 0) { + if (sysinfo->banksize[(2 * dimmno) + 1] != 0) { dra = (dra << 4) | dra; } - if (i < DIMM_SOCKETS) - dra0 |= (dra << (i*8)); + if (dimmno < DIMM_SOCKETS) + dra0 |= (dra << (dimmno*8)); else - dra1 |= (dra << ((i - DIMM_SOCKETS)*8)); + dra1 |= (dra << ((dimmno - DIMM_SOCKETS)*8)); } MCHBAR16(C0DRA0) = dra0; @@ -3051,7 +3041,7 @@ static void sdram_setup_processor_side(void) * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 * @param spd_addresses pointer to a list of SPD addresses */ -void sdram_initialize(int boot_path, const u8 *spd_addresses) +void sdram_initialize(int boot_path) { struct sys_info sysinfo; u8 reg8, cas_mask; @@ -3061,7 +3051,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.boot_path = boot_path; - sysinfo.spd_addresses = spd_addresses; /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ sdram_get_dram_configuration(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 9eb4193..20fbe8c 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -20,6 +20,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <device/dram/ddr3.h> + #define DIMM_SOCKETS 2 #define DIMM_TCO_BASE 0x30 @@ -63,14 +65,18 @@ struct sys_info { u8 banks[2 * DIMM_SOCKETS]; u8 banksize[2 * 2 * DIMM_SOCKETS]; - const u8 *spd_addresses; - + spd_raw_data spd[4]; } __attribute__ ((packed)); void receive_enable_adjust(struct sys_info *sysinfo); -void sdram_initialize(int boot_path, const u8 *sdram_addresses); +void sdram_initialize(int boot_path); int fixup_i945_errata(void); void udelay(u32 us); +void mainboard_get_spd(spd_raw_data *spd); +void read_spd(spd_raw_data *spd, u8 addr); +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void);

1 0

Patch set updated for coreboot: 8c5df13 autoport: Experimental stuff
by Vladimir Serbinenko 15 May '15

15 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit 8c5df13a91fb12506ac42d86a0905b8ee336c9ac Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 62 +++++ util/autoport/bd82x6x.go | 328 +++++++++++++++++++++++ util/autoport/i82801gx.go | 530 +++++++++++++++++++++++++++++++++++++ util/autoport/i945.go | 120 +++++++++ util/autoport/log_maker.go | 85 ++++++ util/autoport/log_reader.go | 314 ++++++++++++++++++++++ util/autoport/main.go | 617 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/rce823.go | 39 +++ util/autoport/root.go | 29 ++ util/autoport/sandybridge.go | 114 ++++++++ 10 files changed, 2238 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..f98fe27 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,62 @@ +package main + +import ( + "fmt" + "sort" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + keys := []int{} + for nid, _ := range codec.PinConfig { + keys = append(keys, nid) + } + + sort.Ints(keys) + + for _, nid := range keys { + fmt.Fprintf(az, "\n\t/* NID 0x%02x: Subsystem ID. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, codec.PinConfig[nid]) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..f633b4f --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,328 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } +} + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true + /* FIXME: hardcoded */ + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + /* FIXME: hardcoded */ + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + /* FIXME: hardcoded */ + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + pcieHotplugMap := "{ " + + for port := 0; port < 7; port++ { + if b.IsPCIeHotplug(ctx, port) { + pcieHotplugMap += "1, " + } else { + pcieHotplugMap += "0, " + } + } + + if b.IsPCIeHotplug(ctx, 7) { + pcieHotplugMap += "1 }" + } else { + pcieHotplugMap += "0 }" + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "alt_gp_smi_en": "0x0000", + "gpi1_routing": "2", + "gpi8_routing": "2", + "sata_interface_speed_support": "0x3", + "gen1_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "pcie_port_coalesce": "1", + "pcie_hotplug_map": pcieHotplugMap, + + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}] + + if ok { + cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8]) + cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0]) + cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) + } + + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ +`) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI32Simple(sb, addr, 0x84) + RestorePCI32Simple(sb, addr, 0x88) + RestorePCI32Simple(sb, addr, 0x8c) + RestorePCI32Simple(sb, addr, 0x90) + + RestorePCI16Simple(sb, addr, 0x80) + + RestorePCI32Simple(sb, addr, 0xac) + + sb.WriteString(`} + +void rcba_config(void) +{ + /* Disable devices. */ +`) + RestoreRCBA32(sb, inteltool, 0x3414) + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString("\n}\n") + + sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + + currentMap := map[uint32]int{ + 0x20000153: 0, + 0x20000f57: 1, + 0x2000055b: 2, + 0x20000f51: 3, + 0x2000094a: 4, + } + + for port := uint(0); port < 14; port++ { + var pinmask uint32 + OCPin := -1 + if port < 8 { + pinmask = inteltool.RCBA[0x35a0] + } else { + pinmask = inteltool.RCBA[0x35a4] + } + for pin := uint(0); pin < 4; pin++ { + if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { + OCPin = int(pin) + if port >= 8 { + OCPin += 4 + } + } + } + fmt.Fprintf(sb, "\t{ %d, %d, %d },\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], + OCPin) + } + sb.WriteString("};\n") + + sb.WriteString(` +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} +`) + + /* FIXME: hardcoded. */ + gnvs := Create(ctx, "gnvs.c") + defer gnvs.Close() + + gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + + AddRAMStageFile("gnvs.c", "") +} + +func init() { + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..323419a --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,530 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + KconfigBool["HAVE_MP_TABLE"] = true + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes +`) + + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME: does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutPCIChip(addr, ioapic) + + ideConfig := uint8(0) + ide, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}] + if ok { + ideConfig = ide.ConfigDump[0x54] + } + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME: should be a CMOS config */ + "sata_ahci": "0x1", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) + + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME: hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + ec.WriteString("/* FIXME: Add EC support here. */") + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + /* FIXME: hardcoded. */ + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; +} +`) + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + si.WriteString("/* FIXME: Add superio support here. */") + + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME: hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + + + + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME: hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* FIXME: Add EC support here */ + break; + case APM_CNT_ACPI_DISABLE: + /* FIXME: Add EC support here */ + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME: hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..91b1b98 --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,120 @@ +package main + +import ( + "log" + "strings" +) + +type i945mc struct { + variant string +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + + cpuModel := ctx.InfoSource.GetCPUModel()[0] + socket := "" + switch cpuModel >> 4 { + case 0x69, 0x6d, 0x6e, 0x6f: + socket = "mFCPGA478" + case 0x106c: + socket = "441" + default: + log.Fatalf("unsupported cpu: 0x%x", cpuModel) + } + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_" + socket, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "VGA"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 1}, writeEmpty: true, additionalComment: "Display controller"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_"+strings.ToUpper(socket)] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_" + i.variant] = true + + cs := Create(ctx, "cstates.c") + defer cs.Close() + AddRAMStageFile("cstates.c", "") + + /* FIXME: hardcoded. */ + cs.WriteString( + `#include <arch/acpigen.h> +#include <device/device.h> +#include <northbridge/intel/i945/i945.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} +`) +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27ac, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment: "display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..3abea7e --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,85 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + in, err := os.Open("/proc/cpuinfo") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..a17a6e9 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,314 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.Contains(line, "DEFAULT"): + continue + case strings.Contains(line, "DIFF"): + continue + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +func (l *LogDevReader) GetCPUModel() (ret []uint32) { + file, err := os.Open(l.InputDirectory + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + ret = make([]uint32, 0, 100) + proc := 0 + for scanner.Scan() { + line := scanner.Text() + sep := strings.Index(line, ":") + if sep < 0 { + continue + } + key := strings.TrimSpace(line[0:sep]) + val := strings.TrimSpace(line[sep+1:]) + + if key == "processor" { + proc, _ := strconv.Atoi(val) + if len(ret) <= proc { + ret = ret[0 : proc+1] + } + continue + } + if key == "cpu family" { + family, _ := strconv.Atoi(val) + ret[proc] |= uint32(((family & 0xf) << 8) | ((family & 0xff0) << 16)) + } + if key == "model" { + model, _ := strconv.Atoi(val) + ret[proc] |= uint32(((model & 0xf) << 4) | ((model & 0xf0) << 12)) + } + if key == "stepping" { + stepping, _ := strconv.Atoi(val) + ret[proc] |= uint32(stepping & 0xf) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..ad7e281 --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,617 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "sort" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte + GetCPUModel() []uint32 +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf("0x%04x", uint16(inp[0])|(uint16(inp[1])<<8)) +} + +func FormatHexLE32(d []uint8) string { + u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24) + return fmt.Sprintf("0x%08x", u) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMStageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMStageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+3], + pcidev.ConfigDump[addr+2], + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot.PCIAddr) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete(MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + keys := []string{} + for reg, _ := range dev.Registers { + keys = append(keys, reg) + } + + sort.Strings(keys) + + for _, reg := range keys { + val := dev.Registers[reg] + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIChip(addr PCIDevData, cur DevTreeNode) { + unmatchedPCIChips[addr.PCIAddr] = cur +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + SubVendor: uint16(addr.ConfigDump[0x2c]) | (uint16(addr.ConfigDump[0x2d]) << 8), + SubSystem: uint16(addr.ConfigDump[0x2e]) | (uint16(addr.ConfigDump[0x2f]) << 8), + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 { + cur.PCIController = true + cur.ChildPCIBus = int(addr.ConfigDump[0x19]) + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func makeKconfigName(ctx Context) { + kn := Create(ctx, "Kconfig.name") + defer kn.Close() + + fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model) +} + +func makeKconfig(ctx Context) { + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + keys := []string{} + for name, val := range KconfigBool { + if val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, "\tselect %s\n", name) + } + + keys = nil + for name, val := range KconfigBool { + if !val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + bool + default n +`, name) + } + + keys = nil + for name, _ := range KconfigStringUnquoted { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + string + default %s +`, name, KconfigStringUnquoted[name]) + } + + keys = nil + for name, _ := range KconfigString { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + string + default "%s" +`, name, KconfigString[name]) + } + + keys = nil + for name, _ := range KconfigHex { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + hex + default 0x%x +`, name, KconfigHex[name]) + } + + keys = nil + for name, _ := range KconfigInt { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + int + default %d +`, name, KconfigInt[name]) + } + + fmt.Fprintf(kc, "endif\n") +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + /* FIXME: hardcoded. */ + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + writeMF(mf, RAMStageFiles, "ramstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + if dmi.IsLaptop { + bi.WriteString("Category: laptop\n") + } else { + /* FIXME: other categories. */ + bi.WriteString("Category: desktop\n") + } + + rs := Create(ctx, "romstage.c") + defer rs.Close() + rs.WriteString("/* dummy file */\n") + + /* FIXME: flash chip. */ + + makeKconfig(ctx) + makeKconfigName(ctx) + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + /* FIXME: use scoping at another level. */ + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go new file mode 100644 index 0000000..7c92109 --- /dev/null +++ b/util/autoport/rce823.go @@ -0,0 +1,39 @@ +package main + +import "fmt" + +type rce823 struct { + variant string +} + +func (r rce823) Scan(ctx Context, addr PCIDevData) { + if addr.Dev == 0 && addr.Func == 0 { + cur := DevTreeNode{ + Chip: "drivers/ricoh/rce822", + Comment: "Ricoh cardreader", + Registers: map[string]string{ + + "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1), + "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false}, + }, + } + PutPCIChip(addr, cur) + } + PutPCIDev(addr, "Ricoh SD card reader") + KconfigBool["DRIVERS_RICOH_RCE822"] = true +} + +func init() { + RegisterPCI(0x1180, 0xe822, rce823{}) + RegisterPCI(0x1180, 0xe823, rce823{}) +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..60b5ccd --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,29 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x", + pciDev.PCIVenID, pciDev.PCIDevID)} + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..5466fcc --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,114 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment: "VGA controller"}}) +}

1 0

Patch merged into coreboot/master: 9d45d69 ibexpeak: Merge common NVS init
by gerrit＠coreboot.org 14 May '15

14 May '15

the following patch was just integrated into master: commit 9d45d6975ccdae7253c75259e1885b68186ce83d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Oct 20 19:16:44 2014 +0200 ibexpeak: Merge common NVS init Change-Id: Ia5e26110928fa011305c13362f20fbe78ca9cf30 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7134 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> See http://review.coreboot.org/7134 for details. -gerrit

1 0

New patch to review for coreboot: e4b7be7 cbfstool: Fix shadowed global index
by Kyösti Mälkki 14 May '15

14 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10210 -gerrit commit e4b7be72925c4d4836d90e950f95c28c844087b8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 15 09:14:09 2015 +0300 cbfstool: Fix shadowed global index Change-Id: Ic8bccea1f2ddef874d8e440fa4fa05de1d4f9550 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/cbfstool/partitioned_file.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c index 3f47a26..4e1a8b5 100644 --- a/util/cbfstool/partitioned_file.c +++ b/util/cbfstool/partitioned_file.c @@ -46,8 +46,8 @@ static unsigned count_selected_fmap_entries(const struct fmap *fmap, assert(callback); unsigned count = 0; - for (unsigned index = 0; index < fmap->nareas; ++index) { - if (callback(fmap->areas + index, arg)) + for (unsigned i = 0; i < fmap->nareas; ++i) { + if (callback(fmap->areas + i, arg)) ++count; } return count;

1 0

Patch set updated for coreboot: 86d970c cbfstool: Fix fmd_scanner build compatibility
by Kyösti Mälkki 14 May '15

14 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10162 -gerrit commit 86d970cb94087d08e1baddaff5df891263b39b14 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 9 08:06:02 2015 +0300 cbfstool: Fix fmd_scanner build compatibility Fixes these errors: error: declaration of ‘input’ shadows a global declaration [-Werror=shadow] error: redundant redeclaration of ‘isatty’ [-Werror=redundant-decls] Change-Id: I4563d36e5389db4fdc5be3ca4e0e88af2642f7f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/cbfstool/Makefile | 3 ++- util/cbfstool/Makefile.inc | 1 + util/cbfstool/fmd_scanner.l | 12 ++++++------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 4238445..6e8235b 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -93,7 +93,8 @@ $(FMAPTESTS_BINARY): $(FMAPTESTS_COMMON) # Yacc source is superset of header $(obj)/fmd_parser.o: CFLAGS += -Wno-redundant-decls -# Lex generates unneeded functions +# Lex generates unneeded functions and declarations +$(obj)/fmd_scanner.o: CFLAGS += -Wno-redundant-decls $(obj)/fmd_scanner.o: CFLAGS += -Wno-unused-function # Tolerate lzma sdk warnings $(obj)/lzma/C/LzmaEnc.o: CFLAGS += -Wno-sign-compare -Wno-cast-qual diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1aa9d76..2c8fa0a 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -84,6 +84,7 @@ $(objutil)/cbfstool/rmodtool: $(addprefix $(objutil)/cbfstool/,$(rmodobj)) # Yacc source is superset of header $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls # Lex generates unneeded functions +$(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-unused-function # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index d2cc43d..0a58210 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -23,8 +23,8 @@ #include <assert.h> #include <string.h> -int parse_integer(char *input, int base); -int copy_string(const char *input); +int parse_integer(char *src, int base); +int copy_string(const char *src); %} %option noyywrap @@ -44,10 +44,10 @@ MULTIPLIER [KMG] %% -int parse_integer(char *input, int base) +int parse_integer(char *src, int base) { char *multiplier = NULL; - unsigned val = strtoul(input, &multiplier, base); + unsigned val = strtoul(src, &multiplier, base); if (*multiplier) { switch(*multiplier) { @@ -71,8 +71,8 @@ int parse_integer(char *input, int base) return INTEGER; } -int copy_string(const char *input) +int copy_string(const char *src) { - yylval.strval = strdup(input); + yylval.strval = strdup(src); return STRING; }

1 0

New patch to review for coreboot: e665d70 util/inteltool: add Broadwell-U support
by Matt DeVillier 14 May '15

14 May '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10209 -gerrit commit e665d701dd5b5f7fd901c5684f69ec6777724ddf Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu May 14 21:58:33 2015 -0500 util/inteltool: add Broadwell-U support add handling of PCI IDs for Broadwell-U/Wildcat Point LP, using same functions as Haswell-U/Lynx Point LP Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- util/inteltool/gpio.c | 2 ++ util/inteltool/inteltool.c | 2 ++ util/inteltool/inteltool.h | 2 ++ util/inteltool/memory.c | 1 + util/inteltool/pcie.c | 3 +++ util/inteltool/powermgt.c | 1 + util/inteltool/rootcmplx.c | 1 + util/inteltool/spi.c | 1 + 8 files changed, 13 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index aaacd57..7084c44 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -856,6 +856,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = lynxpoint_lp_gpio_registers; size = ARRAY_SIZE(lynxpoint_lp_gpio_registers); @@ -1050,6 +1051,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: for (i = 0; i < 95; i++) { io_register_t tmp_gpio; char gpio_name[32]; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 1a6bda2..a3712c5 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -84,6 +84,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -163,6 +164,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, "Wildcat Point Low Power SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3014b3e..6c1977e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -112,6 +112,7 @@ #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -173,6 +174,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 3aa3e4f..950d4a3 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -216,6 +216,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 6fa94e9..ecfa2f1 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -216,6 +216,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -321,6 +322,7 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: dmi_registers = haswell_ult_dmi_registers; size = ARRAY_SIZE(haswell_ult_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -418,6 +420,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 2cefabe..865cfba 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -705,6 +705,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index f57e773..c099737 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -98,6 +98,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index e4a77b6..8873fc0 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -170,6 +170,7 @@ int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; size = ARRAY_SIZE(spi_bar_registers); spi_register = spi_bar_registers;

1 0

Patch set updated for coreboot: e9bb4e5 gm45: Link cstates.c rather than including it.
by Vladimir Serbinenko 14 May '15

14 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7375 -gerrit commit e9bb4e59a2ce67f45fb76f33d2daa35fceabcd14 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 13:44:36 2014 +0100 gm45: Link cstates.c rather than including it. The comment about necessity of include isn't true anymore as get_cst_entries is not weak anymore so if it's not found, the linking would fail. Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x200/Makefile.inc | 1 + src/mainboard/lenovo/x200/mainboard.c | 3 --- src/mainboard/roda/rk9/Makefile.inc | 2 ++ src/mainboard/roda/rk9/mainboard.c | 3 --- 4 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 4eb1216..c3c8a0e 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -18,3 +18,4 @@ ## ramstage-y += dock.c +ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 5354834..8ba7a35 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -32,9 +32,6 @@ #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> -#include "cstates.c" /* Include it, as the linker won't find - the overloaded weak function in there. */ - const char *smbios_mainboard_bios_version(void) { static char *s = NULL; diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index 1a6cb02..d69f715 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -18,3 +18,5 @@ ## ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c +ramstage-y += cstates.c + diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 4ae004b..1b607cc 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -26,9 +26,6 @@ #include <pc80/keyboard.h> #include <ec/acpi/ec.h> -#include "cstates.c" /* Include it, as the linker won't find - the overloaded weak function in there. */ - static void ec_setup(void) { /* Thermal limits? Values are from ectool's ram dump. */

1 0

Patch set updated for coreboot: 6d4957d Make acpi_fill_hest into parameter
by Vladimir Serbinenko 14 May '15

14 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7373 -gerrit commit 6d4957d217696721054a18548e2b46c25b76d532 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 13:36:18 2014 +0100 Make acpi_fill_hest into parameter This avoids thew need to supply weak function and avoids associated risks of forgetting to link in relevant files. Change-Id: Ie96475babb4aa4ea8db49023af5b31bfa63b21dc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 8 ++------ src/arch/x86/include/arch/acpi.h | 4 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 +++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 ++-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ++-- 10 files changed, 21 insertions(+), 24 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index bc2a0cc..bb994e2 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -554,11 +554,6 @@ static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } -unsigned long __attribute__((weak)) acpi_fill_hest(acpi_hest_t *hest) -{ - return (unsigned long)hest; -} - unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) { acpi_header_t *header = &(hest->header); @@ -618,7 +613,8 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t * } /* ACPI 4.0 */ -void acpi_write_hest(acpi_hest_t *hest) +void acpi_write_hest(acpi_hest_t *hest, + unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) { acpi_header_t *header = &(hest->header); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index da1a020..bb78aaa 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -546,10 +546,10 @@ unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, u8 dev, u8 fn); +void acpi_write_hest(acpi_hest_t *hest, + unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); -void acpi_write_hest(acpi_hest_t *hest); unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); -unsigned long acpi_fill_hest(acpi_hest_t *hest); void acpi_save_gnvs(u32 gnvs_address); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 26d4eee..7dabf4b 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -793,7 +793,7 @@ static void cpu_bus_init(device_t dev) /* North Bridge Structures */ -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -843,7 +843,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e4da36c..a65140c 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -815,7 +815,7 @@ static void northbridge_fill_ssdt_generator(void) acpigen_pop_len(); } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -845,7 +845,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 14f56f2..8a909e6 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -483,7 +483,7 @@ static unsigned scan_chains(device_t dev, unsigned max) } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -534,7 +534,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index b9baf0c..e7ecfa7 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -459,7 +459,7 @@ static void set_resources(struct device *dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -511,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 29337fb..840deaf 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -458,7 +458,8 @@ static void nb_set_resources(device_t dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -510,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 86d5a92..c557e8d 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -459,7 +459,7 @@ static void set_resources(device_t dev) } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -511,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 76581cd..6240b7e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -453,7 +453,7 @@ static void set_resources(device_t dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -505,7 +505,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 4f646f7..0e38f3e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -447,7 +447,7 @@ static void northbridge_init(struct device *dev) { } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -499,7 +499,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length;

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Patch set updated for coreboot: 8c0fd0c gm45: Link cstates.c rather than including it.
by Vladimir Serbinenko 14 May '15

14 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7375 -gerrit commit 8c0fd0c8de83362923017d786b61a7dba375e719 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 13:44:36 2014 +0100 gm45: Link cstates.c rather than including it. The comment about necessity of include isn't true anymore as get_cst_entries is not weak anymore so if it's not found, the linking would fail. Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x200/Makefile.inc | 1 + src/mainboard/lenovo/x200/mainboard.c | 3 --- src/mainboard/roda/rk9/Makefile.inc | 2 ++ src/mainboard/roda/rk9/mainboard.c | 3 --- 4 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 4eb1216..c3c8a0e 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -18,3 +18,4 @@ ## ramstage-y += dock.c +ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 5354834..8ba7a35 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -32,9 +32,6 @@ #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> -#include "cstates.c" /* Include it, as the linker won't find - the overloaded weak function in there. */ - const char *smbios_mainboard_bios_version(void) { static char *s = NULL; diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index 1a6cb02..d69f715 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -18,3 +18,5 @@ ## ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c +ramstage-y += cstates.c + diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 4ae004b..1b607cc 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -26,9 +26,6 @@ #include <pc80/keyboard.h> #include <ec/acpi/ec.h> -#include "cstates.c" /* Include it, as the linker won't find - the overloaded weak function in there. */ - static void ec_setup(void) { /* Thermal limits? Values are from ectool's ram dump. */

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coreboot-gerrit May 2015