coreboot-gerrit February 2015

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Patch set updated for coreboot: d11f3be AMD K8 fam10: Set SB_HT_CHAIN_ON_BUS0 default 0
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8353 -gerrit commit d11f3bee82e25423bcaef625665563186fff9913 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 11:23:16 2015 +0200 AMD K8 fam10: Set SB_HT_CHAIN_ON_BUS0 default 0 SB HyperTransport chain is always scanned before other chains on BUS0. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/ibm/e325/Kconfig | 4 ---- src/mainboard/ibm/e326/Kconfig | 4 ---- src/mainboard/iwill/dk8s2/Kconfig | 4 ---- src/mainboard/iwill/dk8x/Kconfig | 4 ---- src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/tyan/s2850/Kconfig | 4 ---- src/mainboard/tyan/s2875/Kconfig | 4 ---- src/mainboard/tyan/s2880/Kconfig | 4 ---- src/mainboard/tyan/s2882/Kconfig | 4 ---- src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdfam10/Kconfig | 4 ++++ src/northbridge/amd/amdfam10/northbridge.c | 27 ++++++++++++++------------- src/northbridge/amd/amdk8/Kconfig | 4 ++++ src/northbridge/amd/amdk8/northbridge.c | 23 +++++++++++------------ 15 files changed, 33 insertions(+), 69 deletions(-) diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 071557a..7cb8a31 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -69,6 +69,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a7d06fc..d5e6b89 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -283,27 +283,28 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; + int pass = 0; nodeid = amdfam10_nodeid(dev); - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } + /* Scan twice, first pass does SB HT chain only. */ + do { #if CONFIG_PCI_BUS_SEGN_BITS - max = check_segn(dev, max, sysconf.nodes, &sysconf); + if (pass == 1) + max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; + for (link = dev->link_list; link; link = link->next) { + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((pass==0) && !is_sblink) + continue; + if ((pass==1) && is_sblink) + continue; + max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + } + } while (++pass < 2); - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } return max; } diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 65dc173..8dd8cea 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,6 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config QRANK_DIMM_SUPPORT bool default n diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f775c25..4edc197 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -230,25 +230,24 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) unsigned nodeid; struct bus *link; unsigned sblink = 0; + unsigned pass = 0; nodeid = amdk8_nodeid(dev); if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + /* Scan twice, first pass does SB HT chain only. */ + do { + for (link = dev->link_list; link; link = link->next) { + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((pass==0) && !is_sblink) + continue; + if ((pass==1) && is_sblink) + continue; max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; + } + } while (++pass < 2); - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } return max; }

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Patch set updated for coreboot: c6b2a66 AMD fam10: Refactor variables in scan_chain
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8351 -gerrit commit c6b2a66a56188b51cf97f664a4e301945dc83dec Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:37:45 2015 +0200 AMD fam10: Refactor variables in scan_chain We only need one of devx and dev. This function should be called with dev already adjusted if link_num > 3. Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f2b18d0..f28c726 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -168,7 +168,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - device_t devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -182,14 +181,13 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 reg = pci_read_config32(dev, regpos); if(reg & 1) return max; // already ganged no sblink1 - devx = get_node_pci(nodeid, 4); - } else { - devx = dev; + + dev = get_node_pci(nodeid, 4); } /* Check for connected link. */ link->cap = 0x80 + ((link->link_num & 3) * 0x20); - if (!is_non_coherent_link(devx, link)) + if (!is_non_coherent_link(dev, link)) return max; /* See if there is an available configuration space mapping @@ -233,7 +231,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(devx, link->cap + 0x14); + busses = pci_read_config32(dev, link->cap + 0x14); /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is @@ -241,7 +239,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool */ busses &= 0xffff00ff; busses |= ((u32)(link->secondary) << 8); - pci_write_config32(devx, link->cap + 0x14, busses); + pci_write_config32(dev, link->cap + 0x14, busses); /* set the config map space */

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Patch set updated for coreboot: a91f91e AMD fam10: Move the test for connected HyperTransport link
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8350 -gerrit commit a91f91e4a4f292be7df406b3606c1b5870aa22af Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:23:03 2015 +0200 AMD fam10: Move the test for connected HyperTransport link Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 32 +++++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 275c79c..f2b18d0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -140,13 +140,29 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } +static bool is_non_coherent_link(struct device *dev, struct bus *link) +{ + u32 link_type; + do { + link_type = pci_read_config32(dev, link->cap + 0x18); + } while (link_type & ConnectionPending); + + if (!(link_type & LinkConnected)) + return false; + + do { + link_type = pci_read_config32(dev, link->cap + 0x18); + } while (!(link_type & InitComplete)); + + return !!(link_type & NonCoherent); +} + static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, u32 max) { // I want to put sb chain in bus 0 can I? - u32 link_type; int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain @@ -171,19 +187,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool devx = dev; } + /* Check for connected link. */ link->cap = 0x80 + ((link->link_num & 3) * 0x20); - do { - link_type = pci_read_config32(devx, link->cap + 0x18); - } while(link_type & ConnectionPending); - if (!(link_type & LinkConnected)) { - return max; - } - do { - link_type = pci_read_config32(devx, link->cap + 0x18); - } while(!(link_type & InitComplete)); - if (!(link_type & NonCoherent)) { + if (!is_non_coherent_link(devx, link)) return max; - } + /* See if there is an available configuration space mapping * register in function 1. */

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Patch set updated for coreboot: 954df57 AMD K8 fam10: Refactor offset_unitid configuration
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8349 -gerrit commit 954df57a112a7436007da002d4a7300aa0d46e9a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 13:09:06 2015 +0200 AMD K8 fam10: Refactor offset_unitid configuration Change-Id: I198f2ad321e1a8b6d932f5624b129e312e36a309 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/hypertransport_def.h | 7 +++++++ src/northbridge/amd/amdfam10/northbridge.c | 23 ++++++++++------------- src/northbridge/amd/amdk8/incoherent_ht.c | 14 ++++---------- src/northbridge/amd/amdk8/northbridge.c | 24 ++++++++++-------------- 4 files changed, 31 insertions(+), 37 deletions(-) diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index d6276ba..8af94d9 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -18,4 +18,11 @@ #define HT_FREQ_2600Mhz 14 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ + +static inline bool offset_unit_id(bool is_sb_ht_chain) +{ + bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); + return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain); +} + #endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8f6d6f9..275c79c 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -140,8 +140,8 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 sblink, - u32 max, u32 offset_unitid) +static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, + u32 max) { // I want to put sb chain in bus 0 can I? @@ -197,7 +197,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link->link_num)) { // actually max is 0 here + if (is_sblink) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -253,7 +253,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -290,9 +290,9 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ for (link = dev->link_list; link; link = link->next) { - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && (nodeid == 0) && (link->link_num == sblink)) - max = amdfam10_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } #if CONFIG_PCI_BUS_SEGN_BITS @@ -300,14 +300,11 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) #endif for (link = dev->link_list; link; link = link->next) { - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && (nodeid == 0) && (link->link_num == sblink)) + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) continue; - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - offset_unitid = offset_unitid && - (((nodeid == 0) && (sblink == link->link_num)) || !CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY); - - max = amdfam10_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } return max; } diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 40589c4..d765fc7 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -546,10 +546,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - offset_unitid = offset_unitid && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || (i == 0)); - - devn = offset_unitid ? CONFIG_HT_CHAIN_UNITID_BASE : 1; + devn = offset_unit_id(i == 0) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) { @@ -668,19 +665,16 @@ static int ht_setup_chains(uint8_t ht_c_num) dword |= (reg & 0xffff0000)>>8; pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - offset_unitid = offset_unitid && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || (i == 0)); - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(busn, offset_unitid); + ht_collapse_previous_enumeration(busn, offset_unit_id(i == 0)); upos = ((reg & 0xf00)>>8) * 0x20 + 0x80; udev = PCI_DEV(0, devpos, 0); #if CONFIG_RAMINIT_SYSINFO - ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not + ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0), sysinfo); // all not #else - reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not + reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0)); //all not #endif } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 6785659..29fa2a4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -84,8 +84,8 @@ static u32 amdk8_nodeid(device_t dev) return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 sblink, - u32 max, u32 offset_unitid) +static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, + u32 max) { u32 link_type; @@ -143,7 +143,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 sbli */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link->link_num)) { // actually max is 0 here + if(is_sblink) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -203,7 +203,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 sbli else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -244,21 +244,17 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 for (link = dev->link_list; link; link = link->next) { - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && (nodeid == 0) && (link->link_num == sblink)) - max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } for (link = dev->link_list; link; link = link->next) { - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && (nodeid == 0) && (link->link_num == sblink)) + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) continue; - unsigned offset_unitid = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - offset_unitid = offset_unitid && - (((nodeid == 0) && (sblink == link->link_num)) || !CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY); - - max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } return max; }

1 0

Patch set updated for coreboot: b38f5cc southbridge/amd/pi: Add the bolton definitions
by Dave Frodin 04 Feb '15

04 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8286 -gerrit commit b38f5cc51d206594c38ea01a7f2c29c7228e806e Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:48 2015 -0700 southbridge/amd/pi: Add the bolton definitions This adds the PCI and interrupt related definitions for the bolton specific features. Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 19 +++++++++++--- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 12 +++++++++ src/southbridge/amd/pi/hudson/pci_devs.h | 30 +++++++++++++++++++++++ 3 files changed, 57 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index e6bd2da..78a40f0 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -25,7 +25,6 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_NC 0x1F /* Not Used */ #define PIRQ_A 0x00 /* INT A */ @@ -41,9 +40,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -67,6 +66,18 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define FCH_INT_TABLE_SIZE 0x54 +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index d0fe9c8..517c892 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -20,6 +20,17 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -29,5 +40,6 @@ const char * intr_types[] = { [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", }; +#endif #endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index d2549d4..c22f758 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -28,6 +28,11 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -69,6 +74,14 @@ #define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 @@ -93,4 +106,21 @@ #define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + #endif /* _PI_HUDSON_PCI_DEVS_H_ */

1 0

Patch set updated for coreboot: 93e33f5 southbridge/amd/pi: Add the bolton definitions
by Dave Frodin 04 Feb '15

04 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8286 -gerrit commit 93e33f5611ef2609f7278ace2df9ec35e0eda03f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:48 2015 -0700 southbridge/amd/pi: Add the bolton definitions This adds the PCI and interrupt related definitions for the bolton specific features. Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 24 +++++++++++++----- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 12 +++++++++ src/southbridge/amd/pi/hudson/pci_devs.h | 30 +++++++++++++++++++++++ 3 files changed, 60 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index e6bd2da..27a1ad5 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -25,7 +25,6 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_NC 0x1F /* Not Used */ #define PIRQ_A 0x00 /* INT A */ @@ -41,17 +40,15 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ #define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ @@ -67,6 +64,21 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define FCH_INT_TABLE_SIZE 0x54 +#define PIRQ_SD 0x14 /* SD */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#define FCH_INT_TABLE_SIZE 0x63 +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_SD 0x17 /* SD */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index d0fe9c8..517c892 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -20,6 +20,17 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -29,5 +40,6 @@ const char * intr_types[] = { [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", }; +#endif #endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index d2549d4..c22f758 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -28,6 +28,11 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -69,6 +74,14 @@ #define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 @@ -93,4 +106,21 @@ #define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + #endif /* _PI_HUDSON_PCI_DEVS_H_ */

1 0

New patch to review for coreboot: b9e0df8 AMD K8 fam10: Set SB_HT_CHAIN_ON_BUS0 default 0
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8353 -gerrit commit b9e0df8ce1fbf95cc1d17e46ecb70de3ae1f69e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 11:23:16 2015 +0200 AMD K8 fam10: Set SB_HT_CHAIN_ON_BUS0 default 0 SB HyperTransport chain is always scanned before other chains on BUS0. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/ibm/e325/Kconfig | 4 ---- src/mainboard/ibm/e326/Kconfig | 4 ---- src/mainboard/iwill/dk8s2/Kconfig | 4 ---- src/mainboard/iwill/dk8x/Kconfig | 4 ---- src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/tyan/s2850/Kconfig | 4 ---- src/mainboard/tyan/s2875/Kconfig | 4 ---- src/mainboard/tyan/s2880/Kconfig | 4 ---- src/mainboard/tyan/s2882/Kconfig | 4 ---- src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdfam10/Kconfig | 4 ++++ src/northbridge/amd/amdfam10/northbridge.c | 27 ++++++++++++++------------- src/northbridge/amd/amdk8/Kconfig | 4 ++++ src/northbridge/amd/amdk8/northbridge.c | 23 +++++++++++------------ 15 files changed, 33 insertions(+), 69 deletions(-) diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 071557a..7cb8a31 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -69,6 +69,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a7d06fc..d5e6b89 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -283,27 +283,28 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; + int pass = 0; nodeid = amdfam10_nodeid(dev); - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } + /* Scan twice, first pass does SB HT chain only. */ + do { #if CONFIG_PCI_BUS_SEGN_BITS - max = check_segn(dev, max, sysconf.nodes, &sysconf); + if (pass == 1) + max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; + for (link = dev->link_list; link; link = link->next) { + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((pass==0) && !is_sblink) + continue; + if ((pass==1) && is_sblink) + continue; + max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + } + } while (++pass < 2); - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } return max; } diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 65dc173..8dd8cea 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,6 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config QRANK_DIMM_SUPPORT bool default n diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f775c25..4edc197 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -230,25 +230,24 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) unsigned nodeid; struct bus *link; unsigned sblink = 0; + unsigned pass = 0; nodeid = amdk8_nodeid(dev); if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + /* Scan twice, first pass does SB HT chain only. */ + do { + for (link = dev->link_list; link; link = link->next) { + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + if ((pass==0) && !is_sblink) + continue; + if ((pass==1) && is_sblink) + continue; max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; + } + } while (++pass < 2); - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } return max; }

1 0

New patch to review for coreboot: 5382062 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8352 -gerrit commit 5382062a78c7aadabd342c3388aab24a065d3aec Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 11:20:27 2015 +0200 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0 Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 40 ++++++++++++------------------ src/northbridge/amd/amdk8/northbridge.c | 29 ++++++++-------------- 2 files changed, 27 insertions(+), 42 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f28c726..a7d06fc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -169,10 +169,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 max_bus; u32 min_bus; u32 busses; - u32 segn = max>>8; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - u32 busn = max&0xff; -#endif u32 max_devfn; if (link->link_num > 3) { @@ -201,28 +197,24 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if (is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. - else { - min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same - } - max = min_bus | (segn<<8); - #else - //other ... - else { + u32 segn = max >> 8; + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { + min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + u32 busn = max & 0xff; + // second chain will be on 0x40, third 0x80, forth 0xc0 + // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 + // >4 will use more segments, + // We can have 16 segmment and every segment have 256 bus, + // For that case need the kernel support mmio pci config. + min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same + max = min_bus | (segn<<8); } - #endif -#else - min_bus = ++max; -#endif max_bus = 0xfc | (segn<<8); link->secondary = min_bus; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 29fa2a4..f775c25 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -141,26 +141,19 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if(is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { + min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + // second chain will be on 0x40, third 0x80, forth 0xc0 + min_bus = ((max>>6) + 1) * 0x40; + max = min_bus; } - #endif -#else - min_bus = ++max; -#endif + max_bus = 0xff; link->secondary = min_bus;

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New patch to review for coreboot: a8a2ca0 AMD fam10: Refactor variables in scan_chain
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8351 -gerrit commit a8a2ca0057a1d2aa1f2518d5470653b54b9f883c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:37:45 2015 +0200 AMD fam10: Refactor variables in scan_chain We only need one of devx and dev. This function should be called with dev already adjusted if link_num > 3. Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f2b18d0..f28c726 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -168,7 +168,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - device_t devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -182,14 +181,13 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 reg = pci_read_config32(dev, regpos); if(reg & 1) return max; // already ganged no sblink1 - devx = get_node_pci(nodeid, 4); - } else { - devx = dev; + + dev = get_node_pci(nodeid, 4); } /* Check for connected link. */ link->cap = 0x80 + ((link->link_num & 3) * 0x20); - if (!is_non_coherent_link(devx, link)) + if (!is_non_coherent_link(dev, link)) return max; /* See if there is an available configuration space mapping @@ -233,7 +231,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(devx, link->cap + 0x14); + busses = pci_read_config32(dev, link->cap + 0x14); /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is @@ -241,7 +239,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool */ busses &= 0xffff00ff; busses |= ((u32)(link->secondary) << 8); - pci_write_config32(devx, link->cap + 0x14, busses); + pci_write_config32(dev, link->cap + 0x14, busses); /* set the config map space */

1 0

New patch to review for coreboot: b349aa7 AMD fam10: Move the test for connected HyperTransport link
by Kyösti Mälkki 04 Feb '15

04 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8350 -gerrit commit b349aa740401bd243eb83223b4304a38f5f73844 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:23:03 2015 +0200 AMD fam10: Move the test for connected HyperTransport link Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 32 +++++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 275c79c..f2b18d0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -140,13 +140,29 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } +static bool is_non_coherent_link(struct device *dev, struct bus *link) +{ + u32 link_type; + do { + link_type = pci_read_config32(dev, link->cap + 0x18); + } while (link_type & ConnectionPending); + + if (!(link_type & LinkConnected)) + return false; + + do { + link_type = pci_read_config32(dev, link->cap + 0x18); + } while (!(link_type & InitComplete)); + + return !!(link_type & NonCoherent); +} + static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, u32 max) { // I want to put sb chain in bus 0 can I? - u32 link_type; int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain @@ -171,19 +187,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool devx = dev; } + /* Check for connected link. */ link->cap = 0x80 + ((link->link_num & 3) * 0x20); - do { - link_type = pci_read_config32(devx, link->cap + 0x18); - } while(link_type & ConnectionPending); - if (!(link_type & LinkConnected)) { - return max; - } - do { - link_type = pci_read_config32(devx, link->cap + 0x18); - } while(!(link_type & InitComplete)); - if (!(link_type & NonCoherent)) { + if (!is_non_coherent_link(devx, link)) return max; - } + /* See if there is an available configuration space mapping * register in function 1. */

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coreboot-gerrit February 2015