coreboot-gerrit October 2015

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Patch set updated for coreboot: mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
by Timothy Pearson 31 Oct '15

31 Oct '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12285 -gerrit commit 5f6d3b7073a67d52be3ca82deddaea6ebcb28bf1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 15:00:23 2015 -0500 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre_k8/Kconfig | 9 +++--- src/mainboard/asus/kfsn4-dre_k8/devicetree.cb | 5 +++- src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 6 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 39 +++++++++++++++----------- 4 files changed, 35 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig index bb05e95..39d530b 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig +++ b/src/mainboard/asus/kfsn4-dre_k8/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -35,15 +36,15 @@ config BOOTBLOCK_MAINBOARD_INIT config DCACHE_RAM_BASE hex - default 0xcf000 + default 0xc8000 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x08000 config APIC_ID_OFFSET hex - default 0 + default 0x10 config MAINBOARD_PART_NUMBER string @@ -63,7 +64,7 @@ config MAX_PHYSICAL_CPUS config MEM_TRAIN_SEQ int - default 0 + default 1 config HT_CHAIN_UNITID_BASE hex diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb index 0eae379..a02b234 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb @@ -180,11 +180,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "sata1_enable" = "1" end end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - device pci 19.0 on end + device pci 19.0 on end # Link 0 == LDT 0 + device pci 19.0 on end # Link 1 == LDT 1 + device pci 19.0 on end # Link 2 == LDT 2 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c index 8160457..d87bc3f 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c @@ -44,9 +44,9 @@ unsigned apicid_ck804; /* Here you only need to set value in pci1234 for HT-IO that could be installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */ static u32 pci1234x[] = { - 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ff0, 0x0000ff0, 0x0000ff0, }; @@ -54,7 +54,7 @@ static u32 pci1234x[] = { in chain, assume every chain only have 4 ht device at most */ static unsigned hcdnx[] = { - 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, }; static unsigned get_bus_conf_done = 0; diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 7098701..0c701df 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -66,6 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/early_ht.c" #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ @@ -199,7 +200,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; - u32 bsp_apicid = 0, val, wants_reset, needs_reset; + uint32_t bsp_apicid = 0; + uint32_t dword; + uint8_t needs_reset = 0; #if IS_ENABLED(CONFIG_SET_FIDVID) struct cpuid_result cpuid1; #endif @@ -207,8 +210,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - if (!cpu_init_detectedx && boot_cpu()) + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); sio_setup(); + } post_code(0x30); @@ -226,8 +233,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + dword = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -240,19 +247,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); post_code(0x35); - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - /* Wait for all base cores to start */ wait_all_core0_started(); + post_code(0x36); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x37); if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); - post_code(0x37); + post_code(0x38); wait_all_other_cores_started(bsp_apicid); + post_code(0x39); } ht_setup_chains_x(sysinfo); @@ -280,18 +289,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); - post_code(0x38); - - printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); - wants_reset = ck804_early_setup_x(); + post_code(0x3a); printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n"); needs_reset = optimize_link_coherent_ht(); printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n"); needs_reset |= optimize_link_incoherent_ht(sysinfo); + printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); + needs_reset |= ck804_early_setup_x(); /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { @@ -299,9 +309,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - if (wants_reset) - printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); - post_code(0x3b); allow_all_aps_stop(bsp_apicid);

1 0

Patch set updated for coreboot: mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
by Timothy Pearson 31 Oct '15

31 Oct '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12285 -gerrit commit e580855c6cceb3d8bb43ddb03c311757df341938 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 15:00:23 2015 -0500 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre_k8/Kconfig | 9 +++--- src/mainboard/asus/kfsn4-dre_k8/devicetree.cb | 5 +++- src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 6 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 39 +++++++++++++++----------- 4 files changed, 35 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig index bb05e95..39d530b 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig +++ b/src/mainboard/asus/kfsn4-dre_k8/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -35,15 +36,15 @@ config BOOTBLOCK_MAINBOARD_INIT config DCACHE_RAM_BASE hex - default 0xcf000 + default 0xc8000 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x08000 config APIC_ID_OFFSET hex - default 0 + default 0x10 config MAINBOARD_PART_NUMBER string @@ -63,7 +64,7 @@ config MAX_PHYSICAL_CPUS config MEM_TRAIN_SEQ int - default 0 + default 1 config HT_CHAIN_UNITID_BASE hex diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb index 0eae379..a02b234 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb @@ -180,11 +180,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "sata1_enable" = "1" end end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - device pci 19.0 on end + device pci 19.0 on end # Link 0 == LDT 0 + device pci 19.0 on end # Link 1 == LDT 1 + device pci 19.0 on end # Link 2 == LDT 2 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c index 8160457..d87bc3f 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c @@ -44,9 +44,9 @@ unsigned apicid_ck804; /* Here you only need to set value in pci1234 for HT-IO that could be installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */ static u32 pci1234x[] = { - 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ff0, 0x0000ff0, 0x0000ff0, }; @@ -54,7 +54,7 @@ static u32 pci1234x[] = { in chain, assume every chain only have 4 ht device at most */ static unsigned hcdnx[] = { - 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, }; static unsigned get_bus_conf_done = 0; diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 7098701..0c701df 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -66,6 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/early_ht.c" #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ @@ -199,7 +200,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; - u32 bsp_apicid = 0, val, wants_reset, needs_reset; + uint32_t bsp_apicid = 0; + uint32_t dword; + uint8_t needs_reset = 0; #if IS_ENABLED(CONFIG_SET_FIDVID) struct cpuid_result cpuid1; #endif @@ -207,8 +210,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - if (!cpu_init_detectedx && boot_cpu()) + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); sio_setup(); + } post_code(0x30); @@ -226,8 +233,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + dword = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -240,19 +247,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); post_code(0x35); - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - /* Wait for all base cores to start */ wait_all_core0_started(); + post_code(0x36); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x37); if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); - post_code(0x37); + post_code(0x38); wait_all_other_cores_started(bsp_apicid); + post_code(0x39); } ht_setup_chains_x(sysinfo); @@ -280,18 +289,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); - post_code(0x38); - - printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); - wants_reset = ck804_early_setup_x(); + post_code(0x3a); printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n"); needs_reset = optimize_link_coherent_ht(); printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n"); needs_reset |= optimize_link_incoherent_ht(sysinfo); + printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); + needs_reset |= ck804_early_setup_x(); /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { @@ -299,9 +309,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - if (wants_reset) - printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); - post_code(0x3b); allow_all_aps_stop(bsp_apicid);

1 0

New patch to review for coreboot: mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
by Timothy Pearson 31 Oct '15

31 Oct '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12285 -gerrit commit c77d236b605dcc6d2de9bb36032128da38ad0c2f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 15:00:23 2015 -0500 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre_k8/Kconfig | 8 +++--- src/mainboard/asus/kfsn4-dre_k8/devicetree.cb | 5 +++- src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 6 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 39 +++++++++++++++----------- 4 files changed, 34 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig index bb05e95..4fa33ea 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig +++ b/src/mainboard/asus/kfsn4-dre_k8/Kconfig @@ -35,15 +35,15 @@ config BOOTBLOCK_MAINBOARD_INIT config DCACHE_RAM_BASE hex - default 0xcf000 + default 0xc8000 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x08000 config APIC_ID_OFFSET hex - default 0 + default 0x10 config MAINBOARD_PART_NUMBER string @@ -63,7 +63,7 @@ config MAX_PHYSICAL_CPUS config MEM_TRAIN_SEQ int - default 0 + default 1 config HT_CHAIN_UNITID_BASE hex diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb index 0eae379..a02b234 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb @@ -180,11 +180,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "sata1_enable" = "1" end end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - device pci 19.0 on end + device pci 19.0 on end # Link 0 == LDT 0 + device pci 19.0 on end # Link 1 == LDT 1 + device pci 19.0 on end # Link 2 == LDT 2 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c index 8160457..d87bc3f 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c @@ -44,9 +44,9 @@ unsigned apicid_ck804; /* Here you only need to set value in pci1234 for HT-IO that could be installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */ static u32 pci1234x[] = { - 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ff0, 0x0000ff0, 0x0000ff0, }; @@ -54,7 +54,7 @@ static u32 pci1234x[] = { in chain, assume every chain only have 4 ht device at most */ static unsigned hcdnx[] = { - 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, }; static unsigned get_bus_conf_done = 0; diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 7098701..0c701df 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -66,6 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/early_ht.c" #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ @@ -199,7 +200,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; - u32 bsp_apicid = 0, val, wants_reset, needs_reset; + uint32_t bsp_apicid = 0; + uint32_t dword; + uint8_t needs_reset = 0; #if IS_ENABLED(CONFIG_SET_FIDVID) struct cpuid_result cpuid1; #endif @@ -207,8 +210,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - if (!cpu_init_detectedx && boot_cpu()) + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); sio_setup(); + } post_code(0x30); @@ -226,8 +233,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + dword = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -240,19 +247,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); post_code(0x35); - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - /* Wait for all base cores to start */ wait_all_core0_started(); + post_code(0x36); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x37); if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); - post_code(0x37); + post_code(0x38); wait_all_other_cores_started(bsp_apicid); + post_code(0x39); } ht_setup_chains_x(sysinfo); @@ -280,18 +289,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); - post_code(0x38); - - printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); - wants_reset = ck804_early_setup_x(); + post_code(0x3a); printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n"); needs_reset = optimize_link_coherent_ht(); printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n"); needs_reset |= optimize_link_incoherent_ht(sysinfo); + printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); + needs_reset |= ck804_early_setup_x(); /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { @@ -299,9 +309,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - if (wants_reset) - printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); - post_code(0x3b); allow_all_aps_stop(bsp_apicid);

1 0

Patch merged into coreboot/master: arch/x86: avoid race condition on build.h
by gerrit＠coreboot.org 31 Oct '15

31 Oct '15

the following patch was just integrated into master: commit ab355750fc444315bfecf4be2195a98eceaeacef Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Oct 15 11:07:07 2015 +0200 arch/x86: avoid race condition on build.h Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/11904 for details. -gerrit

1 0

New patch to review for coreboot: amd/00730F01: Add correct CPU model
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12284 -gerrit commit fb847c07c400a4742c87f0f288658e8b2fa13317 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 07:58:22 2015 +0300 amd/00730F01: Add correct CPU model Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00730F01/model_16_init.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 453d985..93b4839 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -46,9 +46,6 @@ static void model_16_init(device_t dev) u32 siblings; #endif - //x86_enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); disable_cache (); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); @@ -119,7 +116,8 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x730f00 }, /* ML-A0, Guess, TODO: */ + { X86_VENDOR_AMD, 0x730F00 }, + { X86_VENDOR_AMD, 0x730F01 }, { 0, 0 }, };

1 0

New patch to review for coreboot: AMD binaryPI: Fix include paths
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12283 -gerrit commit f39eb3a6bb9d07c422f7c650d77c4766168df74a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 31 18:31:36 2015 +0200 AMD binaryPI: Fix include paths Do not mix open-source AGESA and binaryPI includes. Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/fixme.c | 2 +- src/cpu/amd/pi/00660F01/fixme.c | 2 +- src/cpu/amd/pi/00730F01/fixme.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 10c5f86..f7d153e 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -18,7 +18,7 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index a9858c2..b1a4316 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -18,7 +18,7 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 2ec2237..3e8784a 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -18,7 +18,7 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" void amd_initcpuio(void)

1 0

Patch set updated for coreboot: Revert "AMD OemS3Save: refactor for Merlin Falcon"
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12282 -gerrit commit 93f67a71e5a618100c8e989a93085caa1c45486c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 31 18:06:52 2015 +0200 Revert "AMD OemS3Save: refactor for Merlin Falcon" This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93. Do not mix open-source AGESA and binary PI trees. Once you have working S3 support for binaryPI platforms, add the adapted oem_s3.c file as northbridge/amd/pi/oem_s3.c instead. Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/agesawrapper.h | 2 +- src/northbridge/amd/agesa/oem_s3.c | 8 +------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 7e58e79..eb1a59c 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -74,6 +74,6 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(void *vS3SaveParams); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index f9ce4a7..f1d3e4e 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -117,15 +117,9 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) static u8 MTRRStorage[S3_DATA_MTRR_SIZE]; -AGESA_STATUS OemS3Save(void *vS3SaveParams) +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) { -#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) - AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams; - S3_DATA_BLOCK *dataBlock = &S3SaveParams->S3DataBlock; -#else - AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams; AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; -#endif u32 MTRRStorageSize = 0; uintptr_t pos, size;

1 0

New patch to review for coreboot: Revert "AMD OemS3Save: refactor for Merlin Falcon"
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12282 -gerrit commit 793f11f79251a10f7dda862fef256b5732238370 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 31 18:06:52 2015 +0200 Revert "AMD OemS3Save: refactor for Merlin Falcon" This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93. Do not mix open-source AGESA and binary PI trees. Once you have working S3 support for binaryPI platforms, add the adapted oem_s3.c file as northbridge/amd/pi/oem_s3.c instead. Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/agesawrapper.h | 2 +- src/northbridge/amd/agesa/oem_s3.c | 8 +------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 7e58e79..eb1a59c 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -74,6 +74,6 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(void *vS3SaveParams); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index f9ce4a7..f1d3e4e 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -117,15 +117,9 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) static u8 MTRRStorage[S3_DATA_MTRR_SIZE]; -AGESA_STATUS OemS3Save(void *vS3SaveParams) +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) { -#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) - AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams; - S3_DATA_BLOCK *dataBlock = &S3SaveParams->S3DataBlock; -#else - AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams; AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; -#endif u32 MTRRStorageSize = 0; uintptr_t pos, size;

1 0

Patch set updated for coreboot: AGESA BiosCallouts: Remove cast
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12270 -gerrit commit 8723d4a8266ef03557ab36e70f34b76efed75e12 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 30 23:38:40 2015 +0200 AGESA BiosCallouts: Remove cast This cast only hides errors in matching the API properly. Change-Id: Ic396dfb572a50ac5ce5c1c83424e1f17f15bad1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.c | 2 +- src/mainboard/tyan/s8226/rd890_cfg.c | 2 +- src/northbridge/amd/agesa/BiosCallOuts.h | 2 +- src/northbridge/amd/agesa/agesawrapper.c | 20 ++++++++++---------- src/northbridge/amd/agesa/eventlog.c | 2 +- src/southbridge/amd/agesa/hudson/agesawrapper.c | 4 ++-- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index 9689b9d..06b335f 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index a337714..147d32b 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index a337714..147d32b 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index a337714..147d32b 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index 78925d9..a8faadf 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -39,7 +39,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr); typedef struct { UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINTN Data, VOID* ConfigPtr); + CALLOUT_ENTRY CalloutPtr; } BIOS_CALLOUT_STRUCT; extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index bfad605..4b2a23e 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -45,7 +45,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdParamStruct.NewStructPtr = &AmdResetParams; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -69,7 +69,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); @@ -98,7 +98,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -131,7 +131,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); @@ -161,7 +161,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); @@ -187,7 +187,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdS3LateParamsPtr = &AmdS3LateParams; AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); @@ -220,7 +220,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -248,7 +248,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdInterfaceParams.AllocationMethod = PostMemDram; AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; @@ -282,7 +282,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -342,7 +342,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 014a803..603c9b8 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -716,7 +716,7 @@ static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c index b98d7b4..20f504f 100644 --- a/src/southbridge/amd/agesa/hudson/agesawrapper.c +++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c @@ -53,7 +53,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore (void) StdHeader.HeapStatus = HEAP_SYSTEM_MEM; StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.CalloutPtr = &GetBiosCallout; StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; @@ -73,7 +73,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (void) StdHeader.HeapStatus = HEAP_SYSTEM_MEM; StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.CalloutPtr = &GetBiosCallout; StdHeader.Func = 0; StdHeader.ImageBasePtr = 0;

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Patch set updated for coreboot: AMD binaryPI BiosCallouts: Remove cast
by Kyösti Mälkki 31 Oct '15

31 Oct '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12271 -gerrit commit 53d0ebbc263ac27b8cd827011b6cc3f4bad67113 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 30 23:38:40 2015 +0200 AMD binaryPI BiosCallouts: Remove cast This cast only hides errors in matching the API properly. Change-Id: I9b878ab997b8ff087a7209f94522646b10b94bf6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/pi/BiosCallOuts.h | 2 +- src/northbridge/amd/pi/agesawrapper.c | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/pi/BiosCallOuts.h b/src/northbridge/amd/pi/BiosCallOuts.h index 6864f28..69f8355 100644 --- a/src/northbridge/amd/pi/BiosCallOuts.h +++ b/src/northbridge/amd/pi/BiosCallOuts.h @@ -61,7 +61,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); + CALLOUT_ENTRY CalloutPtr; } BIOS_CALLOUT_STRUCT; extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 9bdf340..7b9f153 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -67,7 +67,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdParamStruct.NewStructPtr = &AmdResetParams; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); @@ -99,7 +99,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); @@ -129,7 +129,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = NULL; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -185,7 +185,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; status = AmdCreateStruct (&AmdParamStruct); @@ -253,7 +253,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -291,7 +291,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; @@ -345,7 +345,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( &(ApExeParams.StdHeader)); ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; @@ -377,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); @@ -410,7 +410,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore(void) StdHeader.HeapStatus = HEAP_SYSTEM_MEM; StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.CalloutPtr = &GetBiosCallout; StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; @@ -445,7 +445,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdS3LateParamsPtr = &AmdS3LateParams; AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); @@ -479,7 +479,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void) StdHeader.HeapStatus = HEAP_SYSTEM_MEM; StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.CalloutPtr = &GetBiosCallout; StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; @@ -521,7 +521,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdInterfaceParams.AllocationMethod = PostMemDram; AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; @@ -580,7 +580,7 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) &(AmdEventParams.StdHeader)); AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.HeapStatus = HeapStatus;

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coreboot-gerrit October 2015