coreboot-gerrit January 2015

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Patch set updated for coreboot: 19bb78c CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
by Kyösti Mälkki 27 Jan '15

27 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7888 -gerrit commit 19bb78c2fda2c495dec95b700f384ed3659fa071 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 22 12:28:07 2014 +0200 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 9 ++--- src/cpu/intel/haswell/romstage.c | 4 +- src/include/cbmem.h | 4 +- src/mainboard/emulation/qemu-i440fx/memory.c | 4 +- src/northbridge/intel/fsp_rangeley/raminit.c | 14 ++++--- src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 + .../intel/fsp_sandybridge/northbridge.c | 10 ----- src/northbridge/intel/fsp_sandybridge/ram_calc.c | 38 +++++++++++++++++ src/northbridge/intel/fsp_sandybridge/raminit.c | 8 ---- src/northbridge/intel/gm45/ram_calc.c | 7 +++- src/northbridge/intel/haswell/ram_calc.c | 11 +++-- src/northbridge/intel/i945/ram_calc.c | 11 +++-- src/northbridge/intel/nehalem/ram_calc.c | 11 +++-- src/northbridge/intel/sandybridge/ram_calc.c | 11 +++-- src/soc/intel/baytrail/baytrail/smm.h | 2 +- src/soc/intel/baytrail/memmap.c | 8 ++-- src/soc/intel/broadwell/memmap.c | 13 ++++-- src/soc/intel/fsp_baytrail/Makefile.inc | 2 - src/soc/intel/fsp_baytrail/baytrail/smm.h | 2 +- src/soc/intel/fsp_baytrail/memmap.c | 22 +++++++++- src/soc/intel/fsp_baytrail/raminit.c | 47 ---------------------- 21 files changed, 131 insertions(+), 109 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 80588c3..a145223 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -57,23 +57,20 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif - -#else +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } - -#endif /* DYNAMIC_CBMEM */ +#endif +#endif /* !DYNAMIC_CBMEM */ void cbmem_run_init_hooks(void) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index bd2513f..1af5259 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; - top_of_ram = get_top_of_ram(); + top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size) /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); + return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } void ramstage_cache_invalid(struct ramstage_cache *cache) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 88d2bfe..05708da 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -190,6 +190,8 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif +unsigned long get_top_of_ram(void); + void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -201,8 +203,6 @@ static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) /* Common API between cbmem and dynamic cbmem. */ -unsigned long get_top_of_ram(void); - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index a189d75..d43b4e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,7 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return qemu_get_memory_size() * 1024; + return (void *) (qemu_get_memory_size() * 1024); } diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..9626745 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -26,19 +26,23 @@ #include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Calculate the top of usable (low) DRAM. * The FSP's reserved memory sits just below the SMM region, * allowing calculation of the top of usable memory. */ - u32 tom = sideband_read(B_UNIT, BMBOUND); - u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; + uintptr_t tom = sideband_read(B_UNIT, BMBOUND); + uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; if (bsmmrrl) { tom = bsmmrrl; } - tom -= FSP_RESERVE_MEMORY_SIZE; - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); } diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 080a7f4..ca6f345 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -20,11 +20,13 @@ subdirs-y += fsp ramstage-y += northbridge.c +ramstage-y += ram_calc.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += raminit.c +romstage-y += ram_calc.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b39f4c9 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -unsigned long get_top_of_ram(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c new file mode 100644 index 0000000..43a1105 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <fsp_util.h> +#include "northbridge.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); +} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c index 19b48ca..8689274 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ b/src/northbridge/intel/fsp_sandybridge/raminit.c @@ -74,11 +74,3 @@ void report_memory_config(void) ((ch_conf >> 16) & 1) ? ", selected" : ""); } } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c8c15d3..d9d3357 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -86,7 +86,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -105,3 +105,8 @@ unsigned long get_top_of_ram(void) } return tor; } + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index 99e7d67..01ad50d 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -24,12 +24,17 @@ #include <cbmem.h> #include "haswell.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignement. */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); } diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index d09b2e1..4b7d895 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -24,9 +24,9 @@ #include <cbmem.h> #include "i945.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { - u32 tom; + uintptr_t tom; if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { /* IGD enabled, get top of Memory from BSM register */ @@ -53,5 +53,10 @@ unsigned long get_top_of_ram(void) /* TSEG either disabled or invalid */ break; } - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index db57a3d..d36684e 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "nehalem.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 3693a07..e147909 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "sandybridge.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h index 5ead89f..0d920fb 100644 --- a/src/soc/intel/baytrail/baytrail/smm.h +++ b/src/soc/intel/baytrail/baytrail/smm.h @@ -31,7 +31,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f383d82..f2e14b3 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -22,12 +22,12 @@ #include <baytrail/iosf.h> #include <baytrail/smm.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return (unsigned long)smm_region_start(); + return (void *) smm_region_start(); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 046cc1d..28f4062 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -23,19 +23,24 @@ #include <broadwell/pci_devs.h> #include <broadwell/systemagent.h> -unsigned long get_top_of_ram(void) +static uintptr_t dpr_region_start(void) { /* * Base of DPR is top of usable DRAM below 4GiB. The register has * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); - u32 tom = dpr & ~((1 << 20) - 1); + uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t tom = dpr & ~((1 << 20) - 1); /* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM) tom -= (dpr & DPR_SIZE_MASK) << 16; - return (unsigned long)tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) dpr_region_start(); } diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fcbe6e7..3896e85 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -44,8 +44,6 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c ramstage-y += pmutil.c -romstage-y += raminit.c -ramstage-y += raminit.c ramstage-y += southcluster.c romstage-y += reset.c ramstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h index 0208c9f..136c2ca 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/smm.h +++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h @@ -36,7 +36,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 83858b8..615916b 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,25 @@ #include <cbmem.h> #include <baytrail/iosf.h> #include <baytrail/smm.h> +#include <drivers/intel/fsp/fsp_util.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); +} + +/* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + * + * The entire memory map is shown in northcluster.c + */ + +void *cbmem_top(void) +{ + uintptr_t tom = smm_region_start(); + if (!tom) + tom = iosf_bunit_read(BUNIT_BMBOUND); + return (void *) tom - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c deleted file mode 100644 index 55692d2..0000000 --- a/src/soc/intel/fsp_baytrail/raminit.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <cbmem.h> -#include <device/device.h> -#include <baytrail/baytrail.h> -#include <baytrail/iosf.h> -#include <cpu/x86/msr.h> -#include <drivers/intel/fsp/fsp_util.h> - -unsigned long get_top_of_ram(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - * - * The entire memory map is shown in northcluster.c - */ - u32 tom = iosf_bunit_read(BUNIT_BMBOUND); - u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - tom -= FSP_RESERVE_MEMORY_SIZE; - - return (unsigned long) tom; -}

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Patch set updated for coreboot: f2cb0fa CBMEM console: Fix and enhance pre-RAM support
by Kyösti Mälkki 27 Jan '15

27 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7862 -gerrit commit f2cb0fa789e42665c1f33cd78299d5bea4ff1b0f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 21 08:55:47 2014 +0200 CBMEM console: Fix and enhance pre-RAM support Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/Kconfig | 4 -- src/arch/arm/bootblock.ld | 4 +- src/arch/arm/romstage.ld | 2 +- src/arch/arm64/bootblock.ld | 2 + src/arch/arm64/romstage.ld | 2 +- src/arch/riscv/romstage.ld | 2 +- src/console/Kconfig | 14 +++++-- src/include/console/cbmem_console.h | 3 +- src/lib/Makefile.inc | 1 + src/lib/cbmem_console.c | 80 +++++++++++++++++++++---------------- 10 files changed, 66 insertions(+), 48 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 1c3a339..124dc3f 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -24,10 +24,6 @@ config ARM_BOOTBLOCK_CUSTOM bool default n -config CBMEM_CONSOLE_PRERAM_BASE - hex - depends on CONSOLE_CBMEM - config CPU_HAS_BOOTBLOCK_INIT bool default n diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index c1a6ccf..5b91f4b 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -49,8 +49,8 @@ SECTIONS *(.sbss.*); } : to_load = 0xff - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; - verstage_preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; + verstage_preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld index 8c32046..34e9eaa 100644 --- a/src/arch/arm/romstage.ld +++ b/src/arch/arm/romstage.ld @@ -69,7 +69,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index acce1f1..907d009 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -49,6 +49,8 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; + /DISCARD/ : { *(.comment) *(.note) diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index d05fdd1..a8d092c 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld index 839c285..a58aee3 100644 --- a/src/arch/riscv/romstage.ld +++ b/src/arch/riscv/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - /*preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;*/ + /*preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;*/ /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/console/Kconfig b/src/console/Kconfig index 0d32011..5974695 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -175,8 +175,9 @@ config CONSOLE_CBMEM Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space. +if CONSOLE_CBMEM + config CONSOLE_CBMEM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" default 0x20000 help @@ -184,9 +185,14 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_PRERAM_BUFFER_BASE + hex + default 0xabadbeef if !CACHE_AS_RAM || BROKEN_CAR_MIGRATE + default 0x0 + config CONSOLE_PRERAM_BUFFER_SIZE - depends on CONSOLE_CBMEM - hex "Room allocated for console output before RAM is initialized" + hex + default 0x0 if CONSOLE_PRERAM_BUFFER_BASE = 0xabadbeef default 0xc00 help Console is used before RAM is initialized. This is the room reserved @@ -194,6 +200,8 @@ config CONSOLE_PRERAM_BUFFER_SIZE can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. +endif + config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" depends on BOARD_EMULATION_QEMU_X86 diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 36d132c..81bc10f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -32,7 +32,8 @@ static inline void cbmemc_reinit(void) {} #endif #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ - ((ENV_ROMSTAGE && !CONFIG_BROKEN_CAR_MIGRATE) || ENV_RAMSTAGE) + (ENV_RAMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE && \ + ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || ENV_ROMSTAGE))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 946012d..b5eb819 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index a8195a6..6783b30 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -37,6 +37,9 @@ struct cbmem_console { static struct cbmem_console *cbmem_console_p CAR_GLOBAL; +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p); + #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -63,6 +66,10 @@ extern struct cbmem_console preram_cbmem_console; static u8 static_console[STATIC_CONSOLE_SIZE]; #endif +/* flags for init */ +#define CBMEMC_RESET (1<<0) +#define CBMEMC_APPEND (1<<1) + static inline struct cbmem_console *current_console(void) { return car_sync_var(cbmem_console_p); @@ -73,27 +80,46 @@ static inline void current_console_set(struct cbmem_console *new_console_p) car_set_var(cbmem_console_p, new_console_p); } -static inline void init_console_ptr(void *storage, u32 total_space) +static inline void init_console_ptr(void *storage, u32 total_space, int flags) { struct cbmem_console *cbm_cons_p = storage; - /* Initialize the cache-as-ram pointer and underlying structure. */ - car_set_var(cbmem_console_p, cbm_cons_p); - cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); - cbm_cons_p->buffer_cursor = 0; + if (!cbm_cons_p) { + current_console_set(NULL); + return; + } + + if (flags & CBMEMC_RESET) { + cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->buffer_cursor = 0; + } + if (flags & CBMEMC_APPEND) { + struct cbmem_console *tmp_cons_p = current_console(); + if (tmp_cons_p) + copy_console_buffer(tmp_cons_p, cbm_cons_p); + } + + current_console_set(cbm_cons_p); } void cbmemc_init(void) { #ifdef __PRE_RAM__ + int flags = CBMEMC_RESET; + + /* Do not clear output from bootblock. */ + if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_CACHE_AS_RAM)) + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + flags = 0; + init_console_ptr(&preram_cbmem_console, - CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE, flags); #else /* * Initializing before CBMEM is available, use static buffer to store * the log. */ - init_console_ptr(static_console, sizeof(static_console)); + init_console_ptr(static_console, sizeof(static_console), CBMEMC_RESET); #endif } @@ -119,13 +145,11 @@ void cbmemc_tx_byte(unsigned char data) * If there is overflow - add to the destination area a string, reporting the * overflow and the number of dropped characters. */ -static void copy_console_buffer(struct cbmem_console *new_cons_p) +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p) { u32 copy_size, dropped_chars; u32 cursor = new_cons_p->buffer_cursor; - struct cbmem_console *old_cons_p; - - old_cons_p = current_console(); if (old_cons_p->buffer_cursor < old_cons_p->buffer_size) copy_size = old_cons_p->buffer_cursor; @@ -187,35 +211,21 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; + int flags = CBMEMC_APPEND; -#ifdef __PRE_RAM__ - if (IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (ENV_ROMSTAGE && (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) return; -#endif - -#ifndef __PRE_RAM__ - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (!cbm_cons_p) { - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - - if (!cbm_cons_p) { - current_console_set(NULL); - return; - } - cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - - sizeof(struct cbmem_console); + /* If CBMEM entry already existed, old contents is not altered. */ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - cbm_cons_p->buffer_cursor = 0; - } + /* Clear old contents of CBMEM buffer. */ + if (ENV_ROMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) + flags |= CBMEMC_RESET; - copy_console_buffer(cbm_cons_p); - - current_console_set(cbm_cons_p); + init_console_ptr(cbm_cons_p, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } - /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit)

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Patch set updated for coreboot: ac088f3 FSP platforms: Clear area in CAR for cbmem
by Kyösti Mälkki 27 Jan '15

27 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195 -gerrit commit ac088f344881196afee920046d50e5cd85b2d411 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem cbmem requires that the memory at DCACHE_RAM_BASE be cleared or it does not get used. This patch just clears CAR memory, leaving 4k untouched for stack. The stack is very small at this point, and obviously doesn't care whether the memory is cleared or not. The FSP has loaded a pattern into CAR, which helps to see the stack usage (and poisons the stack as well). Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 3 +++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 ++ src/southbridge/intel/fsp_rangeley/romstage.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 72832ea..e836bfa 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -180,6 +180,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) u32 pm1_cnt; u16 pm1_sts; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); + post_code(0x40); #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b0b8133..8ba0886 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -158,6 +158,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); post_code(0x40); program_base_addresses(); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..62cb567 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -44,6 +44,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); + /* * Do not use the Serial Console before it is setup. * This causes the I/O to clog and a side effect is

1 0

Patch set updated for coreboot: 2052e85 drivers/intel/fsp: Add find_saved_temp_mem()
by Kyösti Mälkki 27 Jan '15

27 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8194 -gerrit commit 2052e85b6cbb2f3a3f5e2267d1c2c2c846a4a4bb Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:11:55 2015 -0700 drivers/intel/fsp: Add find_saved_temp_mem() Add a function to retrieve the location of the CAR temporary memory that was saved by the FSP into the HOB structure. Change-Id: I2635de5207cd699740721d333a7706425b837651 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/fsp_util.c | 18 ++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 7 +++++++ 2 files changed, 25 insertions(+) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index d0ed9cf..0844b37 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -177,6 +177,24 @@ volatile u8 * find_fsp () return (fsp_ptr); } +/** finds the saved temporary memory information in the FSP HOB list + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to saved CAR MEM or NULL if not found. + */ +void * find_saved_temp_mem(void *hob_list_ptr) +{ + EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + EFI_HOB_GUID_TYPE *saved_mem_hob = + (EFI_HOB_GUID_TYPE *) find_hob_by_guid( + hob_list_ptr, &temp_hob_guid); + + if (saved_mem_hob == NULL) + return NULL; + + return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); +} + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index 3c72f24..a39f5a2 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -37,6 +37,7 @@ void print_fsp_info(void); void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); +void * find_saved_temp_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); @@ -124,4 +125,10 @@ extern void *FspHobListPtr; UpdData->member?"Enabled":"Disabled"); \ break; + +#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }; +#endif + #endif /* FSP_UTIL_H */

1 0

Patch merged into coreboot/master: 7b132de drivers/intel/fsp: Add HOB tools to work with GUIDs
by gerrit＠coreboot.org 27 Jan '15

27 Jan '15

the following patch was just integrated into master: commit 7b132deb80a81443faff983f25768d859af2e778 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sat Jan 3 17:18:58 2015 -0700 drivers/intel/fsp: Add HOB tools to work with GUIDs Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8066 for details. -gerrit

1 0

Patch set updated for coreboot: c00c31e southbridge/amd/pi: write_hpet requires additional config option
by Dave Frodin 27 Jan '15

27 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8288 -gerrit commit c00c31e5825efb7f905c38728a4f147e11c316f6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:04 2015 -0700 southbridge/amd/pi: write_hpet requires additional config option This copies what was done in southbridge/amd/agesa in: commit 56f46d8 agesa/family15tn: Switch to per-device ACPI TEST: amd/lamar. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index d15a6d1..7e2ec00 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -328,8 +328,8 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, .scan_bus = scan_static_bus,

1 0

Patch set updated for coreboot: c082a4d northbridge/amd/pi: Correct a typo in a bitwise AND
by Dave Frodin 27 Jan '15

27 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8289 -gerrit commit c082a4d87a8c8e59ac4f8f82672c3467897c712f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jan 23 07:26:14 2015 -0700 northbridge/amd/pi: Correct a typo in a bitwise AND Found-by: Clang Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 53ba694..02e32bb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1059,7 +1059,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "KaveriPI Debug: Grabbing the AMD Topology Information.\n"); AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); - modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1); + modules = (*(u32*)modules_ptr) & ((1ull << (sizeof(modules) * 8)) - 1); ASSERT(modules > 0); ASSERT(options); ioapic_count = (int)options->CfgPlatNumIoApics;

1 0

Patch set updated for coreboot: f3777d3 southbridge/amd/pi: Rework the SATA config menu
by Dave Frodin 27 Jan '15

27 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8253 -gerrit commit f3777d31fc2bb1af31be784b999e3bbf390a6e69 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jan 21 07:56:38 2015 -0700 southbridge/amd/pi: Rework the SATA config menu This change creates a config variable for each of the Hudson SATA modes to allow easier decoding of the various modes. These changes will be needed later when a hudson/bolton based board is added. Change-Id: I0d6374bd5f3befeaf4cc6cc0d069112a7e71da15 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/Kconfig | 91 +++++++++++++++++++++-------------- 1 file changed, 54 insertions(+), 37 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 9d1010f..a7d666d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -128,49 +128,66 @@ config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 -config HUDSON_SATA_MODE - int "SATA Mode" - default 0 - range 0 6 +choice + prompt "SATA Mode" + default HUDSON_SATA_IDE help Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. - 0: NATIVE mode does not require a ROM. - 1: RAID mode must have the two ROM files. - 2: AHCI may work with or without AHCI ROM. It depends on the payload support. - For example, seabios does not require the AHCI ROM. - 3: LEGACY IDE - 4: IDE to AHCI - 5: AHCI7804: ROM Required, and AMD driver required in the OS. - 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. - -comment "NATIVE" - depends on HUDSON_SATA_MODE = 0 -comment "RAID" - depends on HUDSON_SATA_MODE = 1 +config HUDSON_SATA_IDE + bool "NATIVE" + help + NATIVE is the default mode and does not require a ROM. -comment "AHCI" - depends on HUDSON_SATA_MODE = 2 +config HUDSON_SATA_RAID + bool "RAID" + help + Hudson RAID mode must have the two required ROM files. -comment "LEGACY IDE" - depends on HUDSON_SATA_MODE = 3 +config HUDSON_SATA_AHCI + bool "AHCI" + help + AHCI may work with or without AHCI ROM. It depends on the payload support. + For example, seabios does not require the AHCI ROM. -comment "IDE to AHCI" - depends on HUDSON_SATA_MODE = 4 +config HUDSON_SATA_LEGACY_IDE + bool "LEGACY IDE" + help + TODO -comment "AHCI7804" - depends on HUDSON_SATA_MODE = 5 +config HUDSON_SATA_IDE2AHCI + bool "IDE to AHCI" + help + TODO -comment "IDE to AHCI7804" - depends on HUDSON_SATA_MODE = 6 +config HUDSON_SATA_AHCI7804 + bool "AHCI7804" + help + AHCI ROM Required, and AMD driver required in the OS. -if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5 +config HUDSON_SATA_IDE2AHCI7804 + bool "IDE to AHCI7804" + help + AHCI ROM Required, and AMD driver required in the OS. +endchoice +config HUDSON_SATA_MODE + int + depends on (HUDSON_SATA_IDE || HUDSON_SATA_RAID || HUDSON_SATA_AHCI) + default "0" if HUDSON_SATA_IDE + default "1" if HUDSON_SATA_RAID + default "2" if HUDSON_SATA_AHCI + default "3" if HUDSON_SATA_LEGACY_IDE + default "4" if HUDSON_SATA_IDE2AHCI + default "5" if HUDSON_SATA_AHCI7804 + default "6" if HUDSON_SATA_IDE2AHCI7804 + +if HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 config AHCI_ROM_ID - string "AHCI device PCI IDs" - default "1022,7801" if HUDSON_SATA_MODE = 2 - default "1022,7804" if HUDSON_SATA_MODE = 5 + string "AHCI device PCI IDs" + default "1022,7801" if HUDSON_SATA_AHCI + default "1022,7804" if HUDSON_SATA_AHCI7804 config HUDSON_AHCI_ROM bool "Add a AHCI ROM" @@ -179,11 +196,9 @@ config AHCI_ROM_FILE string "AHCI ROM path and filename" depends on HUDSON_AHCI_ROM default "src/southbridge/amd/pi/hudson/ahci.bin" +endif # HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 -endif - -if HUDSON_SATA_MODE = 1 - +if HUDSON_SATA_RAID config RAID_ROM_ID string "RAID device PCI IDs" default "1022,7802" @@ -192,21 +207,23 @@ config RAID_ROM_ID config RAID_ROM_FILE string "RAID ROM path and filename" + depends on HUDSON_SATA_RAID default "src/southbridge/amd/pi/hudson/raid.bin" config RAID_MISC_ROM_FILE string "RAID Misc ROM path and filename" default "src/southbridge/amd/pi/hudson/misc.bin" + depends on HUDSON_SATA_RAID config RAID_MISC_ROM_POSITION hex "RAID Misc ROM Position" default 0xFFF00000 + depends on HUDSON_SATA_RAID help The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000. - -endif +endif # HUDSON_SATA_RAID config HUDSON_LEGACY_FREE bool "System is legacy free"

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New patch to review for coreboot: 1eb6484 northbridge/amd/pi: Correct a typo in a bitwise AND
by Dave Frodin 27 Jan '15

27 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8289 -gerrit commit 1eb6484b1072dcfe15d47cb33860cb6b7f74e004 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jan 23 07:26:14 2015 -0700 northbridge/amd/pi: Correct a typo in a bitwise AND This was found by clang. Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 53ba694..02e32bb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1059,7 +1059,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "KaveriPI Debug: Grabbing the AMD Topology Information.\n"); AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); - modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1); + modules = (*(u32*)modules_ptr) & ((1ull << (sizeof(modules) * 8)) - 1); ASSERT(modules > 0); ASSERT(options); ioapic_count = (int)options->CfgPlatNumIoApics;

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New patch to review for coreboot: dbf105f southbridge/amd/pi: write_hpet requires additional config option
by Dave Frodin 27 Jan '15

27 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8288 -gerrit commit dbf105fdfd01f5074a351052942df497f4d7b46f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:04 2015 -0700 southbridge/amd/pi: write_hpet requires additional config option This copies what was done in southbridge/amd/agesa. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index d15a6d1..7e2ec00 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -328,8 +328,8 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, .scan_bus = scan_static_bus,

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coreboot-gerrit January 2015