the following patch was just integrated into master:
commit dfc0c13b1ae1027743e80126855c615c72ffb609
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Mon Jun 16 17:02:24 2014 +1000
mainboard/jetway/nf81-t56n-lf: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6043
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/6043 for details.
-gerrit
the following patch was just integrated into master:
commit a0b4a8d8197421b6454d0614deeef1eef575bdd1
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Jun 15 14:28:23 2014 +0300
ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/6032 for details.
-gerrit
the following patch was just integrated into master:
commit c862e441627468cd8b27436a26b0153010f491c5
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jun 14 15:25:33 2014 +0300
northbridge/intel: Drop use of set_top_of_ram()
We implement get_top_of_ram() on these chipset to resolve CBMEM
location early in romstage. Call to set_top_ram() is not required.
Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6031 for details.
-gerrit
the following patch was just integrated into master:
commit 191d221920143d47032997c48654f0d74e83e86e
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Jun 15 12:06:12 2014 +0300
intel/nehalem: Add get_top_top_ram() in ramstage
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
set_top_of_ram() will no longer be available.
Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/6030 for details.
-gerrit
the following patch was just integrated into master:
commit aac45febc78c2e3254fc6ed58ad8b81ce59bbf26
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Jun 15 12:00:08 2014 +0300
emulation/x86 : Drop HAVE_ACPI_RESUME
S3 resume detection not implemented in romstage.c.
Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6028 for details.
-gerrit
the following patch was just integrated into master:
commit a1e924ca6b5c8ce84625ac525db117391e5f872f
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jun 6 08:32:42 2014 +0300
mainboard/supermicro/h8dme: Drop unused code
Clang complains about a unused debug function, so remove dead code.
We have copy of dump_smbus_registers() in amdk8/debug.c.
Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5942
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/5942 for details.
-gerrit
the following patch was just integrated into master:
commit f565ab0e2500090f9392d83c7b0e8b8bbab67ce4
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat May 31 17:08:40 2014 +0300
lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
Use the value from hardware for uma_memory_base.
Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/5893 for details.
-gerrit
Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5963
-gerrit
commit af9cf7f4511f202a8ac753b52e0962948b0a7b8e
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Mon Jun 9 12:33:24 2014 -0600
superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/superio/nuvoton/Makefile.inc | 1 +
src/superio/nuvoton/nct5104d/early_serial.c | 77 +++++++++++++++++++++++++++++
src/superio/nuvoton/nct5104d/nct5104d.h | 8 +--
3 files changed, 83 insertions(+), 3 deletions(-)
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index 1ce6963..6fd1266 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -19,6 +19,7 @@
## include generic nuvoton pre-ram stage driver
romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c
+romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d/early_serial.c
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
diff --git a/src/superio/nuvoton/nct5104d/early_serial.c b/src/superio/nuvoton/nct5104d/early_serial.c
new file mode 100644
index 0000000..2d63268
--- /dev/null
+++ b/src/superio/nuvoton/nct5104d/early_serial.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * A generic romstage (pre-ram) driver for Nuvoton variant Super I/O chips.
+ *
+ * The following is derived directly from the vendor Nuvoton's data-sheets:
+ *
+ * To toggle between `configuration mode` and `normal operation mode` as to
+ * manipulate the various LDN's in Nuvoton Super I/O's we are required to
+ * pass magic numbers `passwords keys`.
+ *
+ * NUVOTON_ENTRY_KEY := enable configuration : 0x87
+ * NUVOTON_EXIT_KEY := disable configuration : 0xAA
+ *
+ * To modify a LDN's configuration register, we use the index port to select
+ * the index of the LDN and then write to the data port to alter the
+ * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a
+ * user modified pair is 0x2E, 0x2F respectively.
+ *
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+#include "nct5104d.h"
+
+#define NUVOTON_ENTRY_KEY 0x87
+#define NUVOTON_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0x87' into index port dev
+ * two times. */
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(NUVOTON_ENTRY_KEY, port);
+ outb(NUVOTON_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(NUVOTON_EXIT_KEY, port);
+}
+
+/* Route UARTD to pins 41-48 */
+void nuvoton_enable_uartd(device_t dev)
+{
+ u8 tmp;
+ u16 port = dev >> 8;
+ pnp_enter_conf_state(dev);
+ outb(0x1c, port);
+ tmp = inb(port + 1);
+ tmp |= 0x04;
+ outb(tmp, port + 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h
index b72dda0..f6a0387 100644
--- a/src/superio/nuvoton/nct5104d/nct5104d.h
+++ b/src/superio/nuvoton/nct5104d/nct5104d.h
@@ -19,8 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_NUVOTON_NCT5104D_NCT5104D_H
-#define SUPERIO_NUVOTON_NCT5104D_NCT5104D_H
+#ifndef SUPERIO_NUVOTON_NCT5104D_H
+#define SUPERIO_NUVOTON_NCT5104D_H
/* Logical Device Numbers (LDN). */
#define NCT5104D_FDC 0x00 /* FDC - not pinned out */
@@ -42,4 +42,6 @@
#define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V)
#define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V)
-#endif /* SUPERIO_NUVOTON_NCT5104D_NCT5104D_H */
+void nuvoton_enable_uartd(device_t dev);
+
+#endif /* SUPERIO_NUVOTON_NCT5104D_H */