Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5963
-gerrit
commit a8bb7861f85d99041d69cd62bcf58e2aa8f8795f
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Mon Jun 9 12:33:24 2014 -0600
superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/superio/nuvoton/nct5104d/Makefile.inc | 1 +
src/superio/nuvoton/nct5104d/early_init.c | 56 +++++++++++++++++++++++++++++++
src/superio/nuvoton/nct5104d/nct5104d.h | 8 +++--
3 files changed, 62 insertions(+), 3 deletions(-)
diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc
index fcb5ec2..b6278ba 100644
--- a/src/superio/nuvoton/nct5104d/Makefile.inc
+++ b/src/superio/nuvoton/nct5104d/Makefile.inc
@@ -19,3 +19,4 @@
##
ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c
+romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c
diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c
new file mode 100644
index 0000000..c9a408e
--- /dev/null
+++ b/src/superio/nuvoton/nct5104d/early_init.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+#include "nct5104d.h"
+
+#define NUVOTON_ENTRY_KEY 0x87
+#define NUVOTON_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0x87' into index port dev
+ * two times. */
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(NUVOTON_ENTRY_KEY, port);
+ outb(NUVOTON_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(NUVOTON_EXIT_KEY, port);
+}
+
+/* Route UARTD to pins 41-48 */
+void nct5104d_enable_uartd(device_t dev)
+{
+ u8 tmp;
+ u16 port = dev >> 8;
+ pnp_enter_conf_state(dev);
+ outb(0x1c, port);
+ tmp = inb(port + 1);
+ tmp |= 0x04;
+ outb(tmp, port + 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h
index b72dda0..74df793 100644
--- a/src/superio/nuvoton/nct5104d/nct5104d.h
+++ b/src/superio/nuvoton/nct5104d/nct5104d.h
@@ -19,8 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_NUVOTON_NCT5104D_NCT5104D_H
-#define SUPERIO_NUVOTON_NCT5104D_NCT5104D_H
+#ifndef SUPERIO_NUVOTON_NCT5104D_H
+#define SUPERIO_NUVOTON_NCT5104D_H
/* Logical Device Numbers (LDN). */
#define NCT5104D_FDC 0x00 /* FDC - not pinned out */
@@ -42,4 +42,6 @@
#define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V)
#define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V)
-#endif /* SUPERIO_NUVOTON_NCT5104D_NCT5104D_H */
+void nct5104d_enable_uartd(device_t dev);
+
+#endif /* SUPERIO_NUVOTON_NCT5104D_H */
the following patch was just integrated into master:
commit 17290e4b6c80528baac1bcb5c2e33dbb5aa509be
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jun 13 11:21:13 2014 +0300
intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INIT
This is implied from DYNAMIC_CBMEM from soc/.
Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6029
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer(a)gmail.com>
Reviewed-by: Martin Roth <gaumless(a)gmail.com>
See http://review.coreboot.org/6029 for details.
-gerrit
the following patch was just integrated into master:
commit de38eeaaa6d27b25efc5c7c8ea2b09090f9241f0
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Thu Jun 12 12:31:59 2014 -0600
fsp_baytrail: Add the default FSP location
The default FSP location needs to be in the chipset, not the mainboard.
This was removed from the Bayley Bay mainboard in patch 41ea7230f7
reviewed at http://review.coreboot.org/#/c/5982/
Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5985
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/5985 for details.
-gerrit
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5985
-gerrit
commit 19a7f66159441dac207f5d246f0a2e4200f69a49
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Thu Jun 12 12:31:59 2014 -0600
fsp_baytrail: Add the default FSP location
The default FSP location needs to be in the chipset, not the mainboard.
This was removed from the Bayley Bay mainboard in patch 41ea7230f7
reviewed at http://review.coreboot.org/#/c/5982/
Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/soc/intel/fsp_baytrail/fsp/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig
index 5df6374..0949325 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Kconfig
+++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig
@@ -29,3 +29,13 @@ config FSP_FILE
help
The path and filename of the Intel FSP binary for this platform.
+config FSP_LOC
+ hex "Intel FSP Binary location in CBFS"
+ default 0xfffc0000
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with the Intel's BCT (tool).
+
+ The Bay Trail FSP is built with a preferred base address of
+ 0xFFFC0000.
the following patch was just integrated into master:
commit c0602d4cab34ee228465c2779dda400b367082b6
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Thu Jun 12 12:38:34 2014 -0600
fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were
released as a "Super SKU" which had features of all the different
SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
number 2 in the third character from the left in the microcode name.
- Update the size of the microcode blob. We should be pushing a patch
to eliminate the need for this shortly.
Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
See http://review.coreboot.org/5986 for details.
-gerrit
the following patch was just integrated into master:
commit c94d73e0e6703369831fe6d489a20d71ab2bb974
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Mon Jun 16 17:24:14 2014 +1000
mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.
Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/6045 for details.
-gerrit
the following patch was just integrated into master:
commit 401b8accf8fdade02f40f528812ac081c7a0f432
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Mon Jun 16 17:09:27 2014 +1000
mainboard/amd,lippert: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/6044 for details.
-gerrit