Patch merged into coreboot/master: 0f5cf5e PCI IRQs: Swizzle PCI IRQs for PCI bridges
by gerrit＠coreboot.org 29 May '14
by gerrit＠coreboot.org 29 May '14
29 May '14
the following patch was just integrated into master:
commit 0f5cf5e45b78d2e6a91d978bb86de5a4ff07c4d5
Author: Mike Loptien <loptienm(a)gmail.com>
Date: Mon May 12 21:46:31 2014 -0600
PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien(a)se-eng.com>
See http://review.coreboot.org/5734 for details.
-gerrit
1
0
Patch merged into coreboot/master: 433659a fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
by gerrit＠coreboot.org 29 May '14
by gerrit＠coreboot.org 29 May '14
29 May '14
the following patch was just integrated into master:
commit 433659ad1e864808ec30e90a62ecfd711559c5a9
Author: Martin Roth <gaumless(a)gmail.com>
Date: Mon May 12 21:55:00 2014 -0600
fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91
Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/5791 for details.
-gerrit
1
0
Patch set updated for coreboot: 12523e2 PCI IRQs: Swizzle PCI IRQs for PCI bridges
by Martin Roth 29 May '14
by Martin Roth 29 May '14
29 May '14
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5734
-gerrit
commit 12523e206e456290c7f7012dfa24627a63f828cc
Author: Mike Loptien <loptienm(a)gmail.com>
Date: Mon May 12 21:46:31 2014 -0600
PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
src/device/pci_device.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
src/include/device/pci.h | 2 +
2 files changed, 153 insertions(+)
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index f09fcaa..3a54c2d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -12,6 +12,7 @@
* (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan)
* Copyright (C) 2005-2009 coresystems GmbH
* (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH)
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
*/
/*
@@ -1303,6 +1304,156 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
return max;
}
+/**
+ * Take an INT_PIN number (0, 1 - 4) and convert
+ * it to a string ("NO PIN", "PIN A" - "PIN D")
+ *
+ * @param pin PCI Interrupt Pin number (0, 1 - 4)
+ * @return A string corresponding to the pin number or "Invalid"
+ */
+const char *pin_to_str(int pin)
+{
+ const char *str[5] = {
+ "NO PIN",
+ "PIN A",
+ "PIN B",
+ "PIN C",
+ "PIN D",
+ };
+
+ if (pin >= 0 && pin <= 4)
+ return str[pin];
+ else
+ return "Invalid PIN, not 0 - 4";
+}
+
+/**
+ * Get the PCI INT_PIN swizzle for a device defined as:
+ * pin_parent = (pin_child + devn_child) % 4 + 1
+ * where PIN A = 1 ... PIN_D = 4
+ *
+ * Given a PCI device structure 'dev', find the interrupt pin
+ * that will be triggered on its parent bridge device when
+ * generating an interrupt. For example: Device 1:3.2 may
+ * use INT_PIN A but will trigger PIN D on its parent bridge
+ * device. In this case, this function will return 4 (PIN D).
+ *
+ * @param dev A PCI device structure to swizzle interrupt pins for
+ * @param *parent_bdg The PCI device structure for the bridge
+ * device 'dev' is attached to
+ * @return The interrupt pin number (1 - 4) that 'dev' will
+ * trigger when generating an interrupt
+ */
+static int swizzle_irq_pins(device_t dev, device_t *parent_bridge)
+{
+ device_t parent; /* Our current device's parent device */
+ device_t child; /* The child device of the parent */
+ uint8_t parent_bus = 0; /* Parent Bus number */
+ uint16_t parent_devfn = 0; /* Parent Device and Function number */
+ uint16_t child_devfn = 0; /* Child Device and Function number */
+ uint8_t swizzled_pin = 0; /* Pin swizzled across a bridge */
+
+ /* Start with PIN A = 0 ... D = 3 */
+ swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1;
+
+ /* While our current device has parent devices */
+ child = dev;
+ for (parent = child->bus->dev; parent; parent = parent->bus->dev) {
+ parent_bus = parent->bus->secondary;
+ parent_devfn = parent->path.pci.devfn;
+ child_devfn = child->path.pci.devfn;
+
+ /* Swizzle the INT_PIN for any bridges not on root bus */
+ swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4;
+ printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n"
+ "\tAttached to bridge device %01X:%02Xh.%02Xh\n",
+ pin_to_str(swizzled_pin + 1), parent_bus,
+ PCI_SLOT(parent_devfn), PCI_FUNC(parent_devfn));
+
+ /* Continue until we find the root bus */
+ if (parent_bus > 0) {
+ /*
+ * We will go on to the next parent so this parent
+ * becomes the child
+ */
+ child = parent;
+ continue;
+ } else {
+ /*
+ * Found the root bridge device,
+ * fill in the structure and exit
+ */
+ *parent_bridge = parent;
+ break;
+ }
+ }
+
+ /* End with PIN A = 1 ... D = 4 */
+ return swizzled_pin + 1;
+}
+
+/**
+ * Given a device structure 'dev', find its interrupt pin
+ * and its parent bridge 'parent_bdg' device structure.
+ * If it is behind a bridge, it will return the interrupt
+ * pin number (1 - 4) of the parent bridge that the device
+ * interrupt pin has been swizzled to, otherwise it will
+ * return the interrupt pin that is programmed into the
+ * PCI config space of the target device. If 'dev' is
+ * behind a bridge, it will fill in 'parent_bdg' with the
+ * device structure of the bridge it is behind, otherwise
+ * it will copy 'dev' into 'parent_bdg'.
+ *
+ * @param dev A PCI device structure to get interrupt pins for.
+ * @param *parent_bdg The PCI device structure for the bridge
+ * device 'dev' is attached to.
+ * @return The interrupt pin number (1 - 4) that 'dev' will
+ * trigger when generating an interrupt.
+ * Errors: -1 is returned if the device is not enabled
+ * -2 is returned if a parent bridge could not be found.
+ */
+int get_pci_irq_pins(device_t dev, device_t *parent_bdg)
+{
+ uint8_t bus = 0; /* The bus this device is on */
+ uint16_t devfn = 0; /* This device's device and function numbers */
+ uint8_t int_pin = 0; /* Interrupt pin used by the device */
+ uint8_t target_pin = 0; /* Interrupt pin we want to assign an IRQ to */
+
+ /* Make sure this device is enabled */
+ if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI)))
+ return -1;
+
+ bus = dev->bus->secondary;
+ devfn = dev->path.pci.devfn;
+
+ /* Get and validate the interrupt pin used. Only 1-4 are allowed */
+ int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ if (int_pin < 1 || int_pin > 4)
+ return -1;
+
+ printk(BIOS_SPEW, "PCI IRQ: Found device %01X:%02X.%02X using %s\n",
+ bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pin_to_str(int_pin));
+
+ /* If this device is on a bridge, swizzle its INT_PIN */
+ if (bus) {
+ /* Swizzle its INT_PINs */
+ target_pin = swizzle_irq_pins(dev, parent_bdg);
+
+ /* Make sure the swizzle returned valid structures */
+ if (parent_bdg == NULL) {
+ printk(BIOS_WARNING,
+ "Warning: Could not find parent bridge for this device!\n");
+ return -2;
+ }
+ } else { /* Device is not behind a bridge */
+ target_pin = int_pin; /* Return its own interrupt pin */
+ *parent_bdg = dev; /* Return its own structure */
+ }
+
+ /* Target pin is the interrupt pin we want to assign an IRQ to */
+ return target_pin;
+}
+
#if CONFIG_PC80_SYSTEM
/**
* Assign IRQ numbers.
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 5594d29..8175970 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -82,6 +82,8 @@ void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
void pci_dev_init(struct device *dev);
unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev);
+const char * pin_to_str(int pin);
+int get_pci_irq_pins(device_t dev, device_t *parent_bdg);
void pci_assign_irqs(unsigned bus, unsigned slot,
const unsigned char pIntAtoD[4]);
1
0
Patch merged into coreboot/master: 2a9b2ed drivers/intel/fsp: update enable_mrc_cache with fast boot
by gerrit＠coreboot.org 29 May '14
by gerrit＠coreboot.org 29 May '14
29 May '14
the following patch was just integrated into master:
commit 2a9b2ed3ff5411d0efdbde3b9ba1d1de06ab09aa
Author: Martin Roth <gaumless(a)gmail.com>
Date: Mon May 19 15:30:00 2014 -0600
drivers/intel/fsp: update enable_mrc_cache with fast boot
When going from a configuration with fast boot disabled to one with
it enabled, ENABLE_MRC_CACHE was not being enabled properly. This
forces it on with ENABLE_FSP_FAST_BOOT.
Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/5794 for details.
-gerrit
1
0
Patch merged into coreboot/master: 7312c54 add rtc_init() to romstage
by gerrit＠coreboot.org 29 May '14
by gerrit＠coreboot.org 29 May '14
29 May '14
the following patch was just integrated into master:
commit 7312c54dc684099a6d85ae13f3de097754ced0f0
Author: Martin Roth <gaumless(a)gmail.com>
Date: Mon May 12 21:52:54 2014 -0600
add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5735 for details.
-gerrit
1
0
29 May '14
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5735
-gerrit
commit 4ba47f88dc3326f870be443f43837463662f468f
Author: Martin Roth <gaumless(a)gmail.com>
Date: Mon May 12 21:52:54 2014 -0600
add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/drivers/pc80/Makefile.inc | 1 +
src/drivers/pc80/mc146818rtc.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc
index 4d0a280..d216e2c 100644
--- a/src/drivers/pc80/Makefile.inc
+++ b/src/drivers/pc80/Makefile.inc
@@ -1,3 +1,4 @@
+romstage-y += mc146818rtc.c
ramstage-y += mc146818rtc.c
ramstage-y += isa-dma.c
ramstage-y += i8254.c
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index 51cd6c3..6f8a4eb 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -71,6 +71,7 @@ void rtc_init(int invalid)
unsigned char x;
#endif
+#ifndef __PRE_RAM__
#if CONFIG_HAVE_ACPI_RESUME
/*
* Avoid clearing pending interrupts and resetting the RTC control
@@ -80,7 +81,8 @@ void rtc_init(int invalid)
*/
if (acpi_slp_type == 3)
return;
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+#endif /* __PRE_RAM__ */
printk(BIOS_DEBUG, "RTC Init\n");
1
0
29 May '14
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5735
-gerrit
commit c12d1625e24bd0f6c7d5ef474b81455aca08cbf8
Author: Martin Roth <gaumless(a)gmail.com>
Date: Mon May 12 21:52:54 2014 -0600
add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/drivers/pc80/Makefile.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc
index 4d0a280..d216e2c 100644
--- a/src/drivers/pc80/Makefile.inc
+++ b/src/drivers/pc80/Makefile.inc
@@ -1,3 +1,4 @@
+romstage-y += mc146818rtc.c
ramstage-y += mc146818rtc.c
ramstage-y += isa-dma.c
ramstage-y += i8254.c
1
0
Patch set updated for coreboot: 07b5830 sandy/ivybridge: Native raminit.
by Vladimir Serbinenko 29 May '14
by Vladimir Serbinenko 29 May '14
29 May '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5786
-gerrit
commit 07b583055ce3b1c12b62926d50f6a61bf7139a2d
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun May 18 11:05:56 2014 +0200
sandy/ivybridge: Native raminit.
Based on damo22 work and my X230 tracing.
Works for my X230 in a variety of RAM configs.
Also-By: Damien Zammit <damien(a)zamaudio.com>
Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/device/dram/ddr3.c | 8 +-
src/include/device/dram/ddr3.h | 11 +-
src/mainboard/lenovo/x230/Kconfig | 4 -
src/mainboard/lenovo/x230/romstage.c | 72 +-
src/northbridge/intel/sandybridge/Kconfig | 2 +-
src/northbridge/intel/sandybridge/Makefile.inc | 2 +
src/northbridge/intel/sandybridge/pchinit.c | 549 ++++
src/northbridge/intel/sandybridge/raminit.c | 3769 ++++++++++++++++++++++--
src/northbridge/intel/sandybridge/raminit.h | 16 +-
src/southbridge/intel/bd82x6x/early_me.c | 122 +-
10 files changed, 4269 insertions(+), 286 deletions(-)
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index 9b4f490..69782ab 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -110,7 +110,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
{
int ret;
u16 crc, spd_crc;
- u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width, sdram_width;
+ u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width;
u8 reg8;
u32 mtb; /* medium time base */
unsigned int val, param;
@@ -209,8 +209,8 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
printram(" Invalid SDRAM width\n");
ret = SPD_STATUS_INVALID_FIELD;
}
- sdram_width = (4 << val);
- printram(" SDRAM width : %u\n", sdram_width);
+ dimm->width = (4 << val);
+ printram(" SDRAM width : %u\n", dimm->width);
/* Memory bus width */
reg8 = spd[8];
@@ -236,7 +236,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
* capacity_shift
* The rest is the JEDEC formula */
dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width
- * dimm->ranks) / sdram_width;
+ * dimm->ranks) / dimm->width;
/* Fine Timebase (FTB) Dividend/Divisor */
/* Dividend */
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index b19c51c..fcaf10b 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -37,6 +37,7 @@
* @{
*/
#define TCK_1066MHZ 240
+#define TCK_933MHZ 275
#define TCK_800MHZ 320
#define TCK_666MHZ 384
#define TCK_533MHZ 480
@@ -54,11 +55,11 @@
* disabled.
* @{
*/
-#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP)
+//#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP)
#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
-#else
-#define printram(x, ...)
-#endif
+//#else
+//#define printram(x, ...)
+//#endif
/** @} */
/*
@@ -137,6 +138,8 @@ typedef struct dimm_attr_st {
u16 cas_supported;
/* Flags extracted from SPD */
dimm_flags_t flags;
+ /* SDRAM width */
+ u8 width;
/* Number of ranks */
u8 ranks;
/* Number or row address bits */
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 1e4f90b..6721118 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -49,10 +49,6 @@ config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config IRQ_SLOT_COUNT
int
default 18
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 6e4e685..dba19b1 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -114,60 +114,13 @@ void main(unsigned long bist)
int cbmem_was_initted;
u32 pm1_cnt;
u16 pm1_sts;
+ spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
hlt ();
}
- struct pei_data pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xA0, 0x00,0xA2,0x00 },
- .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- .gbe_enable = 1,
- .ddr3lv_support = 0,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
- .max_ddr3_freq = 1600,
- .usb_port_config = {
- /* enabled usb oc pin length */
- { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */
- { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */
- { 1, 3, 0x0080 }, /* P2: dock, OC 3 */
- { 1, 0, 0x0040 }, /* P3: wwan, no OC */
- { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */
- { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */
- { 0, 0, 0x0000 }, /* P6: Empty */
- { 1, 0, 0x0080 }, /* P7: dock, no OC */
- { 0, 0, 0x0000 }, /* P8: Empty */
- { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */
- { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */
- { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */
- { 1, 0, 0x0040 }, /* P12: wlan, no OC */
- { 1, 0, 0x0080 }, /* P13: webcam, no OC */
- },
- .ddr_refresh_rate_config = 2, /* Force double refresh rate */
- };
-
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
@@ -224,24 +177,13 @@ void main(unsigned long bist)
post_code(0x39);
post_code(0x3a);
- pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
- /* MRC.bin has a bug and sometimes halts (instead of reboot?).
- */
- if (boot_mode != 2)
- {
- RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
- outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
- }
-
- sdram_initialize(&pei_data);
+ memset (spd, 0, sizeof (spd));
+ read_spd (&spd[0], 0x50);
+ read_spd (&spd[2], 0x51);
- if (boot_mode != 2)
- {
- RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
- outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
- }
+ init_dram_ddr3 (spd, 1);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
@@ -254,8 +196,8 @@ void main(unsigned long bist)
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
- if (boot_mode!=2)
- save_mrc_data(&pei_data);
+// if (boot_mode!=2)
+// save_mrc_data(&pei_data);
#if CONFIG_HAVE_ACPI_RESUME
/* If there is no high memory area, we didn't boot before, so
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index fb92e40..1d60f5a 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -52,7 +52,7 @@ config MRC_CACHE_SIZE
config DCACHE_RAM_BASE
hex
- default 0xff7e0000
+ default 0xfefe0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 6655e2a..707a8d0 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -27,6 +27,8 @@ ramstage-y += mrccache.c
romstage-y += ram_calc.c
romstage-y += raminit.c
+romstage-y += pchinit.c
+romstage-y += ../../../device/dram/ddr3.c
romstage-y += mrccache.c
romstage-y += early_init.c
romstage-y += report_platform.c
diff --git a/src/northbridge/intel/sandybridge/pchinit.c b/src/northbridge/intel/sandybridge/pchinit.c
new file mode 100644
index 0000000..72fd156
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pchinit.c
@@ -0,0 +1,549 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <arch/cbfs.h>
+#include <cbfs.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include "raminit.h"
+#include "pei_data.h"
+#include "sandybridge.h"
+#include <delay.h>
+
+/* Management Engine is in the southbridge */
+#include "southbridge/intel/bd82x6x/me.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <cpu/x86/msr.h>
+#include <cpu/cpu.h>
+#include "cpu/intel/model_2065x/model_2065x.h"
+
+#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
+
+static void
+wait_2338 (void)
+{
+ while (read8 (DEFAULT_RCBABASE | 0x2338) & 1);
+}
+
+static u32
+read_2338 (u32 edx)
+{
+ u32 ret;
+
+ write32 (DEFAULT_RCBABASE | 0x2330, edx);
+ write16 (DEFAULT_RCBABASE | 0x2338, (read16 (DEFAULT_RCBABASE | 0x2338)
+ & 0x1ff) | 0x600);
+ wait_2338 ();
+ ret = read32 (DEFAULT_RCBABASE | 0x2334);
+ wait_2338 ();
+ read8 (DEFAULT_RCBABASE | 0x2338);
+ return ret;
+}
+
+static void
+write_2338 (u32 edx, u32 val)
+{
+ read_2338 (edx);
+ write16 (DEFAULT_RCBABASE | 0x2338, (read16 (DEFAULT_RCBABASE | 0x2338)
+ & 0x1ff) | 0x600);
+ wait_2338 ();
+
+ write32 (DEFAULT_RCBABASE | 0x2334, val);
+ wait_2338 ();
+ write16 (DEFAULT_RCBABASE | 0x2338,
+ (read16 (DEFAULT_RCBABASE | 0x2338) & 0x1ff) | 0x600);
+ read8 (DEFAULT_RCBABASE | 0x2338);
+}
+
+#define USB_ACC_CONTROL 0x80
+
+static void
+init_usb (void)
+{
+ u32 base;
+ read32 (DEFAULT_RCBABASE | 0x3418); // !!! = 0x06000000
+ pcie_read_config16 (SOUTHBRIDGE, 0x40); // !!! = 0x0501
+ read32 (DEFAULT_RCBABASE | 0x3598); // !!! = 0x00000000
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0x10); // !!! = 0x00000000
+ pcie_read_config16 (PCI_DEV (0, 0x1d, 0), 0x04); // !!! = 0x0000
+ base = 0xe8000000;
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0x10, base);
+ pcie_read_config16 (PCI_DEV (0, 0x1d, 0), 0x04); // !!! = 0x0000
+ pcie_write_config16 (PCI_DEV (0, 0x1d, 0), 0x04, 0x0006);
+
+ pcie_write_config16 (PCI_DEV (0, 0x1d, 0), USB_ACC_CONTROL,
+ pcie_read_config16 (PCI_DEV (0, 0x1d, 0),
+ USB_ACC_CONTROL) | 1);
+ read32 (base + 4); // !!! = 0x00204008
+ write32 (base + 4, 0x00200008);
+ read32 (base + 4); // !!! = 0x00200008
+ write32 (base + 4, 0x00200003);
+ pcie_write_config16 (PCI_DEV (0, 0x1d, 0), USB_ACC_CONTROL,
+ pcie_read_config16 (PCI_DEV (0, 0x1d, 0),
+ USB_ACC_CONTROL) & ~1);
+ read32 (0xe8000024); // !!! = 0x00001000
+ write16 (0xe8000020, read16 (0xe8000020) | 2);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0x84); // !!! = 0x83088e01
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0x84, 0x930c8811);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0x88); // !!! = 0x04000030
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0x88, 0x24000d30);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0xf4); // !!! = 0x00408588
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0xf4, 0x80408588);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0xf4); // !!! = 0x80408588
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0xf4, 0x80808588);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0xf4); // !!! = 0x80808588
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0xf4, 0x00808588);
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0xfc); // !!! = 0x20591708
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0xfc, 0x205b1708);
+ write32 (DEFAULT_RCBABASE | 0x3560,
+ read32 (DEFAULT_RCBABASE | 0x3560) | 0x20c8000);
+ pcie_read_config16 (PCI_DEV (0, 0x1d, 0), 0x04); // !!! = 0x0006
+ pcie_write_config16 (PCI_DEV (0, 0x1d, 0), 0x04, 0x0000);
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0x10, 0x00000000);
+ base = 0xfef00000;
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0x10); // !!! = 0xfef00000
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0x10); // !!! = 0xfef00000
+ pcie_read_config16 (PCI_DEV (0, 0x1a, 0), 0x04); // !!! = 0x0002
+ pcie_read_config16 (PCI_DEV (0, 0x1a, 0), 0x04); // !!! = 0x0002
+ pcie_write_config16 (PCI_DEV (0, 0x1a, 0), 0x04, 0x0006);
+ pcie_write_config16 (PCI_DEV (0, 0x1a, 0), 0x80,
+ pcie_read_config16 (PCI_DEV (0, 0x1a, 0), 0x80) | 1);
+ read32 (base + 4); // !!! = 0x00203006
+ write32 (base + 4, 0x00200006);
+ read32 (base + 4); // !!! = 0x00200006
+ write32 (base + 4, 0x00200003);
+ pcie_write_config16 (PCI_DEV (0, 0x1a, 0), USB_ACC_CONTROL,
+ pcie_read_config16 (PCI_DEV (0, 0x1a, 0),
+ USB_ACC_CONTROL) & ~1);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0x84); // !!! = 0x83088e01
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0x84, 0x930c8811);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0x88); // !!! = 0x04000030
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0x88, 0x24000d30);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0xf4); // !!! = 0x00408588
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0xf4, 0x80408588);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0xf4); // !!! = 0x80408588
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0xf4, 0x80808588);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0xf4); // !!! = 0x80808588
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0xf4, 0x00808588);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0xfc); // !!! = 0x20591708
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0xfc, 0x205b1708);
+ write32 (DEFAULT_RCBABASE | 0x3560,
+ read32 (DEFAULT_RCBABASE | 0x3560) | 0x20c8000);
+ pcie_write_config16 (PCI_DEV (0, 0x1a, 0), 0x04, 0x0002);
+
+ pcie_read_config16 (SOUTHBRIDGE, 0x02); // !!! = 0x1e55
+ outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
+ u16 reg_359c = 0x150;
+ int i;
+ for (i = 0; i < 14; i++)
+ if (reg_359c & (1 << i))
+ write16 (DEFAULT_RCBABASE | 0x359c,
+ read16 (DEFAULT_RCBABASE | 0x359c) | (1 << i));
+ else
+ write16 (DEFAULT_RCBABASE | 0x359c,
+ read16 (DEFAULT_RCBABASE | 0x359c) & ~(1 << i));
+ pcie_read_config8 (SOUTHBRIDGE, 0x08); // !!! = 0x04
+ pcie_read_config16 (SOUTHBRIDGE, 0x02); // !!! = 0x1e55
+ pcie_read_config32 (PCI_DEV (0, 0x14, 0), 0xe4); // !!! = 0x00000000
+ pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+ outw (0x0000, DEFAULT_PMBASE | 0x003c);
+ write32 (DEFAULT_RCBABASE | 0x3418, 0x16001fe0);
+ read32 (DEFAULT_RCBABASE | 0x3418); // !!! = 0x16001fe0
+}
+
+static void
+init_thermal (void)
+{
+ /* OK { */
+ pcie_write_config32 (PCI_DEV (0, 0x1f, 6), 0x40, 0xfed08000);
+ pcie_write_config32 (PCI_DEV (0, 0x1f, 6), 0x44, 0x00000000);
+ pcie_read_config32 (PCI_DEV (0, 0x1f, 6), 0x40); // !!! = 0xfed08004
+ pcie_write_config32 (PCI_DEV (0, 0x1f, 6), 0x40, 0xfed08005);
+ write16 (0xfed08004, 0x3a2b);
+ write8 (0xfed0800c, 0xff);
+ write8 (0xfed0800d, 0x00);
+ write8 (0xfed0800e, 0x40);
+ write8 (0xfed08082, 0x00);
+ write8 (0xfed08001, 0xba);
+ msr_t msr;
+ msr = rdmsr (MSR_TEMPERATURE_TARGET); // !!! = 0x0000000000691200
+ write16 (0xfed08012, ((msr.lo >> 16) & 0xff) << 6);
+ write16 (0xfed08016, 0x808c);
+
+
+ write32 (DEFAULT_RCBABASE | 0x38b0,
+ (read32 (DEFAULT_RCBABASE | 0x38b0) & 0xffff8003) | 0x403c);
+
+ write16 (0xfed08014, 0xde87);
+ /* } OK */
+ if (read32 (DEFAULT_RCBABASE | 0x38b4) & 0x4000) // !!! = 0x0000437e
+ write16 (0xfed0801a, 0x0000);
+ else
+ {
+ /* ? */
+ }
+ pcie_read_config32 (PCI_DEV (0, 0x1f, 6), 0x40); // !!! = 0xfed08005
+ pcie_write_config32 (PCI_DEV (0, 0x1f, 6), 0x40, 0xfed08004);
+ pcie_write_config32 (PCI_DEV (0, 0x1f, 6), 0x40, 0x00000000);
+}
+
+void
+pch_init (void)
+{
+ int i;
+
+ /* Undocumented. */
+ pcie_write_config8 (SOUTHBRIDGE, 0xa6,
+ pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
+
+ write32 (DEFAULT_RCBABASE | 0x2088, 0x00109000);
+ read32 (DEFAULT_RCBABASE | 0x20ac); // !!! = 0x00000000
+ write32 (DEFAULT_RCBABASE | 0x20ac, 0x40000000);
+ write32 (DEFAULT_RCBABASE | 0x100c, 0x01110000);
+ write8 (DEFAULT_RCBABASE | 0x2340, 0x1b);
+ read32 (DEFAULT_RCBABASE | 0x2314); // !!! = 0x0a080000
+ write32 (DEFAULT_RCBABASE | 0x2314, 0x0a280000);
+ read32 (DEFAULT_RCBABASE | 0x2310); // !!! = 0xc809605b
+ write32 (DEFAULT_RCBABASE | 0x2310, 0xa809605b);
+ write32 (DEFAULT_RCBABASE | 0x2324, 0x00854c74);
+ read8 (DEFAULT_RCBABASE | 0x0400); // !!! = 0x00
+ read32 (DEFAULT_RCBABASE | 0x2310); // !!! = 0xa809605b
+ write32 (DEFAULT_RCBABASE | 0x2310, 0xa809605b);
+ read32 (DEFAULT_RCBABASE | 0x2310); // !!! = 0xa809605b
+ write32 (DEFAULT_RCBABASE | 0x2310, 0xa809605b);
+
+ write_2338 (0xea007f62, 0x00590133);
+ write_2338 (0xec007f62, 0x00590133);
+ write_2338 (0xec007f64, 0x59555588);
+ write_2338 (0xea0040b9, 0x0001051c);
+ write_2338 (0xeb0040a1, 0x800084ff);
+ write_2338 (0xec0040a1, 0x800084ff);
+ write_2338 (0xea004001, 0x00008400);
+ write_2338 (0xeb004002, 0x40201758);
+ write_2338 (0xec004002, 0x40201758);
+ write_2338 (0xea004002, 0x00601758);
+ write_2338 (0xea0040a1, 0x810084ff);
+ write_2338 (0xeb0040b1, 0x0001c598);
+ write_2338 (0xec0040b1, 0x0001c598);
+ write_2338 (0xeb0040b6, 0x0001c598);
+ write_2338 (0xea0000a9, 0x80ff969f);
+ write_2338 (0xea0001a9, 0x80ff969f);
+ write_2338 (0xeb0040b2, 0x0001c396);
+ write_2338 (0xeb0040b3, 0x0001c396);
+ write_2338 (0xec0040b2, 0x0001c396);
+ write_2338 (0xea0001a9, 0x80ff94ff);
+ write_2338 (0xea000151, 0x0088037f);
+ write_2338 (0xea0000a9, 0x80ff94ff);
+ write_2338 (0xea000051, 0x0088037f);
+
+ write_2338 (0xea007f05, 0x00010642);
+ write_2338 (0xea0040b7, 0x0001c91c);
+ write_2338 (0xea0040b8, 0x0001c91c);
+ write_2338 (0xeb0040a1, 0x820084ff);
+ write_2338 (0xec0040a1, 0x820084ff);
+ write_2338 (0xea007f0a, 0xc2480000);
+
+ write_2338 (0xec00404d, 0x1ff177f);
+ write_2338 (0xec000084, 0x5a600000);
+ write_2338 (0xec000184, 0x5a600000);
+ write_2338 (0xec000284, 0x5a600000);
+ write_2338 (0xec000384, 0x5a600000);
+ write_2338 (0xec000094, 0x000f0501);
+ write_2338 (0xec000194, 0x000f0501);
+ write_2338 (0xec000294, 0x000f0501);
+ write_2338 (0xec000394, 0x000f0501);
+ write_2338 (0xec000096, 0x00000001);
+ write_2338 (0xec000196, 0x00000001);
+ write_2338 (0xec000296, 0x00000001);
+ write_2338 (0xec000396, 0x00000001);
+ write_2338 (0xec000001, 0x00008c08);
+ write_2338 (0xec000101, 0x00008c08);
+ write_2338 (0xec000201, 0x00008c08);
+ write_2338 (0xec000301, 0x00008c08);
+ write_2338 (0xec0040b5, 0x0001c518);
+ write_2338 (0xec000087, 0x06077597);
+ write_2338 (0xec000187, 0x06077597);
+ write_2338 (0xec000287, 0x06077597);
+ write_2338 (0xec000387, 0x06077597);
+ write_2338 (0xea000050, 0x00bb0157);
+ write_2338 (0xea000150, 0x00bb0157);
+ write_2338 (0xec007f60, 0x77777d77);
+ write_2338 (0xea00008d, 0x01320000);
+ write_2338 (0xea00018d, 0x01320000);
+
+ read16 (DEFAULT_RCBABASE | 0x0400); // !!! = 0x0b00
+ read32 (DEFAULT_RCBABASE | 0x0400); // !!! = 0x00000b00
+
+ write_2338 (0xec0007b2, 0x04514b5e);
+ write_2338 (0xec00078c, 0x40000200);
+ write_2338 (0xec000780, 0x02000020);
+
+ read8 (DEFAULT_RCBABASE | 0x3414); // !!! = 0x00
+
+ read32 (DEFAULT_RCBABASE | 0x3598); // !!! = 0x00000001
+ read32 (DEFAULT_RCBABASE | 0x3598); // !!! = 0x00000001
+ write32 (DEFAULT_RCBABASE | 0x3598, 0x00000000);
+ read32 (DEFAULT_RCBABASE | 0x3598); // !!! = 0x00000000
+ pcie_read_config32 (PCI_DEV (0, 0x1d, 0), 0x88); // !!! = 0x04000030
+ pcie_write_config32 (PCI_DEV (0, 0x1d, 0), 0x88, 0x04000030);
+ pcie_read_config32 (PCI_DEV (0, 0x1a, 0), 0x88); // !!! = 0x04000030
+ pcie_write_config32 (PCI_DEV (0, 0x1a, 0), 0x88, 0x04000030);
+
+ read32 (DEFAULT_RCBABASE | 0x3410); // !!! = 0x00000c20
+ write32 (DEFAULT_RCBABASE | 0x3410, 0x00000c20);
+ read32 (DEFAULT_RCBABASE | 0x3410); // !!! = 0x00000c20
+ /* Disable SATA2. */
+ write32 (DEFAULT_RCBABASE | 0x3418,
+ read32 (DEFAULT_RCBABASE | 0x3418) | 0x02000000);
+ read32 (DEFAULT_RCBABASE | 0x3418); // !!! = 0x06000000
+
+ /* Configure thermal */
+ init_thermal ();
+
+ read8 (DEFAULT_RCBABASE | 0x31fe); // !!! = 0x00
+ read16 (DEFAULT_RCBABASE | 0x31fe); // !!! = 0x0000
+ write16 (DEFAULT_RCBABASE | 0x31fe, 0x0100);
+ read16 (DEFAULT_RCBABASE | 0x31fe); // !!! = 0x0100
+ read8 (DEFAULT_RCBABASE | 0x31fe); // !!! = 0x00
+ write8 (0xfec00000, 0x00);
+ read32 (0xfec00010); // !!! = 0x00000000
+ init_usb ();
+
+ write32 (DEFAULT_DMIBAR | 0x0914,
+ read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
+ write32 (DEFAULT_DMIBAR | 0x0934,
+ read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
+ for (i = 0; i < 4; i++)
+ {
+ write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
+ read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
+ write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
+ read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
+ }
+ write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
+ & 0xfffffff) | 0x40000000);
+ for (i = 0; i < 2; i++)
+ {
+ write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
+ read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
+ write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
+ read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
+ }
+ write32 (DEFAULT_DMIBAR | 0x090c,
+ read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
+ write32 (DEFAULT_DMIBAR | 0x092c,
+ read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
+ read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
+ read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208
+ write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
+ read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
+ read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208
+ write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
+ read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008
+ write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
+ read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
+ read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
+ read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300
+ write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
+ read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300
+ write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
+ read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
+ write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
+ read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000
+ write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
+ read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000
+ write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
+ read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
+ read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
+ read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec
+ write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
+ read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
+ write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
+ read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400
+ write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
+ read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008
+ write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
+ read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008
+ write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
+ read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080
+ write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
+ read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080
+ write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
+ read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280
+ write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
+ read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280
+ write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
+ read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
+ read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
+ read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
+ read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
+ read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600
+ write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
+ read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec
+ write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
+ read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280
+ write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
+ read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec
+ write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
+ read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280
+ write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
+ read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460
+ write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
+ read8 (DEFAULT_RCBABASE | 0x21a4); // !!! = 0x42
+
+ read32 (DEFAULT_RCBABASE | 0x21a4); // !!! = 0x00012c42
+ read32 (DEFAULT_RCBABASE | 0x2340); // !!! = 0x0013001b
+ write32 (DEFAULT_RCBABASE | 0x2340, 0x003a001b);
+ read8 (DEFAULT_RCBABASE | 0x21b0); // !!! = 0x01
+ write8 (DEFAULT_RCBABASE | 0x21b0, 0x02);
+ read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41
+ write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
+ read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
+ read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041
+ read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
+ read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
+ read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
+
+ pcie_read_config16 (PCI_DEV (0, 0x1e, 0), 0x00); // !!! = 0x8086
+ pcie_write_config32 (PCI_DEV (0, 0x1e, 0), 0x18, 0x00ff0200);
+ pcie_read_config8 (PCI_DEV (0, 0x1e, 0), 0x19); // !!! = 0x02
+
+ pcie_write_config8 (PCI_DEV (0, 0x1e, 0), 0x1a, 0x02);
+ pcie_write_config32 (PCI_DEV (0, 0x1e, 0), 0x18, 0x00000000);
+
+ read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f
+ write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
+ read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000
+ write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
+ read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000
+ write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
+ read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080
+ write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
+ read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
+ pcie_read_config32 (SOUTHBRIDGE, 0xf0); // !!! = 0xfed1c001
+ read32 (DEFAULT_RCBABASE | 0x0050); // !!! = 0x01200654
+ write32 (DEFAULT_RCBABASE | 0x0050, 0x01200654);
+ read32 (DEFAULT_RCBABASE | 0x0050); // !!! = 0x01200654
+ write32 (DEFAULT_RCBABASE | 0x0050, 0x012a0654);
+ read32 (DEFAULT_RCBABASE | 0x0050); // !!! = 0x012a0654
+ read8 (DEFAULT_RCBABASE | 0x1114); // !!! = 0x00
+ write8 (DEFAULT_RCBABASE | 0x1114, 0x05);
+ read32 (DEFAULT_RCBABASE | 0x2014); // !!! = 0x80000011
+ write32 (DEFAULT_RCBABASE | 0x2014, 0x80000019);
+ read32 (DEFAULT_RCBABASE | 0x2020); // !!! = 0x00000000
+ write32 (DEFAULT_RCBABASE | 0x2020, 0x81000022);
+ read32 (DEFAULT_RCBABASE | 0x2020); // !!! = 0x81000022
+ read32 (DEFAULT_RCBABASE | 0x2030); // !!! = 0x00000000
+ write32 (DEFAULT_RCBABASE | 0x2030, 0x82000044);
+ read32 (DEFAULT_RCBABASE | 0x2030); // !!! = 0x82000044
+ read32 (DEFAULT_RCBABASE | 0x2040); // !!! = 0x00000000
+ write32 (DEFAULT_RCBABASE | 0x2040, 0x87000080);
+ read32 (DEFAULT_RCBABASE | 0x0050); // !!! = 0x012a0654
+ write32 (DEFAULT_RCBABASE | 0x0050, 0x812a0654);
+ read32 (DEFAULT_RCBABASE | 0x0050); // !!! = 0x812a0654
+ read16 (DEFAULT_RCBABASE | 0x201a); // !!! = 0x0000
+ read16 (DEFAULT_RCBABASE | 0x2026); // !!! = 0x0000
+ read16 (DEFAULT_RCBABASE | 0x2036); // !!! = 0x0000
+ read16 (DEFAULT_RCBABASE | 0x2046); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000
+}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 61e1545..e62d1ad 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com>
+ * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,143 +32,180 @@
#include "raminit.h"
#include "pei_data.h"
#include "sandybridge.h"
+#include <delay.h>
/* Management Engine is in the southbridge */
#include "southbridge/intel/bd82x6x/me.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/smbus.h"
+#include <cpu/x86/msr.h>
+#include <cpu/cpu.h>
+#include "cpu/intel/model_2065x/model_2065x.h"
+
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#else
#define recovery_mode_enabled(x) 0
#endif
-/*
- * MRC scrambler seed offsets should be reserved in
- * mainboard cmos.layout and not covered by checksum.
- */
-#if CONFIG_USE_OPTION_TABLE
-#include "option_table.h"
-#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3)
-#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
-#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3)
-#else
-#define CMOS_OFFSET_MRC_SEED 152
-#define CMOS_OFFSET_MRC_SEED_S3 156
-#define CMOS_OFFSET_MRC_SEED_CHK 160
-#endif
+/* FIXME: no ECC support. */
+/* FIXME: no support for 3-channel chipsets. */
+/* FIXME: no S3. */
+/* FIXME: no timing caching. */
-void save_mrc_data(struct pei_data *pei_data)
-{
- u16 c1, c2, checksum;
+#define SANDYIVY_MAX_DIMM_SLOTS 4
-#if CONFIG_EARLY_CBMEM_INIT
- struct mrc_data_container *mrcdata;
- int output_len = ALIGN(pei_data->mrc_output_len, 16);
+#define BASEFREQ 133
+#define tDLLK 512
- /* Save the MRC S3 restore data to cbmem */
- mrcdata = cbmem_add
- (CBMEM_ID_MRCDATA,
- output_len + sizeof(struct mrc_data_container));
+#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
+#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
+#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
+#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
+#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
- printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
- pei_data->mrc_output, mrcdata, output_len);
+#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
+#define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
+#define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
+#define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
+#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
- mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
- mrcdata->mrc_data_size = output_len;
- mrcdata->reserved = 0;
- memcpy(mrcdata->mrc_data, pei_data->mrc_output,
- pei_data->mrc_output_len);
+#define NUM_CHANNELS 2
+#define NUM_SLOTRANKS 4
+#define NUM_SLOTS 2
+#define NUM_LANES 8
- /* Zero the unused space in aligned buffer. */
- if (output_len > pei_data->mrc_output_len)
- memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0,
- output_len - pei_data->mrc_output_len);
+typedef struct odtmap_st {
+ u16 rttwr;
+ u16 rttnom;
+} odtmap;
- mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
- mrcdata->mrc_data_size);
-#endif
+typedef struct dimm_info_st {
+ dimm_attr dimm[SANDYIVY_MAX_DIMM_SLOTS];
+} dimm_info;
- /* Save the MRC seed values to CMOS */
- cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
- printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n",
- pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+struct ram_rank_timings {
+ /* Register 4024. One byte per slotrank. */
+ u8 val_4024;
+ /* Register 4028. One nibble per slotrank. */
+ u8 val_4028;
- cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
- printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
- pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+ int val_320c;
- /* Save a simple checksum of the seed values */
- c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
- sizeof(u32));
- c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
- sizeof(u32));
- checksum = add_ip_checksums(sizeof(u32), c1, c2);
+ struct ram_lane_timings {
+ /* lane register offset 0x10. */
+ u16 timA; /* bits 0 - 5, bits 16 - 18 */
+ u8 rising; /* bits 8 - 14 */
+ u8 falling; /* bits 20 - 26. */
- cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
- cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
-}
+ /* lane register offset 0x20. */
+ int timC; /* bit 0 - 5, 19. */
+ u16 timB; /* bits 8 - 13, 15 - 17. */
+ } lanes[NUM_LANES];
+};
-static void prepare_mrc_cache(struct pei_data *pei_data)
-{
- struct mrc_data_container *mrc_cache;
- u16 c1, c2, checksum, seed_checksum;
+typedef struct ramctr_timing_st {
+ int mobile;
- // preset just in case there is an error
- pei_data->mrc_input = NULL;
- pei_data->mrc_input_len = 0;
+ enum spd_memory_type dram_type;
+ u16 cas_supported;
+ /* tLatencies are in units of ns, scaled by x256 */
+ u32 tCK;
+ u32 tAA;
+ u32 tWR;
+ u32 tRCD;
+ u32 tRRD;
+ u32 tRP;
+ u32 tRAS;
+ u32 tRC;
+ u32 tRFC;
+ u32 tWTR;
+ u32 tRTP;
+ u32 tFAW;
+ /* Latencies in terms of clock cycles
+ * They are saved separately as they are needed for DRAM MRS commands*/
+ u8 CAS; /* CAS read latency */
+ u8 CWL; /* CAS write latency */
+ /* Number of dimms currently connected */
+ u8 n_dimms;
- /* Read scrambler seeds from CMOS */
- pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
- printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n",
- pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+ u32 tREFI;
+ u32 tMOD;
+ u32 tXSOffset;
+ u32 tWLO;
+ u32 tCKE;
+ u32 tXPDLL;
+ u32 tXP;
+ u32 tAONPD;
- pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
- printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
- pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+ u32 delay1;
+ u32 delay2;
- /* Compute seed checksum and compare */
- c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
- sizeof(u32));
- c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
- sizeof(u32));
- checksum = add_ip_checksums(sizeof(u32), c1, c2);
+ u8 eccsupport;
+ u8 dualchannel;
+ u8 thermalrefresh;
- seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK);
- seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8;
+ u8 rankmap[NUM_CHANNELS];
- if (checksum != seed_checksum) {
- printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__);
- pei_data->scrambler_seed = 0;
- pei_data->scrambler_seed_s3 = 0;
- return;
- }
+ int reg_c14_offset;
- if ((mrc_cache = find_current_mrc_cache()) == NULL) {
- /* error message printed in find_current_mrc_cache */
- return;
- }
+ int edge_offset[3];
+ int timC_offset[3];
- pei_data->mrc_input = mrc_cache->mrc_data;
- pei_data->mrc_input_len = mrc_cache->mrc_data_size;
+ int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];
- printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n",
- __func__, pei_data->mrc_input,
- pei_data->mrc_input_len, mrc_cache->mrc_checksum);
-}
+ struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];
+} ramctr_timing;
+
+#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
+#define NORTHBRIDGE PCI_DEV(0, 0x0, 0)
+#define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
+#define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
+#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))
+#define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel])
+#define max(a,b) ((a) > (b) ? (a) : (b))
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#define MAX_EDGE_TIMING 71
+#define MAX_TIMC 127
+#define MAX_TIMB 511
+#define MAX_TIMA 127
-static const char* ecc_decoder[] = {
+static void program_timings(ramctr_timing * ctrl, int channel);
+
+static const char *ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
"active"
};
+static void wait_txt_clear(void)
+{
+ struct cpuid_result cp;
+
+ cp = cpuid_ext(0x1, 0x0);
+ /* Check if TXT is supported? */
+ if (!(cp.ecx & 0x40))
+ return;
+ /* Some TXT public bit. */
+ if (!(read32(0xfed30010) & 1))
+ return;
+ /* Wait for TXT clear. */
+ while (!(read8(0xfed40000) & (1 << 7))) ;
+}
+
+static void sfence(void)
+{
+ asm volatile ("sfence");
+}
+
/*
* Dump in the log memory controller configuration as read from the memory
* controller registers.
*/
static void report_memory_config(void)
{
- u32 addr_decoder_common, addr_decode_ch[2];
+ u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
int i;
addr_decoder_common = MCHBAR32(0x5000);
@@ -175,16 +213,15 @@ static void report_memory_config(void)
addr_decode_ch[1] = MCHBAR32(0x5008);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
- (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
+ (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
- addr_decoder_common & 3,
- (addr_decoder_common >> 2) & 3,
+ addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3);
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
u32 ch_conf = addr_decode_ch[i];
- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
- i, ch_conf);
+ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i,
+ ch_conf);
printk(BIOS_DEBUG, " ECC %s\n",
ecc_decoder[(ch_conf >> 24) & 3]);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
@@ -204,97 +241,3485 @@ static void report_memory_config(void)
}
}
-static void post_system_agent_init(struct pei_data *pei_data)
+static void post_system_agent_init(void)
{
/* If PCIe init is skipped, set the PEG clock gating */
- if (!pei_data->pcie_init)
- MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
+ MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
}
-/**
- * Find PEI executable in coreboot filesystem and execute it.
- *
- * @param pei_data: configuration data for UEFI PEI reference code
- */
-void sdram_initialize(struct pei_data *pei_data)
+void read_spd(spd_raw_data * spd, u8 addr)
{
- struct sys_info sysinfo;
- int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
+ int j;
+ for (j = 0; j < 256; j++)
+ (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j);
+}
- report_platform_info();
+static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm,
+ ramctr_timing * ctrl)
+{
+ int i = 0;
+ int dimms = 0;
+ static const u8 ch[4] = { 0, 0, 1, 1 };
+ static const u8 dm[4] = { 0, 1, 0, 1 };
+ memset (ctrl->rankmap, 0, sizeof (ctrl->rankmap));
+ for (i = 0; i < 4; i++) {
+ spd_decode_ddr3(&dimm->dimm[i], spd[i]);
+ if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
+ // set dimm invalid
+ dimm->dimm[i].ranks = 0;
+ dimm->dimm[i].size_mb = 0;
+ continue;
+ }
- /* Wait for ME to be ready */
- intel_early_me_init();
- intel_early_me_uma_size();
+ dram_print_spd_ddr3(&dimm->dimm[i]);
+ dimms++;
+ ctrl->rank_mirror[ch[i]][dm[i] * 2] = 0;
+ ctrl->rank_mirror[ch[i]][dm[i] * 2 + 1] = spd[i][0x3f] & 1;
+
+ /* FIXME: should merge data from all dimms. */
+ ctrl->thermalrefresh = spd[i][31];
+ ctrl->rankmap[ch[i]] = ((1 << dimm->dimm[i].ranks) - 1) << (2 * dm[i]);
+ printk(BIOS_DEBUG, "i=%d rankmap[%d] = 0x%x\n", i, ch[i], ctrl->rankmap[ch[i]]);
+ }
+ if (!dimms)
+ die("No DIMMs were found");
+}
+
+static void dram_find_common_params(const dimm_info * dimms,
+ ramctr_timing * ctrl)
+{
+ size_t i, valid_dimms;
+ ctrl->cas_supported = 0xff;
+ valid_dimms = 0;
+ for (i = 0; i < 4; i++) {
+ const dimm_attr *dimm = &dimms->dimm[i];
+ if (dimm->dram_type == SPD_MEMORY_TYPE_UNDEFINED)
+ continue;
+ valid_dimms++;
+
+ if (valid_dimms == 1) {
+ /* First DIMM defines the type of DIMM */
+ ctrl->dram_type = dimm->dram_type;
+ } else {
+ /* Check if we have mismatched DIMMs */
+ if (ctrl->dram_type != dimm->dram_type)
+ die("Mismatched DIMM Types");
+ }
+ /* Find all possible CAS combinations */
+ ctrl->cas_supported &= dimm->cas_supported;
- printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
+ /* Find the smallest common latencies supported by all DIMMs */
+ ctrl->tCK = MAX(ctrl->tCK, dimm->tCK);
+ ctrl->tAA = MAX(ctrl->tAA, dimm->tAA);
+ ctrl->tWR = MAX(ctrl->tWR, dimm->tWR);
+ ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD);
+ ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD);
+ ctrl->tRP = MAX(ctrl->tRP, dimm->tRP);
+ ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS);
+ ctrl->tRC = MAX(ctrl->tRC, dimm->tRC);
+ ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC);
+ ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR);
+ ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP);
+ ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW);
+ }
- memset(&sysinfo, 0, sizeof(sysinfo));
+ ctrl->n_dimms = valid_dimms;
+ if (!ctrl->cas_supported)
+ die("Unsupported DIMM combination. "
+ "DIMMS do not support common CAS latency");
+ if (!valid_dimms)
+ die("No valid DIMMs found");
- sysinfo.boot_path = pei_data->boot_mode;
+ ctrl->dualchannel =
+ (pcie_read_config32(PCI_DEV(0, 0, 0), 0xE4) & 0x4000) >> 14;
+ if (ctrl->dualchannel) {
+ printk(BIOS_DEBUG, "Dual channel supported\n");
+ } else {
+ printk(BIOS_DEBUG, "Dual channel not supported\n");
+ }
+}
- /*
- * Do not pass MRC data in for recovery mode boot,
- * Always pass it in for S3 resume.
+static u8 get_CWL(u8 CAS)
+{
+ /* Get CWL based on CAS using the following rule:
+ * _________________________________________
+ * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T |
+ * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T |
*/
- if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
- prepare_mrc_cache(pei_data);
+ static const u8 cas_cwl_map[] = { 5, 5, 5, 6, 6, 7, 7, 8 };
+ if (CAS > 11)
+ return 8;
+ return cas_cwl_map[CAS - 4];
+}
- /* If MRC data is not found we cannot continue S3 resume. */
- if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
- printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
- outb(0x6, 0xcf9);
- hlt();
- }
-
- /* Pass console handler in pei_data */
- pei_data->tx_byte = do_putchar;
-
- /* Locate and call UEFI System Agent binary. */
- /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */
- entry = cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL);
- if (entry) {
- int rv;
- rv = entry (pei_data);
- if (rv) {
- switch (rv) {
- case -1:
- printk(BIOS_ERR, "PEI version mismatch.\n");
- break;
- case -2:
- printk(BIOS_ERR, "Invalid memory frequency.\n");
- break;
- default:
- printk(BIOS_ERR, "MRC returned %x.\n", rv);
+static u32 get_REFI(u32 tCK)
+{
+ /* Get REFI based on MCU frequency using the following rule:
+ * _________________________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u32 frq_refi_map[] =
+ { 3120, 4160, 5200, 6240, 7280, 8320 };
+ if (FRQ > 8)
+ return 8320;
+ return frq_refi_map[FRQ - 3];
+}
+
+static u8 get_XSOffset(u32 tCK)
+{
+ /* Get XSOffset based on MCU frequency using the following rule:
+ * _________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 };
+ if (FRQ > 8)
+ return 11;
+ return frq_xs_map[FRQ - 3];
+}
+
+static u8 get_MOD(u32 tCK)
+{
+ /* Get MOD based on MCU frequency using the following rule:
+ * _____________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * MOD : | 12 | 12 | 12 | 12 | 15 | 16 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 };
+ if (FRQ > 8)
+ return 16;
+ return frq_mod_map[FRQ - 3];
+}
+
+static u8 get_WLO(u32 tCK)
+{
+ /* Get WLO based on MCU frequency using the following rule:
+ * _______________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * WLO : | 4 | 5 | 6 | 6 | 8 | 8 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 };
+ if (FRQ > 8)
+ return 8;
+ return frq_wlo_map[FRQ - 3];
+}
+
+static u8 get_CKE(u32 tCK)
+{
+ /* Get CKE based on MCU frequency using the following rule:
+ * _______________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * CKE : | 3 | 3 | 4 | 4 | 5 | 6 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 };
+ if (FRQ > 8)
+ return 6;
+ return frq_cke_map[FRQ - 3];
+}
+
+static u8 get_XPDLL(u32 tCK)
+{
+ /* Get XPDLL based on MCU frequency using the following rule:
+ * _____________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 };
+ if (FRQ > 8)
+ return 26;
+ return frq_xpdll_map[FRQ - 3];
+}
+
+static u8 get_XP(u32 tCK)
+{
+ /* Get XP based on MCU frequency using the following rule:
+ * _______________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * XP : | 3 | 4 | 4 | 5 | 6 | 7 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 };
+ if (FRQ > 8)
+ return 7;
+ return frq_xp_map[FRQ - 3];
+}
+
+static u8 get_AONPD(u32 tCK)
+{
+ /* Get AONPD based on MCU frequency using the following rule:
+ * ________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 };
+ if (FRQ > 8)
+ return 10;
+ return frq_aonpd_map[FRQ - 3];
+}
+
+static u32 get_COMP2(u32 tCK)
+{
+ /* Get COMP2 based on MCU frequency using the following rule:
+ * ___________________________________________________________
+ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 |
+ * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C |
+ */
+ u32 FRQ = (u32) 256000 / (tCK * BASEFREQ);
+ static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C,
+ 0xC6369CC, 0xC42514C, 0xC21410C
+ };
+ if (FRQ > 8)
+ return 0xD6BEDCC;
+ return frq_comp2_map[FRQ - 3];
+}
+
+static void dram_timing(ramctr_timing * ctrl)
+{
+ u8 val;
+ u32 val32;
+
+ /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure
+ * we cap it if we have faster DIMMs.
+ * Then, align it to the closest JEDEC standard frequency */
+ if (ctrl->tCK <= TCK_1066MHZ) {
+ ctrl->tCK = TCK_1066MHZ;
+ ctrl->delay1 = 16;
+ ctrl->delay2 = 8;
+ ctrl->edge_offset[0] = 16;
+ ctrl->edge_offset[1] = 7;
+ ctrl->edge_offset[2] = 7;
+ ctrl->timC_offset[0] = 18;
+ ctrl->timC_offset[1] = 7;
+ ctrl->timC_offset[2] = 7;
+ ctrl->reg_c14_offset = 16;
+ } else if (ctrl->tCK <= TCK_933MHZ) {
+ ctrl->tCK = TCK_933MHZ;
+ ctrl->delay1 = 15;
+ ctrl->delay2 = 8;
+ ctrl->edge_offset[0] = 14;
+ ctrl->edge_offset[1] = 6;
+ ctrl->edge_offset[2] = 6;
+ ctrl->timC_offset[0] = 15;
+ ctrl->timC_offset[1] = 6;
+ ctrl->timC_offset[2] = 6;
+ ctrl->reg_c14_offset = 14;
+ } else if (ctrl->tCK <= TCK_800MHZ) {
+ ctrl->tCK = TCK_800MHZ;
+ ctrl->delay1 = 12;
+ ctrl->delay2 = 6;
+ ctrl->edge_offset[0] = 13;
+ ctrl->edge_offset[1] = 5;
+ ctrl->edge_offset[2] = 5;
+ ctrl->timC_offset[0] = 14;
+ ctrl->timC_offset[1] = 5;
+ ctrl->timC_offset[2] = 5;
+ ctrl->reg_c14_offset = 12;
+ } else if (ctrl->tCK <= TCK_666MHZ) {
+ ctrl->tCK = TCK_666MHZ;
+ ctrl->delay1 = 12;
+ ctrl->delay2 = 6;
+ ctrl->edge_offset[0] = 10;
+ ctrl->edge_offset[1] = 4;
+ ctrl->edge_offset[2] = 4;
+ ctrl->timC_offset[0] = 11;
+ ctrl->timC_offset[1] = 4;
+ ctrl->timC_offset[2] = 4;
+ ctrl->reg_c14_offset = 10;
+ } else {
+ ctrl->tCK = TCK_533MHZ;
+ ctrl->delay1 = 12;
+ ctrl->delay2 = 5;
+ ctrl->edge_offset[0] = 8;
+ ctrl->edge_offset[1] = 3;
+ ctrl->edge_offset[2] = 3;
+ ctrl->timC_offset[0] = 9;
+ ctrl->timC_offset[1] = 3;
+ ctrl->timC_offset[2] = 3;
+ ctrl->reg_c14_offset = 8;
+ }
+
+ val32 = (1000 << 8) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);
+
+ /* Find CAS and CWL latencies */
+ val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val);
+ /* Find lowest supported CAS latency that satisfies the minimum value */
+ while (!((ctrl->cas_supported >> (val - 4)) & 1)
+ && (ctrl->cas_supported >> (val - 4))) {
+ val++;
+ }
+ /* Is CAS supported */
+ if (!(ctrl->cas_supported & (1 << (val - 4))))
+ printk(BIOS_DEBUG, "CAS not supported\n");
+ printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val);
+ ctrl->CAS = val;
+ ctrl->CWL = get_CWL(ctrl->CAS);
+ printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);
+
+ /* Find tRCD */
+ ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
+
+ ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
+
+ /* Find tRAS */
+ ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
+
+ /* Find tWR */
+ ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
+
+ /* Find tFAW */
+ ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
+
+ /* Find tRRD */
+ ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
+
+ /* Find tRTP */
+ ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
+
+ /* Find tWTR */
+ ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
+
+ /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */
+ ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
+
+ ctrl->tRC = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK;
+ printk(BIOS_DEBUG, "Required tRC : %uT\n", ctrl->tRC);
+
+ ctrl->tREFI = get_REFI(ctrl->tCK);
+ ctrl->tMOD = get_MOD(ctrl->tCK);
+ ctrl->tXSOffset = get_XSOffset(ctrl->tCK);
+ ctrl->tWLO = get_WLO(ctrl->tCK);
+ ctrl->tCKE = get_CKE(ctrl->tCK);
+ ctrl->tXPDLL = get_XPDLL(ctrl->tCK);
+ ctrl->tXP = get_XP(ctrl->tCK);
+ ctrl->tAONPD = get_AONPD(ctrl->tCK);
+}
+
+static void dram_freq(ramctr_timing * ctrl)
+{
+ u8 val1, val2;
+ u32 reg1 = 0;
+
+ /* Step 1 - Set target PCU frequency */
+
+ if (ctrl->tCK <= TCK_1066MHZ) {
+ val1 = 0x08;
+ ctrl->tCK = TCK_1066MHZ;
+ } else if (ctrl->tCK <= TCK_933MHZ) {
+ val1 = 0x07;
+ ctrl->tCK = TCK_933MHZ;
+ } else if (ctrl->tCK <= TCK_800MHZ) {
+ val1 = 0x06;
+ ctrl->tCK = TCK_800MHZ;
+ } else if (ctrl->tCK <= TCK_666MHZ) {
+ val1 = 0x05;
+ ctrl->tCK = TCK_666MHZ;
+ } else {
+ val1 = 0x04;
+ ctrl->tCK = TCK_533MHZ;
+ }
+
+ /* Step 2 - Select frequency in the MCU */
+ reg1 = val1;
+ reg1 |= 0x80000000; // set running bit
+ MCHBAR32(0x5e00) = reg1;
+ while (reg1 & 0x80000000) {
+ printk(BIOS_DEBUG, " PLL busy...");
+ reg1 = MCHBAR32(0x5e00);
+ }
+ printk(BIOS_DEBUG, "done\n");
+
+ /* Step 3 - Verify lock frequency */
+ reg1 = MCHBAR32(0x5e04);
+ val2 = (u8) reg1;
+ if (val2 > val1) {
+ printk(BIOS_DEBUG, "Lock frequency is lower, recalculating\n");
+ switch (val2) {
+ case 8:
+ ctrl->tCK = TCK_1066MHZ;
+ break;
+ case 7:
+ ctrl->tCK = TCK_933MHZ;
+ break;
+ case 6:
+ ctrl->tCK = TCK_800MHZ;
+ break;
+ case 5:
+ ctrl->tCK = TCK_666MHZ;
+ break;
+ case 4:
+ ctrl->tCK = TCK_533MHZ;
+ break;
+ default:
+ printk(BIOS_DEBUG, "ERROR: PLL is off or unknown\n");
+ break;
+ }
+ dram_timing(ctrl); // recalculate timings
+ }
+ printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n",
+ (1000 << 8) / ctrl->tCK);
+}
+
+static void dram_xover(ramctr_timing * ctrl)
+{
+ u32 reg;
+ int channel;
+
+ FOR_ALL_CHANNELS {
+ // enable xover clk
+ printk(BIOS_DEBUG, "[%x] = %x\n", channel * 0x100 + 0xc14,
+ (ctrl->rankmap[channel] << 24));
+ MCHBAR32(channel * 0x100 + 0xc14) = (ctrl->rankmap[channel] << 24);
+
+ // enable xover ctl
+ reg = 0;
+ if (ctrl->rankmap[channel] & 0x5) {
+ reg |= 0x20000;
+ }
+ if (ctrl->rankmap[channel] & 0xa) {
+ reg |= 0x4000000;
+ }
+ // enable xover cmd
+ reg |= 0x4000;
+ printk(BIOS_DEBUG, "[%x] = %x\n", 0x100 * channel + 0x320c,
+ reg);
+ MCHBAR32(0x100 * channel + 0x320c) = reg;
+ }
+}
+
+static void dram_timing_regs(ramctr_timing * ctrl)
+{
+ u32 reg, addr, val32, cpu, stretch;
+ u8 val;
+ struct cpuid_result cpures;
+ int channel;
+
+ FOR_ALL_CHANNELS {
+ // DBP
+ reg = 0;
+ val = ctrl->tRCD;
+ reg = (reg & ~0xf) | val;
+ val = ctrl->tRP;
+ reg = (reg & ~0xf0) | (val << 4);
+ val = ctrl->CAS;
+ reg = (reg & ~0xf00) | (val << 8);
+ val = ctrl->CWL;
+ reg = (reg & ~0xf000) | (val << 12);
+ val = ctrl->tRAS;
+ reg = (reg & ~0xff0000) | (val << 16);
+ printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4000,
+ reg);
+ MCHBAR32(0x400 * channel + 0x4000) = reg;
+
+ // RAP
+ reg = 0;
+ val = ctrl->tRRD;
+ reg = (reg & ~0xf) | val;
+ val = ctrl->tRTP;
+ reg = (reg & ~0xf0) | (val << 4);
+ val = ctrl->tCKE;
+ reg = (reg & ~0xf00) | (val << 8);
+ val = ctrl->tWTR;
+ reg = (reg & ~0xf000) | (val << 12);
+ val = ctrl->tFAW;
+ reg = (reg & ~0xff0000) | (val << 16);
+ val = ctrl->tWR;
+ reg = (reg & ~0x1f000000) | (val << 24);
+ reg = (reg & ~0xc0000000) | (3 << 30);
+ printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4004,
+ reg);
+ MCHBAR32(0x400 * channel + 0x4004) = reg;
+
+ // OTHP
+ addr = 0x400 * channel + 0x400c;
+ reg = MCHBAR32(addr);
+ val = ctrl->tXPDLL;
+ reg = (reg & ~0x1f) | val;
+ val = ctrl->tXP;
+ reg = (reg & ~0xe0) | (val << 5);
+ val = ctrl->tAONPD;
+ reg = (reg & ~0xf00) | (val << 8);
+ printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg);
+ MCHBAR32(addr) = reg;
+
+ MCHBAR32(0x400 * channel + 0x4014) = 0;
+
+ MCHBAR32(addr) |= 0x00020000;
+
+ // ODT stretch
+ reg = 0;
+
+ cpures = cpuid(0);
+ cpu = cpures.eax;
+ if (IS_IVY_CPU(cpu)
+ || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) {
+ stretch = 2;
+ addr = 0x400 * channel + 0x400c;
+ printk(BIOS_DEBUG, "[%x] = %x\n",
+ 0x400 * channel + 0x400c, reg);
+ reg = MCHBAR32(addr);
+
+ if (((ctrl->rankmap[channel] & 3) == 0)
+ || (ctrl->rankmap[channel] & 0xc) == 0) {
+
+ // Rank 0 - operate on rank 2
+ reg = (reg & ~0xc0000) | (stretch << 18);
+
+ // Rank 2 - operate on rank 0
+ reg = (reg & ~0x30000) | (stretch << 16);
+
+ printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg);
+ MCHBAR32(addr) = reg;
+ }
+
+ } else if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
+ stretch = 3;
+ addr = 0x400 * channel + 0x401c;
+ reg = MCHBAR32(addr);
+
+ if (((ctrl->rankmap[channel] & 3) == 0)
+ || (ctrl->rankmap[channel] & 0xc) == 0) {
+
+ // Rank 0 - operate on rank 2
+ reg = (reg & ~0x3000) | (stretch << 12);
+
+ // Rank 2 - operate on rank 0
+ reg = (reg & ~0xc00) | (stretch << 10);
+
+ printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg);
+ MCHBAR32(addr) = reg;
}
- die("Nonzero MRC return value.\n");
+ } else {
+ stretch = 0;
}
+
+ // REFI
+ reg = 0;
+ val32 = ctrl->tREFI;
+ reg = (reg & ~0xffff) | val32;
+ val32 = ctrl->tRFC;
+ reg = (reg & ~0x1ff0000) | (val32 << 16);
+ val32 = (u32) (ctrl->tREFI * 9) / 1024;
+ reg = (reg & ~0xfe000000) | (val32 << 25);
+ printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4298,
+ reg);
+ MCHBAR32(0x400 * channel + 0x4298) = reg;
+
+ MCHBAR32(0x400 * channel + 0x4294) |= 0xff;
+
+ // SRFTP
+ reg = 0;
+ val32 = tDLLK;
+ reg = (reg & ~0xfff) | val32;
+ val32 = ctrl->tXSOffset;
+ reg = (reg & ~0xf000) | (val32 << 12);
+ val32 = tDLLK - ctrl->tXSOffset;
+ reg = (reg & ~0x3ff0000) | (val32 << 16);
+ val32 = ctrl->tMOD - 8;
+ reg = (reg & ~0xf0000000) | (val32 << 28);
+ printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x42a4,
+ reg);
+ MCHBAR32(0x400 * channel + 0x42a4) = reg;
+ }
+}
+
+static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl)
+{
+ int t;
+ u32 reg, val32;
+ int channel;
+
+ FOR_ALL_CHANNELS {
+ dimm_attr *dimmA = 0;
+ dimm_attr *dimmB = 0;
+ reg = 0;
+ val32 = 0;
+ if (info->dimm[2 * channel].size_mb >=
+ info->dimm[2 * channel + 1].size_mb) {
+ // dimm 0 is bigger, set it to dimmA
+ dimmA = &info->dimm[2 * channel];
+ dimmB = &info->dimm[2 * channel + 1];
+ reg |= (0 << 16);
+ } else {
+ // dimm 1 is bigger, set it to dimmA
+ dimmA = &info->dimm[2 * channel + 1];
+ dimmB = &info->dimm[2 * channel];
+ reg |= (1 << 16);
+ // swap dimm info
+ t = ctrl->rank_mirror[channel][1];
+ ctrl->rank_mirror[channel][1] =
+ ctrl->rank_mirror[channel][3];
+ ctrl->rank_mirror[channel][3] = t;
+ }
+ // dimmA
+ if (dimmA && (dimmA->ranks > 0)) {
+ val32 = dimmA->size_mb / 256;
+ reg = (reg & ~0xff) | val32;
+ val32 = dimmA->ranks - 1;
+ reg = (reg & ~0x20000) | (val32 << 17);
+ val32 = (dimmA->width / 8) - 1;
+ reg = (reg & ~0x80000) | (val32 << 19);
+ }
+ // dimmB
+ if (dimmB && (dimmB->ranks > 0)) {
+ val32 = dimmB->size_mb / 256;
+ reg = (reg & ~0xff00) | (val32 << 8);
+ val32 = dimmB->ranks - 1;
+ reg = (reg & ~0x40000) | (val32 << 18);
+ val32 = (dimmB->width / 8) - 1;
+ reg = (reg & ~0x100000) | (val32 << 20);
+ }
+ reg = (reg & ~0x200000) | (1 << 21); // rank interleave
+ reg = (reg & ~0x400000) | (1 << 22); // enhanced interleave
+
+ // Set MAD-DIMM register
+ if ((dimmA && (dimmA->ranks > 0))
+ || (dimmB && (dimmB->ranks > 0))) {
+ MCHBAR32(0x5004 + channel * 4) = reg;
+ }
+ }
+}
+
+static void dram_zones(dimm_info * info, ramctr_timing * ctrl, int training)
+{
+ u32 reg, ch0size, ch1size;
+ u8 val;
+ reg = 0;
+ val = 0;
+ if (training) {
+ ch0size =
+ info->dimm[0].size_mb + info->dimm[1].size_mb ? 256 : 0;
+ ch1size =
+ info->dimm[2].size_mb + info->dimm[3].size_mb ? 256 : 0;
} else {
- die("UEFI PEI System Agent not found.\n");
+ ch0size = info->dimm[0].size_mb + info->dimm[1].size_mb;
+ ch1size = info->dimm[2].size_mb + info->dimm[3].size_mb;
}
-#if CONFIG_USBDEBUG_IN_ROMSTAGE
- /* mrc.bin reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif
+ if (ch0size >= ch1size) {
+ reg = MCHBAR32(0x5014);
+ val = ch1size / 256;
+ reg = (reg & ~0xff000000) | val << 24;
+ reg = (reg & ~0xff0000) | (2 * val) << 16;
+ MCHBAR32(0x5014) = reg;
+ MCHBAR32(0x5000) = 0x24;
+ } else {
+ reg = MCHBAR32(0x5014);
+ val = ch0size / 256;
+ reg = (reg & ~0xff000000) | val << 24;
+ reg = (reg & ~0xff0000) | (2 * val) << 16;
+ MCHBAR32(0x5014) = reg;
+ MCHBAR32(0x5000) = 0x21;
+ }
+}
- /* For reference print the System Agent version
- * after executing the UEFI PEI stage.
- */
- u32 version = MCHBAR32(0x5034);
- printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
- (version >> 8) & 0xff, version & 0xff);
-
- /* Send ME init done for SandyBridge here. This is done
- * inside the SystemAgent binary on IvyBridge. */
- if (BASE_REV_SNB ==
- (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK))
- intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
- else
- intel_early_me_status();
+/* FIXME: this function bugs. */
+static void dram_memorymap(dimm_info * info, int me_uma_size)
+{
+ u32 reg, val, reclaim;
+ u32 tom, gfxstolen, gttsize;
+ size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase,
+ tsegbase, mestolenbase;
+ size_t tsegbasedelta, remapbase, remaplimit;
+ uint16_t ggc;
+
+ mmiosize = 0x400;
+
+ ggc = pci_read_config16(NORTHBRIDGE, GGC);
+ if (!(ggc & 2)) {
+ gfxstolen = ((ggc >> 3) & 0x1f) * 32;
+ gttsize = ((ggc >> 8) & 0x3);
+ } else {
+ gfxstolen = 0;
+ gttsize = 0;
+ }
+
+ tsegsize = CONFIG_SMM_TSEG_SIZE >> 20;
+
+ tom =
+ info->dimm[0].size_mb + info->dimm[1].size_mb +
+ info->dimm[2].size_mb + info->dimm[3].size_mb;
+
+ mestolenbase = tom - me_uma_size;
+
+ toludbase = MIN(4096 - mmiosize, tom - me_uma_size);
+ gfxstolenbase = toludbase - gfxstolen;
+ gttbase = gfxstolenbase - gttsize;
+
+ tsegbase = gttbase - tsegsize;
+
+ // Round tsegbase down to nearest address aligned to tsegsize
+ tsegbasedelta = tsegbase & (tsegsize - 1);
+ tsegbase &= ~(tsegsize - 1);
+
+ gttbase -= tsegbasedelta;
+ gfxstolenbase -= tsegbasedelta;
+ toludbase -= tsegbasedelta;
+
+ // Test if it is possible to reclaim a hole in the ram addressing
+ if (tom - me_uma_size > toludbase) {
+ // Reclaim is possible
+ reclaim = 1;
+ remapbase = MAX(4096, tom - me_uma_size);
+ remaplimit =
+ remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1;
+ touudbase = remaplimit + 1;
+ } else {
+ // Reclaim not possible
+ reclaim = 0;
+ touudbase = tom - me_uma_size;
+ }
+
+ // Update memory map in pci-e configuration space
+
+ // TOM (top of memory)
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0);
+ val = tom & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa0, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg);
+
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4);
+ val = tom & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa4, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg);
+
+ // TOLUD (top of low used dram)
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc);
+ val = toludbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xbc, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg);
+
+ // TOUUD LSB (top of upper usable dram)
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8);
+ val = touudbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa8, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg);
+
+ // TOUUD MSB
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac);
+ val = touudbase & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xac, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg);
+
+ if (reclaim) {
+ // REMAP BASE
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x94);
+ val = remapbase & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x94, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x94, reg);
+
+ // REMAP LIMIT
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x98);
+ val = remaplimit & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x98, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x98, reg);
+
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x9c);
+ val = remaplimit & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x9c, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x9c, reg);
+ }
+ // TSEG
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8);
+ val = tsegbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb8, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg);
+
+ // GFX stolen memory
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0);
+ val = gfxstolenbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb0, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg);
+
+ // GTT stolen memory
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4);
+ val = gttbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb4, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg);
+
+ if (me_uma_size) {
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c);
+ val = (0x80000 - me_uma_size) & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x7c, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg);
+
+ // ME base
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70);
+ val = mestolenbase & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x70, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg);
+
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74);
+ val = mestolenbase & 0xfffff000;
+ reg = (reg & ~0x000fffff) | (val >> 12);
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x74, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg);
+
+ // ME mask
+ reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x78);
+ val = (0x80000 - me_uma_size) & 0xfff;
+ reg = (reg & ~0xfff00000) | (val << 20);
+ reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem
+
+ reg = (reg & ~0x800) | (1 << 11); // set ME memory enable
+ printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x78, reg);
+ pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg);
+ }
+}
+
+static void dram_ioregs(ramctr_timing * ctrl)
+{
+ u32 reg, comp2;
+
+ int channel;
+
+ // IO clock
+ FOR_ALL_CHANNELS {
+ MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel];
+ }
+
+ // IO command
+ FOR_ALL_CHANNELS {
+ MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel];
+ }
+
+ // IO control
+ FOR_ALL_POPULATED_CHANNELS {
+ program_timings(ctrl, channel);
+ }
+
+ // Rcomp
+ printk(BIOS_DEBUG, "RCOMP...");
+ reg = 0;
+ while (reg == 0) {
+ reg = MCHBAR32(0x5084) & 0x10000;
+ }
+ printk(BIOS_DEBUG, "done\n");
+
+ // Set comp2
+ comp2 = get_COMP2(ctrl->tCK);
+ MCHBAR32(0x3714) = comp2;
+ printk(BIOS_DEBUG, "COMP2 done\n");
+
+ // Set comp1
+ FOR_ALL_POPULATED_CHANNELS {
+ reg = MCHBAR32(0x1810 + channel * 0x100); //ch0
+ reg = (reg & ~0xe00) | (1 << 9); //odt
+ reg = (reg & ~0xe00000) | (1 << 21); //clk drive up
+ reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up
+ MCHBAR32(0x1810 + channel * 0x100) = reg;
+ }
+ printk(BIOS_DEBUG, "COMP1 done\n");
+
+ printk(BIOS_DEBUG, "FORCE RCOMP and wait 20us...");
+ MCHBAR32(0x5f08) |= 0x100;
+ udelay(20);
+ printk(BIOS_DEBUG, "done\n");
+}
+
+static void wait_428c(int channel)
+{
+ while (1) {
+ if (read32(DEFAULT_MCHBAR | 0x428c | (channel << 10)) & 0x50)
+ return;
+ }
+}
+
+static void write_reset(ramctr_timing * ctrl)
+{
+ int channel, slotrank;
+
+ /* choose a populated channel. */
+ channel = (ctrl->rankmap[0]) ? 0 : 1;
+
+ wait_428c(channel);
+
+ /* choose a populated rank. */
+ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01);
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001);
+ wait_428c(channel);
+}
+
+static void dram_jedecreset(ramctr_timing * ctrl)
+{
+ u32 reg, addr;
+ int channel;
+
+ while (!(MCHBAR32(0x5084) & 0x10000)) ;
+ do {
+ reg = MCHBAR32(0x428c);
+ } while ((reg & 0x14) == 0);
+
+ // Set state of memory controller
+ reg = 0x112;
+ MCHBAR32(0x5030) = reg;
+ MCHBAR32(0x4ea0) = 0;
+ reg |= 2; //ddr reset
+ MCHBAR32(0x5030) = reg;
+
+ // Assert dimm reset signal
+ reg = MCHBAR32(0x5030);
+ reg &= ~0x2;
+ MCHBAR32(0x5030) = reg;
+
+ // Wait 200us
+ udelay(200);
+
+ // Deassert dimm reset signal
+ MCHBAR32(0x5030) |= 2;
+
+ // Wait 500us
+ udelay(500);
+
+ // Enable DCLK
+ MCHBAR32(0x5030) |= 4;
+
+ // XXX Wait 20ns
+ udelay(1);
+
+ FOR_ALL_CHANNELS {
+ // Set valid rank CKE
+ reg = 0;
+ reg = (reg & ~0xf) | ctrl->rankmap[channel];
+ addr = 0x400 * channel + 0x42a0;
+ MCHBAR32(addr) = reg;
+
+ // Wait 10ns for ranks to settle
+ //udelay(0.01);
+
+ reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4);
+ MCHBAR32(addr) = reg;
+
+ // Write reset using a NOP
+ write_reset(ctrl);
+ }
+}
+
+static odtmap get_ODT(ramctr_timing * ctrl, u8 rank)
+{
+ /* Get ODT based on rankmap: */
+ int dimms_per_ch = 0;
+ int channel;
+
+ FOR_ALL_CHANNELS {
+ dimms_per_ch = max ((ctrl->rankmap[channel] & 1)
+ + ((ctrl->rankmap[channel] >> 2) & 1),
+ dimms_per_ch);
+ }
+
+ if (dimms_per_ch == 1) {
+ return (const odtmap){60, 60};
+ } else if (dimms_per_ch == 2) {
+ return (const odtmap){120, 30};
+ } else {
+ printk(BIOS_DEBUG,
+ "Huh, no dimms? m0 = %d m1 = %d dpc = %d\n",
+ ctrl->rankmap[0],
+ ctrl->rankmap[1], dimms_per_ch);
+ die("");
+ }
+}
+
+static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank,
+ int reg, u32 val)
+{
+ wait_428c(channel);
+
+ printk(BIOS_SPEW, "MRd: %x <= %x\n", reg, val);
+
+ if (ctrl->rank_mirror[channel][slotrank]) {
+ reg = ((reg >> 1) & 1) | ((reg << 1) & 2);
+ val = (val & ~0x1f8) | ((val >> 1) & 0xa8)
+ | ((val & 0xa8) << 1);
+ }
+
+ printk(BIOS_SPEW, "MRd: %x <= %x\n", reg, val);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | (reg << 20) | val | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | (reg << 20) | val | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | (reg << 20) | val | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+}
+
+static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
+{
+ u16 mr0reg, mch_cas, mch_wr;
+ static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 };
+ mr0reg = 0x100;
+
+ // Convert CAS to MCH register friendly
+ if (ctrl->CAS < 12) {
+ mch_cas = (u16) ((ctrl->CAS - 4) << 1);
+ } else {
+ mch_cas = (u16) (ctrl->CAS - 12);
+ mch_cas = ((mch_cas << 1) | 0x1);
+ }
+
+ // Convert tWR to MCH register friendly
+ mch_wr = mch_wr_t[ctrl->tWR - 5];
+
+ mr0reg = (mr0reg & ~0x4) | (mch_cas & 0x1);
+ mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3);
+ mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9);
+ // Fast (desktop) 0x1 or slow (mobile) 0x0
+ mr0reg = (mr0reg & ~0x1000) | (!ctrl->mobile << 12);
+ return mr0reg;
+}
+
+static void dram_mr0(ramctr_timing * ctrl, u8 rank)
+{
+ int channel;
+
+ FOR_ALL_POPULATED_CHANNELS write_mrreg(ctrl, channel, rank, 0,
+ make_mr0(ctrl, rank));
+}
+
+static u32 encode_odt(u32 odt)
+{
+ switch (odt) {
+ case 30:
+ return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4
+ case 60:
+ return (1 << 2); // RZQ/4
+ case 120:
+ return (1 << 6); // RZQ/2
+ default:
+ case 0:
+ return 0;
+ }
+}
+
+static u32 make_mr1(ramctr_timing * ctrl, u8 rank)
+{
+ odtmap odt;
+ u32 mr1reg;
+
+ odt = get_ODT(ctrl, rank);
+ mr1reg = 0x2;
+
+ mr1reg |= encode_odt(odt.rttnom);
+
+ return mr1reg;
+}
+
+static void dram_mr1(ramctr_timing * ctrl, u8 rank)
+{
+ u16 mr1reg;
+ int channel;
+
+ mr1reg = make_mr1(ctrl, rank);
+
+ FOR_ALL_CHANNELS {
+ write_mrreg(ctrl, channel, rank, 1, mr1reg);
+ }
+}
+
+static void dram_mr2(ramctr_timing * ctrl, u8 rank)
+{
+ u16 pasr, cwl, asr, str, mr2reg;
+ odtmap odt;
+ int channel;
+
+ pasr = 0;
+ cwl = ctrl->CWL - 5;
+ asr =
+ (ctrl->thermalrefresh & 0x1) & ((ctrl->thermalrefresh & 0x4) >> 2);
+ /* FIXME: compute STR. */
+ str = 1;
+ odt = get_ODT(ctrl, rank);
+
+ mr2reg = 0;
+ mr2reg = (mr2reg & ~0x7) | pasr;
+ mr2reg = (mr2reg & ~0x38) | (cwl << 3);
+ mr2reg = (mr2reg & ~0x40) | (asr << 6);
+ mr2reg = (mr2reg & ~0x80) | (str << 7);
+ mr2reg |= (odt.rttwr / 60) << 9;
+
+ FOR_ALL_CHANNELS {
+ write_mrreg(ctrl, channel, rank, 2, mr2reg);
+ }
+}
+
+static void dram_mr3(ramctr_timing * ctrl, u8 rank)
+{
+ int channel;
+
+ FOR_ALL_CHANNELS {
+ write_mrreg(ctrl, channel, rank, 3, 0);
+ }
+}
+
+static void dram_mrscommands(ramctr_timing * ctrl)
+{
+ u8 rank;
+ u32 reg, addr;
+ int channel;
+
+ for (rank = 0; rank < 4; rank++) {
+ // MR2
+ printk(BIOS_SPEW, "MR2 rank %d...", rank);
+ dram_mr2(ctrl, rank);
+ printk(BIOS_SPEW, "done\n");
+
+ // MR3
+ printk(BIOS_SPEW, "MR3 rank %d...", rank);
+ dram_mr3(ctrl, rank);
+ printk(BIOS_SPEW, "done\n");
+
+ // MR1
+ printk(BIOS_SPEW, "MR1 rank %d...", rank);
+ dram_mr1(ctrl, rank);
+ printk(BIOS_SPEW, "done\n");
+
+ // MR0
+ printk(BIOS_SPEW, "MR0 rank %d...", rank);
+ dram_mr0(ctrl, rank);
+ printk(BIOS_SPEW, "done\n");
+ }
+
+ write32(DEFAULT_MCHBAR + 0x4e20, 0x7);
+ write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001);
+ write32(DEFAULT_MCHBAR + 0x4e00, 0x60002);
+ write32(DEFAULT_MCHBAR + 0x4e10, 0);
+ write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003);
+ write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001);
+ write32(DEFAULT_MCHBAR + 0x4e04, 0x60400);
+ write32(DEFAULT_MCHBAR + 0x4e14, 0x288);
+ write32(DEFAULT_MCHBAR + 0x4e84, 0x40004);
+
+ // Drain
+ FOR_ALL_CHANNELS {
+ // Wait for ref drained
+ wait_428c(channel);
+ }
+
+ // Refresh enable
+ MCHBAR32(0x5030) |= 8;
+
+ FOR_ALL_POPULATED_CHANNELS {
+ addr = 0x400 * channel + 0x4020;
+ reg = MCHBAR32(addr);
+ reg &= ~0x200000;
+ MCHBAR32(addr) = reg;
+
+ wait_428c(channel);
+
+ rank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
+
+ // Drain
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (rank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1);
+
+ // Drain
+ wait_428c(channel);
+ }
+}
+
+const u32 lane_registers[] = {
+ 0x0000, 0x0200, 0x0400, 0x0600,
+ 0x1000, 0x1200, 0x1400, 0x1600,
+ 0x0800
+};
+
+static int clamp(int val, int low, int up)
+{
+ if (val < low)
+ return low;
+ if (val > up)
+ return up;
+ return val;
+}
+
+static void program_timings(ramctr_timing * ctrl, int channel)
+{
+ u32 reg32, reg_4024, reg_c14, reg_c18, reg_4028;
+ int lane;
+ int slotrank, slot;
+ int full_shift = 0;
+ u16 slot320c[NUM_SLOTS];
+
+ FOR_ALL_POPULATED_RANKS if (full_shift <
+ -ctrl->timings[channel][slotrank].val_320c)
+ full_shift = -ctrl->timings[channel][slotrank].val_320c;
+
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) {
+ case 0:
+ default:
+ slot320c[slot] = 0x7f;
+ break;
+ case 1:
+ slot320c[slot] =
+ ctrl->timings[channel][2 * slot + 0].val_320c +
+ full_shift;
+ break;
+ case 2:
+ slot320c[slot] =
+ ctrl->timings[channel][2 * slot + 1].val_320c +
+ full_shift;
+ break;
+ case 3:
+ slot320c[slot] =
+ (ctrl->timings[channel][2 * slot].val_320c +
+ ctrl->timings[channel][2 * slot +
+ 1].val_320c) / 2 +
+ full_shift;
+ break;
+ }
+
+ reg32 = (1 << 17) | (1 << 14);
+ reg32 |= ((slot320c[0] & 0x3f) << 6) | ((slot320c[0] & 0x40) << 9);
+ reg32 |= (slot320c[1] & 0x7f) << 18;
+ reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6);
+
+ MCHBAR32(0x320c + 0x100 * channel) = reg32;
+
+ reg_c14 = ctrl->rankmap[channel] << 24;
+ reg_c18 = 0;
+
+ FOR_ALL_POPULATED_RANKS {
+ int shift =
+ ctrl->timings[channel][slotrank].val_320c + full_shift;
+ int offset_val_c14;
+ if (shift < 0)
+ shift = 0;
+ offset_val_c14 = ctrl->reg_c14_offset + shift;
+ reg_c14 |= (offset_val_c14 & 0x3f) << (6 * slotrank);
+ reg_c18 |= ((offset_val_c14 >> 6) & 1) << slotrank;
+ }
+
+ MCHBAR32(0xc14 + channel * 0x100) = reg_c14;
+ MCHBAR32(0xc18 + channel * 0x100) = reg_c18;
+
+ reg_4028 = MCHBAR32(0x4028 + 0x400 * channel);
+ reg_4028 &= 0xffff0000;
+
+ reg_4024 = 0;
+
+ FOR_ALL_POPULATED_RANKS {
+ int post_timA_min_high = 7, post_timA_max_high = 0;
+ int pre_timA_min_high = 7, pre_timA_max_high = 0;
+ int shift_402x = 0;
+ int shift =
+ ctrl->timings[channel][slotrank].val_320c + full_shift;
+
+ if (shift < 0)
+ shift = 0;
+
+ FOR_ALL_LANES {
+ if (post_timA_min_high >
+ ((ctrl->timings[channel][slotrank].lanes[lane].
+ timA + shift) >> 6))
+ post_timA_min_high =
+ ((ctrl->timings[channel][slotrank].
+ lanes[lane].timA + shift) >> 6);
+ if (pre_timA_min_high >
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timA >> 6))
+ pre_timA_min_high =
+ (ctrl->timings[channel][slotrank].
+ lanes[lane].timA >> 6);
+ if (post_timA_max_high <
+ ((ctrl->timings[channel][slotrank].lanes[lane].
+ timA + shift) >> 6))
+ post_timA_max_high =
+ ((ctrl->timings[channel][slotrank].
+ lanes[lane].timA + shift) >> 6);
+ if (pre_timA_max_high <
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timA >> 6))
+ pre_timA_max_high =
+ (ctrl->timings[channel][slotrank].
+ lanes[lane].timA >> 6);
+ }
+
+ if (pre_timA_max_high - pre_timA_min_high <
+ post_timA_max_high - post_timA_min_high)
+ shift_402x = +1;
+ else if (pre_timA_max_high - pre_timA_min_high >
+ post_timA_max_high - post_timA_min_high)
+ shift_402x = -1;
+
+ reg_4028 |=
+ (ctrl->timings[channel][slotrank].val_4028 + shift_402x -
+ post_timA_min_high) << (4 * slotrank);
+ reg_4024 |=
+ (ctrl->timings[channel][slotrank].val_4024 +
+ shift_402x) << (8 * slotrank);
+
+ FOR_ALL_LANES {
+ MCHBAR32(lane_registers[lane] + 0x10 + 0x100 * channel +
+ 4 * slotrank)
+ =
+ (((ctrl->timings[channel][slotrank].lanes[lane].
+ timA + shift) & 0x3f)
+ |
+ ((ctrl->timings[channel][slotrank].lanes[lane].
+ rising + shift) << 8)
+ |
+ (((ctrl->timings[channel][slotrank].lanes[lane].
+ timA + shift -
+ (post_timA_min_high << 6)) & 0x1c0) << 10)
+ | (ctrl->timings[channel][slotrank].lanes[lane].
+ falling << 20));
+
+ MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel +
+ 4 * slotrank)
+ =
+ ((clamp
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timC + shift, 0, 127) & 0x3f)
+ |
+ (((ctrl->timings[channel][slotrank].lanes[lane].
+ timB + shift) & 0x3f) << 8)
+ |
+ (((ctrl->timings[channel][slotrank].lanes[lane].
+ timB + shift) & 0x1c0) << 9)
+ |
+ ((clamp
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timC + shift, 0, 127) & 0x40) << 13));
+ }
+ }
+ MCHBAR32(0x4024 + 0x400 * channel) = reg_4024;
+ MCHBAR32(0x4028 + 0x400 * channel) = reg_4028;
+}
+
+static void test_timA(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ (0xc01 | (ctrl->delay1 << 16)));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x100f | ((ctrl->CAS + 36) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ (0xc01 | (ctrl->delay1 << 16)));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+
+ wait_428c(channel);
+}
+
+static int does_lane_work(ramctr_timing * ctrl, int channel, int slotrank,
+ int lane)
+{
+ u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;
+ return ((read32
+ (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 +
+ ((timA / 32) & 1) * 4)
+ >> (timA % 32)) & 1);
+}
+
+struct run {
+ int middle;
+ int end;
+ int start;
+ int all;
+};
+
+static struct run get_longest_zero_run(int *seq, int sz)
+{
+ int i, ls;
+ int bl = 0, bs = 0;
+ struct run ret;
+
+ ls = 0;
+ for (i = 0; i < 2 * sz; i++)
+ if (seq[i % sz]) {
+ if (i - ls > bl) {
+ bl = i - ls;
+ bs = ls;
+ }
+ ls = i + 1;
+ }
+ if (bl == 0) {
+ ret.middle = sz / 2;
+ ret.start = 0;
+ ret.end = sz;
+ ret.all = 1;
+ return ret;
+ }
+
+ ret.start = bs % sz;
+ ret.end = (bs + bl - 1) % sz;
+ ret.middle = (bs + (bl - 1) / 2) % sz;
+ ret.all = 0;
+
+ return ret;
+}
+
+static void discover_timA_coarse(ramctr_timing * ctrl, int channel,
+ int slotrank, int *upperA)
+{
+ int timA;
+ int statistics[NUM_LANES][128];
+ int lane;
+
+ for (timA = 0; timA < 128; timA++) {
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
+ timA = timA;
+ program_timings(ctrl, channel);
+
+ test_timA(ctrl, channel, slotrank);
+
+ FOR_ALL_LANES {
+ statistics[lane][timA] =
+ !does_lane_work(ctrl, channel, slotrank, lane);
+ printk(BIOS_SPEW, "Astat: %d, %d, %d, %x, %x\n",
+ channel, slotrank, lane, timA,
+ statistics[lane][timA]);
+ }
+ }
+ FOR_ALL_LANES {
+ struct run rn = get_longest_zero_run(statistics[lane], 128);
+ ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle;
+ upperA[lane] = rn.end;
+ if (upperA[lane] < rn.middle)
+ upperA[lane] += 128;
+ printk(BIOS_SPEW, "Aval: %d, %d, %d, %x\n", channel, slotrank,
+ lane, ctrl->timings[channel][slotrank].lanes[lane].timA);
+ printk(BIOS_SPEW, "Aend: %d, %d, %d, %x\n", channel, slotrank,
+ lane, upperA[lane]);
+ }
+}
+
+static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank,
+ int *upperA)
+{
+ int timA_delta;
+ int statistics[NUM_LANES][51];
+ int lane, i;
+
+ memset(statistics, 0, sizeof(statistics));
+
+ for (timA_delta = -25; timA_delta <= 25; timA_delta++) {
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
+ timA = upperA[lane] + timA_delta + 0x40;
+ program_timings(ctrl, channel);
+
+ for (i = 0; i < 100; i++) {
+ test_timA(ctrl, channel, slotrank);
+ FOR_ALL_LANES {
+ statistics[lane][timA_delta + 25] +=
+ does_lane_work(ctrl, channel, slotrank,
+ lane);
+ }
+ }
+ FOR_ALL_LANES {
+ printk(BIOS_SPEW, "A+stat: %d, %d, %d, %d (%x), %x\n",
+ channel, slotrank, lane, timA_delta,
+ upperA[lane] + timA_delta + 0x40,
+ statistics[lane][timA_delta + 25]);
+ }
+ }
+ FOR_ALL_LANES {
+ int last_zero, first_all;
+
+ for (last_zero = -25; last_zero <= 25; last_zero++)
+ if (statistics[lane][last_zero + 25])
+ break;
+ last_zero--;
+ for (first_all = -25; first_all <= 25; first_all++)
+ if (statistics[lane][first_all + 25] == 100)
+ break;
+
+ printk(BIOS_SPEW, "lane %d: %d, %d\n", lane, last_zero,
+ first_all);
+
+ ctrl->timings[channel][slotrank].lanes[lane].timA =
+ (last_zero + first_all) / 2 + upperA[lane];
+ printk(BIOS_SPEW, "Aval: %d, %d, %d, %x\n", channel, slotrank,
+ lane, ctrl->timings[channel][slotrank].lanes[lane].timA);
+ }
+}
+
+static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank,
+ int *upperA)
+{
+ int works[NUM_LANES];
+ int lane;
+ while (1) {
+ int all_works = 1, some_works = 0;
+ program_timings(ctrl, channel);
+ test_timA(ctrl, channel, slotrank);
+ FOR_ALL_LANES {
+ works[lane] =
+ !does_lane_work(ctrl, channel, slotrank, lane);
+ if (works[lane])
+ some_works = 1;
+ else
+ all_works = 0;
+ }
+ if (all_works)
+ return;
+ if (!some_works) {
+ if (ctrl->timings[channel][slotrank].val_4024 < 2)
+ die("402x discovery failed");
+ ctrl->timings[channel][slotrank].val_4024 -= 2;
+ printk(BIOS_SPEW, "4024 -= 2;\n");
+ continue;
+ }
+ ctrl->timings[channel][slotrank].val_4028 += 2;
+ printk(BIOS_SPEW, "4028 += 2;\n");
+ if (ctrl->timings[channel][slotrank].val_4028 >= 0x10)
+ die("402x discovery failed");
+ FOR_ALL_LANES if (works[lane]) {
+ ctrl->timings[channel][slotrank].lanes[lane].timA +=
+ 128;
+ upperA[lane] += 128;
+ printk(BIOS_SPEW, "increment %d, %d, %d\n", channel,
+ slotrank, lane);
+ }
+ }
+}
+
+struct timA_minmax {
+ int timA_min_high, timA_max_high;
+};
+
+static void pre_timA_change(ramctr_timing * ctrl, int channel, int slotrank,
+ struct timA_minmax *mnmx)
+{
+ int lane;
+ mnmx->timA_min_high = 7;
+ mnmx->timA_max_high = 0;
+
+ FOR_ALL_LANES {
+ if (mnmx->timA_min_high >
+ (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6))
+ mnmx->timA_min_high =
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timA >> 6);
+ if (mnmx->timA_max_high <
+ (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6))
+ mnmx->timA_max_high =
+ (ctrl->timings[channel][slotrank].lanes[lane].
+ timA >> 6);
+ }
+}
+
+static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank,
+ struct timA_minmax *mnmx)
+{
+ struct timA_minmax post;
+ int shift_402x = 0;
+
+ /* Get changed maxima. */
+ pre_timA_change(ctrl, channel, slotrank, &post);
+
+ if (mnmx->timA_max_high - mnmx->timA_min_high <
+ post.timA_max_high - post.timA_min_high)
+ shift_402x = +1;
+ else if (mnmx->timA_max_high - mnmx->timA_min_high >
+ post.timA_max_high - post.timA_min_high)
+ shift_402x = -1;
+ else
+ shift_402x = 0;
+
+ ctrl->timings[channel][slotrank].val_4028 += shift_402x;
+ ctrl->timings[channel][slotrank].val_4024 += shift_402x;
+ printk(BIOS_SPEW, "4024 += %d;\n", shift_402x);
+ printk(BIOS_SPEW, "4028 += %d;\n", shift_402x);
+}
+
+static void read_training(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ u32 r32;
+ int all_high, some_high;
+ int upperA[NUM_LANES];
+ struct timA_minmax mnmx;
+
+ wait_428c(channel);
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+
+ write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001);
+
+ ctrl->timings[channel][slotrank].val_4028 = 4;
+ ctrl->timings[channel][slotrank].val_4024 = 55;
+ program_timings(ctrl, channel);
+
+ discover_timA_coarse(ctrl, channel, slotrank, upperA);
+
+ all_high = 1;
+ some_high = 0;
+ FOR_ALL_LANES if (ctrl->timings[channel][slotrank].lanes[lane].
+ timA >= 0x40)
+ some_high = 1;
+ else
+ all_high = 0;
+ if (all_high) {
+ ctrl->timings[channel][slotrank].val_4028--;
+ printk(BIOS_SPEW, "4028--;\n");
+ FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].
+ timA -= 0x40;
+ upperA[lane] -= 0x40;
+ }} else if (some_high) {
+ ctrl->timings[channel][slotrank].val_4024++;
+ ctrl->timings[channel][slotrank].val_4028++;
+ printk(BIOS_SPEW, "4024++;\n");
+ printk(BIOS_SPEW, "4028++;\n");
+ }
+
+ program_timings(ctrl, channel);
+
+ pre_timA_change(ctrl, channel, slotrank, &mnmx);
+
+ discover_402x(ctrl, channel, slotrank, upperA);
+
+ post_timA_change(ctrl, channel, slotrank, &mnmx);
+ pre_timA_change(ctrl, channel, slotrank, &mnmx);
+
+ discover_timA_fine(ctrl, channel, slotrank, upperA);
+
+ post_timA_change(ctrl, channel, slotrank, &mnmx);
+ pre_timA_change(ctrl, channel, slotrank, &mnmx);
+
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
+ timA -= mnmx.timA_min_high * 0x40;
+ ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high;
+ printk(BIOS_SPEW, "4028 -= %d;\n", mnmx.timA_min_high);
+
+ post_timA_change(ctrl, channel, slotrank, &mnmx);
+
+ printk(BIOS_SPEW, "4/8: %d, %d, %x, %x\n", channel, slotrank,
+ ctrl->timings[channel][slotrank].val_4024,
+ ctrl->timings[channel][slotrank].val_4028);
+
+ FOR_ALL_LANES
+ printk(BIOS_SPEW, "%d, %d, %d, %x\n", channel, slotrank,
+ lane,
+ ctrl->timings[channel][slotrank].lanes[lane].timA);
+
+ write32(DEFAULT_MCHBAR + 0x3400, 0);
+
+ r32 = read32(DEFAULT_MCHBAR + 0x5030);
+ write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ udelay(1);
+
+ write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+
+ udelay(1);
+ }
+
+ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
+ FOR_ALL_LANES write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel +
+ 4 * lane, 0);
+}
+
+static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ int lane;
+
+ FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane,
+ 0);
+ read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane);
+ }
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
+ | 4 | (ctrl->tRCD << 16));
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | (6 << 16));
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 8);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4);
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 8);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
+ | 8 | (ctrl->CAS << 16));
+
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x40011f4 | (max(ctrl->tRTP, 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ wait_428c(channel);
+}
+
+static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ int timC;
+ int statistics[NUM_LANES][MAX_TIMC + 1];
+ int lane;
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+
+ for (timC = 0; timC <= MAX_TIMC; timC++) {
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
+ timC = timC;
+ program_timings(ctrl, channel);
+
+ test_timC(ctrl, channel, slotrank);
+
+ FOR_ALL_LANES {
+ statistics[lane][timC] =
+ read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
+ 0x400 * channel);
+ printk(BIOS_SPEW, "Cstat: %d, %d, %d, %x, %x\n",
+ channel, slotrank, lane, timC,
+ statistics[lane][timC]);
+ }
+ }
+ FOR_ALL_LANES {
+ struct run rn =
+ get_longest_zero_run(statistics[lane], MAX_TIMC + 1);
+ ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle;
+ if (rn.all)
+ die("timC discovery failed");
+ printk(BIOS_SPEW, "Cval: %d, %d, %d, %x\n", channel, slotrank,
+ lane, ctrl->timings[channel][slotrank].lanes[lane].timC);
+ }
+}
+
+static int get_precedening_channels(ramctr_timing * ctrl, int target_channel)
+{
+ int channel, ret = 0;
+ FOR_ALL_POPULATED_CHANNELS if (channel < target_channel)
+ ret++;
+ return ret;
+}
+
+static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
+{
+ unsigned j;
+ unsigned channel_offset =
+ get_precedening_channels(ctrl, channel) * 0x40;
+ printk(BIOS_SPEW, "channel_offset=%x\n", channel_offset);
+ for (j = 0; j < 16; j++)
+ write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a);
+ sfence();
+}
+
+static int num_of_channels(const ramctr_timing * ctrl)
+{
+ int ret = 0;
+ int channel;
+ FOR_ALL_POPULATED_CHANNELS ret++;
+ return ret;
+}
+
+static void fill_pattern1(ramctr_timing * ctrl, int channel)
+{
+ unsigned j;
+ unsigned channel_offset =
+ get_precedening_channels(ctrl, channel) * 0x40;
+ unsigned channel_step = 0x40 * num_of_channels(ctrl);
+ for (j = 0; j < 16; j++)
+ write32(0x04000000 + channel_offset + j * 4, 0xffffffff);
+ for (j = 0; j < 16; j++)
+ write32(0x04000000 + channel_offset + channel_step + j * 4, 0);
+ sfence();
+}
+
+static void precharge(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+
+ FOR_ALL_POPULATED_CHANNELS {
+ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ 16;
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ 16;
+ } program_timings(ctrl, channel);
+
+ FOR_ALL_POPULATED_RANKS {
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x4041003);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | ((ctrl->CAS + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ 0xc0001);
+
+ wait_428c(channel);
+ }
+
+ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ 48;
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ 48;
+ } program_timings(ctrl, channel);
+
+ FOR_ALL_POPULATED_RANKS {
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x4041003);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | ((ctrl->CAS + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ 0xc0001);
+ wait_428c(channel);
+ }
+ }
+}
+
+static void test_timB(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ write_mrreg(ctrl, channel, slotrank, 1,
+ 0x80 | make_mr1(ctrl, slotrank));
+
+ wait_428c(channel);
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0x8000c01 | ((ctrl->CWL + ctrl->delay2) << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ 8 | (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x4000c01 | ((ctrl->CAS + 38) << 16));
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 4);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001);
+ wait_428c(channel);
+
+ write_mrreg(ctrl, channel, slotrank, 1,
+ 0x1080 | make_mr1(ctrl, slotrank));
+}
+
+static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ int timB;
+ int statistics[NUM_LANES][128];
+ int lane;
+
+ write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2));
+
+ for (timB = 0; timB < 128; timB++) {
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
+ timB = timB;
+ program_timings(ctrl, channel);
+
+ test_timB(ctrl, channel, slotrank);
+
+ FOR_ALL_LANES {
+ statistics[lane][timB] =
+ !((read32
+ (DEFAULT_MCHBAR + lane_registers[lane] +
+ channel * 0x100 + 4 + ((timB / 32) & 1) * 4)
+ >> (timB % 32)) & 1);
+ printk(BIOS_SPEW, "Bstat: %d, %d, %d, %x, %x\n",
+ channel, slotrank, lane, timB,
+ statistics[lane][timB]);
+ }
+ }
+ FOR_ALL_LANES {
+ struct run rn = get_longest_zero_run(statistics[lane], 128);
+ ctrl->timings[channel][slotrank].lanes[lane].timB = rn.end;
+ if (rn.all)
+ die("timB discovery failed");
+ printk(BIOS_SPEW, "Bval: %d, %d, %d, %x\n", channel, slotrank,
+ lane, ctrl->timings[channel][slotrank].lanes[lane].timB);
+ }
+}
+
+static int get_timB_high_adjust(u64 val)
+{
+ int i;
+ if (val >= 0xfffffffffff00000LL)
+ return -1;
+ if (val >= 0xfffffff000000000LL)
+ return -2;
+ if (val >= 0xfff0000000000000LL)
+ return -3;
+
+ for (i = 0; i < 8; i++)
+ if (val >> (8 * (7 - i) + 4))
+ return i;
+ return 8;
+}
+
+static void adjust_high_timB(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+ write32(DEFAULT_MCHBAR + 0x3400, 0x200);
+ FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern1(ctrl, channel);
+ write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 1);
+ }
+ FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
+
+ write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001);
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->tRCD << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0x8);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003);
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x8);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | ((ctrl->tRP) << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0xc01 | ((ctrl->tRCD) << 16));
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x4000c01 |
+ ((ctrl->tRP +
+ ctrl->timings[channel][slotrank].val_4024 +
+ ctrl->timings[channel][slotrank].val_4028) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60008);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+ wait_428c(channel);
+ FOR_ALL_LANES {
+ u64 res =
+ read32(DEFAULT_MCHBAR + lane_registers[lane] +
+ 0x100 * channel + 4);
+ res |=
+ ((u64)
+ read32(DEFAULT_MCHBAR + lane_registers[lane] +
+ 0x100 * channel + 8)) << 32;
+ ctrl->timings[channel][slotrank].lanes[lane].timB +=
+ get_timB_high_adjust(res) * 64;
+ printk(BIOS_SPEW, "Bval+: %d, %d, %d, %x\n", channel,
+ slotrank, lane,
+ ctrl->timings[channel][slotrank].lanes[lane].
+ timB);
+ }} write32(DEFAULT_MCHBAR + 0x3400, 0);
+}
+
+static void write_op(ramctr_timing * ctrl, int channel)
+{
+ int slotrank;
+
+ wait_428c(channel);
+
+ /* choose an existing rank. */
+ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ wait_428c(channel);
+}
+
+static void write_training(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+ u32 r32;
+
+ FOR_ALL_POPULATED_CHANNELS
+ write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
+ read32(DEFAULT_MCHBAR + 0x4008 +
+ 0x400 * channel) | 0x8000000);
+
+ FOR_ALL_POPULATED_CHANNELS {
+ write_op(ctrl, channel);
+ write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
+ read32(DEFAULT_MCHBAR + 0x4020 +
+ 0x400 * channel) | 0x200000);
+ }
+ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ FOR_ALL_POPULATED_CHANNELS {
+ write_op(ctrl, channel);
+ }
+
+ FOR_ALL_CHANNELS
+ FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1,
+ make_mr1(ctrl,
+ slotrank) | 0x1080);
+
+ write32(DEFAULT_MCHBAR + 0x3400, 0x108052);
+
+ r32 = read32(DEFAULT_MCHBAR + 0x5030);
+ write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ udelay(1);
+
+ write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+
+ udelay(1);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS discover_timB(ctrl, channel,
+ slotrank);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel,
+ slotrank, 1,
+ make_mr1(ctrl,
+ slotrank));
+
+ write32(DEFAULT_MCHBAR + 0x3400, 0);
+
+ FOR_ALL_POPULATED_CHANNELS wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8);
+
+ FOR_ALL_POPULATED_CHANNELS {
+ write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
+ ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 +
+ 0x400 * channel));
+ read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel);
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ wait_428c(channel);
+ }
+
+ r32 = read32(DEFAULT_MCHBAR + 0x5030);
+ write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ udelay(1);
+
+ write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+
+ udelay(1);
+
+ printk(BIOS_SPEW, "CPE\n");
+ precharge(ctrl);
+ printk(BIOS_SPEW, "CPF\n");
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
+ write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ 0);
+ } FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);
+ write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ }
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS discover_timC(ctrl, channel,
+ slotrank);
+
+ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+
+ adjust_high_timB(ctrl);
+
+ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
+ write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ 0);
+}} static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
+{
+ struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank];
+ int timC_delta;
+ int lanes_ok = 0;
+ int ctr = 0;
+ int lane;
+
+ for (timC_delta = -5; timC_delta <= 5; timC_delta++) {
+ FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].timC =
+ saved_rt.lanes[lane].timC + timC_delta;
+ }
+ program_timings(ctrl, channel);
+ FOR_ALL_LANES write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
+ | 8 | (ctrl->tRCD << 16));
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | ctr | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x4001020 | (max(ctrl->tRTP, 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001);
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ wait_428c(channel);
+ FOR_ALL_LANES {
+ u32 r32 =
+ read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
+ 0x400 * channel);
+
+ if (r32 == 0)
+ lanes_ok |= 1 << lane;
+ }
+ ctr++;
+ if (lanes_ok == ((1 << NUM_LANES) - 1))
+ break;
+ }
+
+ ctrl->timings[channel][slotrank] = saved_rt;
+ return lanes_ok != ((1 << NUM_LANES) - 1);
+}
+
+const u32 pattern[][16] = {
+ {0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff},
+ {0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000},
+ {0xe62d6424, 0x9277e09e, 0x8f43dc3f, 0x76eae589,
+ 0x0010fdc6, 0xdc55e01c, 0x5effb0ab, 0x6cba5d29,
+ 0xa43d1e64, 0xab5c2e0f, 0x7796ed16, 0x96023bf4,
+ 0xa74c831d, 0x90f138c0, 0x17830a8a, 0x5ac17c47},
+ {0x359ebbeb, 0x2b9b4512, 0xef584d98, 0x106bf7cb,
+ 0x363525ad, 0xb3a4dfdc, 0xa6b9fcd8, 0xd21689ec,
+ 0x84a3695b, 0xbd9c2e27, 0xdb3d0f44, 0x988158f1,
+ 0xcca91d3f, 0xb62a6d12, 0xe905e4cf, 0x7f1fa626},
+ {0xe58efeae, 0xcd006081, 0xa9119403, 0xbcfbd35f,
+ 0x213b3bf7, 0x7bfcb773, 0xc85143f9, 0x0bdbff50,
+ 0xa3053c90, 0x51d66cb7, 0x296f4387, 0xb715f99e,
+ 0xfaddc989, 0xbb1de8a7, 0x39206b4d, 0x80174a57},
+ {0xa1622ac1, 0xb4f4a5f0, 0x16dc2bc3, 0x50fb0954,
+ 0x2e261721, 0x52b82c3c, 0x821902b8, 0x0d4b6c38,
+ 0x1f618631, 0x047956f3, 0xd4337f5a, 0x591f8002,
+ 0x27f28db2, 0xfae37369, 0xb3f27580, 0x3cdb6397},
+ {0x3dee23be, 0x19f36408, 0x227f4a6a, 0x024603c5,
+ 0xd5e062db, 0x6d8d4c5c, 0x7ff693b0, 0x76641be9,
+ 0x9e74f41c, 0xe7bc7f33, 0x2636f2e9, 0x70279750,
+ 0xce2355aa, 0x32d230ef, 0x22f9b468, 0xadd4e7a2},
+ {0x936c0fed, 0xba0612d5, 0xa97c1ea7, 0x10e29d67,
+ 0x1c4c5dc8, 0x83645621, 0xcd8b521c, 0xb8301817,
+ 0xac7d6571, 0xcc41d200, 0x4ebdefdd, 0xd2917bde,
+ 0x60f75acc, 0x7791534b, 0x26ea2a83, 0x6b74513a},
+ {0xd1957b85, 0xc6f8f9ca, 0xf04fb4be, 0xfeb786fb,
+ 0xa1dea3aa, 0x67fe7db6, 0x25d49c87, 0xe3d54870,
+ 0x93dc1f86, 0x7d0c1a18, 0x9272e128, 0x68e1b876,
+ 0xce284c9e, 0x8fa18792, 0x5785a340, 0xb6fcf198},
+ {0xff7d8e4a, 0x0c21ee43, 0xe820b388, 0xb4443c0e,
+ 0xa1e6e498, 0x5c426110, 0x1b434ef3, 0xbef05b91,
+ 0xa6907968, 0x53662ac3, 0x6defac32, 0x2c11c29c,
+ 0x6175cced, 0xb17dd3ad, 0x6e6a1076, 0x1372b1fa},
+ {0x4408ed06, 0x49460ffd, 0xb49d26cb, 0x6a3662a5,
+ 0x5e857047, 0xa387cd4a, 0x04edc81e, 0xfd94d8d4,
+ 0x2fe48d91, 0x9d2356bc, 0x96131878, 0xaca3fce4,
+ 0xbb312c6c, 0x5023b090, 0x3614be70, 0xa14dfabb},
+ {0xd4cc1e83, 0x757a1930, 0xc3d16a61, 0x9e0d6681,
+ 0x8a081fa9, 0xbd11c888, 0x1672f010, 0xa083f71c,
+ 0x1ec02eef, 0xc4586ca8, 0x6d322b35, 0x56054679,
+ 0x1552a0ff, 0x5cb7707e, 0xdfb55d4a, 0xcc76cc07},
+ {0x507cf71f, 0x2166421a, 0x54be4af0, 0xfd42158c,
+ 0x417b1f7f, 0x9466860b, 0x3a0075bf, 0x2055575c,
+ 0xcedfe7ab, 0xbe85aa5f, 0x39d0c2e3, 0x851c19df,
+ 0x39a35a3f, 0x3fb10d7d, 0x20b14899, 0x703b7f08},
+ {0x8a7d9dd1, 0x33235565, 0xbd3d2e57, 0xa48c2726,
+ 0x0d5e2e13, 0xae421ff9, 0x8784a224, 0xf66c1510,
+ 0x057627aa, 0x8fb0cb41, 0x4289975a, 0xb181adfa,
+ 0x59f2059a, 0xe86feb05, 0x84222fc1, 0x319b3ce9},
+ {0xe1e243b8, 0x3b0bcc1a, 0x70396f00, 0x5caff44d,
+ 0xe96961b3, 0xad73f692, 0x8b841a2d, 0xf5838839,
+ 0xec9c9d04, 0xcc2b5562, 0xf8ca2549, 0xa9c52ff8,
+ 0x3b2fde68, 0x3d4dc7f0, 0xa57387d0, 0x051199ad},
+ {0x5f0ce4fc, 0xd830fbb7, 0x90abeb8f, 0x96d9cdbb,
+ 0x58f80a80, 0x0baaca36, 0x81a23623, 0x77127614,
+ 0xaa8382cd, 0x0922fbca, 0xd84d37e1, 0x721297df,
+ 0x160f3b3a, 0x10a1ecdc, 0x151c92f4, 0xc1fdcdab},
+ {0x261c45cc, 0xfeddd2da, 0xfc3cb1c1, 0x6639641f,
+ 0x2c011892, 0x7108bee2, 0x8545e0b9, 0x7dd36dab,
+ 0x07d91950, 0x1520adcb, 0xf84aa939, 0x07d9bb2d,
+ 0xdf1ed826, 0xaee3c814, 0x1dca1e81, 0xc8e9f486},
+ {0x933d306a, 0xaab7103d, 0xa8be37be, 0x49612f3a,
+ 0xb0cf28e5, 0xf9648902, 0x106d7c11, 0xf32e1813,
+ 0x21af36ef, 0xe695e4c4, 0x7ee1831d, 0x2aeda467,
+ 0x99d0c655, 0x3f0691ab, 0xcd68f7c1, 0xb469a20e},
+ {0x8557aef0, 0x3eb0e373, 0x0853ac31, 0xe5bded62,
+ 0x3eddb0dd, 0x6bbf1caf, 0x2119c3d9, 0xe1732350,
+ 0x55456c75, 0xf6119375, 0x498dd1ad, 0x13f80916,
+ 0xb97f9f5e, 0x921d9f4c, 0xabdee367, 0x1d6bb8bf},
+ {0xd165a3be, 0xd8b41598, 0xa20e1809, 0xefd5c8ce,
+ 0x18935c80, 0xdf1911f9, 0xc9e449eb, 0xb887a4d7,
+ 0x4a324f6f, 0x533e8031, 0x1c21c074, 0xa95f1ea5,
+ 0x765b320a, 0x839d7dfb, 0xc7d3aa93, 0xe534ae3d},
+ {0xbe8592c8, 0x068457e6, 0x89b94fa3, 0xd522ad02,
+ 0x7e7db0b7, 0x2c5b896f, 0x9f8ecb37, 0x05b983ff,
+ 0x3fe9b25f, 0x34a6215b, 0x0592ba34, 0xd564f85a,
+ 0x156c426d, 0x25ad5460, 0xe7b5e8b7, 0xa73285c6},
+ {0x5ad8d838, 0x27b42d36, 0xcc806ad1, 0x157a058a,
+ 0x7297735a, 0xffd6df8d, 0xff96f7a2, 0x155b27ea,
+ 0x84708101, 0x979fd78b, 0x49797d0c, 0x0dc93e3c,
+ 0x20287332, 0xed759f88, 0xe5068529, 0xb83aa781},
+ {0xc38b302c, 0x57b54075, 0xac810692, 0xb0d493e7,
+ 0x4adda486, 0x0665ce2e, 0xb2a9c003, 0xafacc4ce,
+ 0x4d5e906d, 0xb3d52fab, 0xe6962c6b, 0x850f4dd1,
+ 0x5021656c, 0x5df6c06b, 0x9255125b, 0x2363c478},
+ {0x188b715c, 0xe8b884b0, 0x5e6d0b9a, 0x1f0051e1,
+ 0xd2d35d4c, 0xbfeaecbe, 0xc84bb0ad, 0x67a232d6,
+ 0x99001587, 0xbf4313e1, 0x74f64061, 0x2c1fc562,
+ 0xb6fe8ca6, 0x5226a239, 0xf5198574, 0x61b51dca},
+ {0x51dcecd3, 0xbadbe596, 0xebe3e84a, 0x772bfdfc,
+ 0x03656ac5, 0xa7c36e91, 0x6cd32cf0, 0xc3f699dd,
+ 0x7d5aba01, 0x51e38e82, 0x23103a98, 0x20298b9d,
+ 0x19436510, 0x63ad7e6c, 0x8bc2b33f, 0x27079917},
+ {0x8bd5be78, 0xf2403bfa, 0x780ebdb6, 0x94c53b64,
+ 0x6241c2e2, 0x5bfb081e, 0x6799e88f, 0xc997b7d1,
+ 0x466ac8b1, 0xbf5909da, 0x497ea39f, 0x402ffb48,
+ 0xd7470c2d, 0x8510aba9, 0x6c52a1c9, 0x812ca967},
+ {0x031f7ab4, 0xd32fe890, 0x36ae6de5, 0x083dcde4,
+ 0x99a7f12f, 0xe44864a7, 0x02b75fff, 0xf25dda35,
+ 0x7679ff4f, 0xed421e01, 0xd9c2cfa1, 0xd36b4e82,
+ 0x5315d908, 0xc7ebcb2a, 0xb6f3e4c1, 0xf5bfbae9},
+ {0x3f4a2a96, 0x64d8bd5a, 0x19acd70d, 0xf62fcdd9,
+ 0x5de99cdf, 0x32f3b7cb, 0x2c020578, 0x4e9bafb8,
+ 0x74919a08, 0xaba33e91, 0xa6bd2254, 0x2435a9b9,
+ 0x47e2a1b4, 0xe837a28e, 0xe113f1b0, 0x7654bd79},
+ {0x05537a6c, 0x77be1a5c, 0x4c7492c9, 0x9086bfb0,
+ 0x257adc18, 0xf4787fc1, 0xe3fb6d53, 0x9525e589,
+ 0x445a65bc, 0x833f7d08, 0x69cf1f7e, 0x9a6372e1,
+ 0xceedb52e, 0x31032997, 0xd1c36828, 0x132772d6},
+ {0x0a166972, 0x89beaf3b, 0x8d780fbc, 0x8aea5392,
+ 0x58347a41, 0x1e381ec2, 0xcc6280c8, 0xee0863e1,
+ 0x976e2dd2, 0x8c6ee6e2, 0xa0ca57cd, 0x95114a7d,
+ 0x3c096704, 0xa941769d, 0x2de20c05, 0x0bf8f812},
+ {0x22779d6c, 0x94e12e8f, 0x5ce40299, 0xea1b55b0,
+ 0x9ebec05d, 0xe076cd2b, 0x8fef5648, 0x6a284c65,
+ 0xa790b705, 0xf0b19997, 0x0d8ca8af, 0x17440419,
+ 0xef4f702f, 0x33cbcbb1, 0x83d60f26, 0x48988397},
+ {0x0fed7f53, 0xb5acbb67, 0xc031c73f, 0x5364d9ef,
+ 0xa6dbd12d, 0x82174a6c, 0xccf8e7ab, 0xc473c036,
+ 0xcff493d8, 0xad9afc3b, 0x316a24e8, 0x1842bea4,
+ 0x4cc0c82e, 0x28ccd91e, 0xd7311b5d, 0x50a89860},
+};
+
+static void fill_pattern5(ramctr_timing * ctrl, int channel)
+{
+ unsigned i, j;
+ unsigned channel_offset =
+ get_precedening_channels(ctrl, channel) * 0x40;
+ unsigned channel_step = 0x40 * num_of_channels(ctrl);
+ for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) {
+ for (j = 0; j < 16; j++)
+ write32(0x04000000 + channel_offset + i * channel_step +
+ j * 4, pattern[i][j]);
+ }
+ sfence();
+}
+
+static void reprogram_320c(ramctr_timing * ctrl)
+{
+ int channel, slotrank;
+ u32 r32;
+
+ FOR_ALL_POPULATED_CHANNELS {
+ wait_428c(channel);
+
+ /* choose an existing rank. */
+ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ wait_428c(channel);
+ write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
+ read32(DEFAULT_MCHBAR + 0x4020 +
+ 0x400 * channel) | 0x200000);
+ }
+ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ FOR_ALL_POPULATED_CHANNELS {
+ wait_428c(channel);
+
+ /* choose an existing rank. */
+ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ wait_428c(channel);
+ }
+
+ /* jedec reset */
+ dram_jedecreset(ctrl);
+ /* mrs commands. */
+ dram_mrscommands(ctrl);
+
+ r32 = read32(DEFAULT_MCHBAR + 0x5030);
+ write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ udelay(1);
+
+ write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+
+ udelay(1);
+}
+
+static void command_training(ramctr_timing * ctrl)
+{
+ int channel;
+ int slotrank;
+ u32 reg_4004_b30;
+ int delta = 0;
+ int c320c;
+ int stat[NUM_SLOTRANKS][256];
+
+ /* FIXME: vendor BIOS discovers this by trying 0 and 2. Apparently 2 should work for
+ all systems but 0 is slightly more efficient for the systems that can tolerate it.
+ */
+ reg_4004_b30 = 2;
+
+ FOR_ALL_POPULATED_CHANNELS
+ /* FIXME: avoid unnecessarry readback. */
+ MCHBAR32(0x4004 + 0x400 * channel) =
+ (MCHBAR32(0x4004 + 0x400 * channel) & ~(3 << 30))
+ | (reg_4004_b30 << 30);
+
+ if (reg_4004_b30 == 2)
+ delta = 2;
+ else if (reg_4004_b30 == 0)
+ delta = 4;
+
+ FOR_ALL_CHANNELS {
+ FOR_ALL_POPULATED_RANKS ctrl->timings[channel][slotrank].
+ val_4024 -= delta;
+ }
+
+ FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern5(ctrl, channel);
+ write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ }
+
+ FOR_ALL_POPULATED_CHANNELS {
+ for (c320c = -127; c320c <= 127; c320c++) {
+ FOR_ALL_POPULATED_RANKS ctrl->
+ timings[channel][slotrank].val_320c = c320c;
+ program_timings(ctrl, channel);
+ reprogram_320c(ctrl);
+ FOR_ALL_POPULATED_RANKS {
+ stat[slotrank][c320c + 127] =
+ test_320c(ctrl, channel, slotrank);
+ printk(BIOS_SPEW, "3stat: %d, %d, %d: %d\n",
+ channel, slotrank, c320c,
+ stat[slotrank][c320c + 127]);
+ }
+ }
+ FOR_ALL_POPULATED_RANKS {
+ struct run rn =
+ get_longest_zero_run(stat[slotrank], 255);
+ ctrl->timings[channel][slotrank].val_320c =
+ rn.middle - 127;
+ printk(BIOS_SPEW, "3val: %d, %d: %d\n", channel,
+ slotrank,
+ ctrl->timings[channel][slotrank].val_320c);
+ if (rn.all)
+ die("c320c discovery failed");
+ }
+ }
+
+ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+
+ reprogram_320c(ctrl);
+}
+
+static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank,
+ int *edges)
+{
+ int edge;
+ int statistics[NUM_LANES][MAX_EDGE_TIMING + 1];
+ int lane;
+
+ for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) {
+ FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ edge;
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ edge;
+ }
+ printk(BIOS_SPEW, "edge %02x\n", edge);
+ program_timings(ctrl, channel);
+
+ FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
+ 4 * lane, 0);
+ read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane +
+ 0x4140);
+ }
+
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ (0xc01 | (ctrl->delay1 << 16)));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | ((ctrl->CAS + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ (0xc01 | (ctrl->delay1 << 16)));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+
+ wait_428c(channel);
+
+ FOR_ALL_LANES {
+ statistics[lane][edge] =
+ read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
+ lane * 4);
+ printk(BIOS_SPEW, "estat %d, %d, %d, %d %02x\n",
+ channel, slotrank, lane, edge,
+ statistics[lane][edge]);
+ }
+ }
+ FOR_ALL_LANES {
+ struct run rn =
+ get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1);
+ edges[lane] = rn.middle;
+ if (rn.all)
+ die("edge discovery failed");
+ printk(BIOS_SPEW, "eval %d, %d, %d, %02x\n", channel, slotrank,
+ lane, edges[lane]);
+ }
+}
+
+static void discover_edges(ramctr_timing * ctrl)
+{
+ int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int channel, slotrank, lane;
+ u32 r32;
+
+ write32(DEFAULT_MCHBAR + 0x3400, 0);
+
+ r32 = read32(DEFAULT_MCHBAR + 0x5030);
+ write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ udelay(1);
+
+ write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+
+ udelay(1);
+
+ FOR_ALL_POPULATED_CHANNELS {
+ FOR_ALL_LANES write32(DEFAULT_MCHBAR + 4 * lane +
+ 0x400 * channel + 0x4080, 0);
+ }
+
+ FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern0(ctrl, channel, 0, 0);
+ write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ FOR_ALL_LANES read32(DEFAULT_MCHBAR + 0x400 * channel +
+ lane * 4 + 0x4140);
+
+ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ 16;
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ 16;
+ } program_timings(ctrl, channel);
+
+ FOR_ALL_POPULATED_RANKS {
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x4041003);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | ((ctrl->CAS + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ 0xc0001);
+
+ wait_428c(channel);
+ }
+
+ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ 48;
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ 48;
+ } program_timings(ctrl, channel);
+
+ FOR_ALL_POPULATED_RANKS {
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x360004);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x4041003);
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24) | 0);
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x1001 | ((ctrl->CAS + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ 0x1f000);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->delay1 << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x360000);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ 0xc0001);
+ wait_428c(channel);
+ }
+
+ FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel +
+ lane * 4,
+ ~read32(DEFAULT_MCHBAR + 0x4040 +
+ 0x400 * channel + lane * 4) & 0xff);
+ }
+
+ fill_pattern0(ctrl, channel, 0, 0xffffffff);
+ write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ }
+
+ /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
+ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ discover_edges_real(ctrl, channel, slotrank,
+ falling_edges[channel][slotrank]);
+ } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ discover_edges_real(ctrl, channel, slotrank,
+ rising_edges[channel][slotrank]);
+ } write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ falling_edges[channel][slotrank][lane];
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ rising_edges[channel][slotrank][lane];
+ } FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ 0);
+}} static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
+ int slotrank, int *edges)
+{
+ int edge;
+ u32 raw_statistics[MAX_EDGE_TIMING + 1];
+ int statistics[MAX_EDGE_TIMING + 1];
+ const int reg3000b24[] = { 0, 0xc, 0x2c };
+ int lane, i;
+ int lower[NUM_LANES];
+ int upper[NUM_LANES];
+
+ FOR_ALL_LANES {
+ lower[lane] = 0;
+ upper[lane] = MAX_EDGE_TIMING;
+ }
+
+ for (i = 0; i < 3; i++) {
+ /* FIXME: trace shows that vendor BIOS also tests with other patterns.
+ I'm not sure whether it's really needed.
+ */
+ write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel,
+ reg3000b24[i] << 24);
+ printk(BIOS_SPEW, "patterned\n");
+ printk(BIOS_SPEW, "[%x] = 0x%08x\n(%d, %d)\n",
+ 0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel,
+ slotrank);
+ for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) {
+ FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].
+ rising = edge;
+ ctrl->timings[channel][slotrank].lanes[lane].
+ falling = edge;
+ }
+ program_timings(ctrl, channel);
+
+ FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4340 +
+ 0x400 * channel + 4 * lane, 0);
+ read32(DEFAULT_MCHBAR + 0x400 * channel +
+ 4 * lane + 0x4140);
+ }
+ wait_428c(channel);
+
+ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ 0x4 | (ctrl->tRCD << 16)
+ | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) <<
+ 10));
+ write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel,
+ 0x240);
+
+ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ 0x1f201);
+ write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) <<
+ 16));
+ write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel,
+ 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ 0x4005020 | (max(ctrl->tRTP, 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel,
+ 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ 0xc01 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ 0xc0001);
+ wait_428c(channel);
+ FOR_ALL_LANES {
+ read32(DEFAULT_MCHBAR + 0x4340 +
+ 0x400 * channel + lane * 4);
+ }
+
+ raw_statistics[edge] =
+ MCHBAR32(0x436c + 0x400 * channel);
+ }
+ FOR_ALL_LANES {
+ struct run rn;
+ for (edge = 0; edge <= MAX_EDGE_TIMING; edge++)
+ statistics[edge] =
+ ! !(raw_statistics[edge] & (1 << lane));
+ rn = get_longest_zero_run(statistics,
+ MAX_EDGE_TIMING + 1);
+ printk(BIOS_SPEW,
+ "edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n",
+ channel, slotrank, i, rn.start, rn.middle,
+ rn.end, rn.start + ctrl->edge_offset[i],
+ rn.end - ctrl->edge_offset[i]);
+ lower[lane] =
+ max(rn.start + ctrl->edge_offset[i], lower[lane]);
+ upper[lane] =
+ min(rn.end - ctrl->edge_offset[i], upper[lane]);
+ edges[lane] = (lower[lane] + upper[lane]) / 2;
+
+ }
+ }
+
+ write32(DEFAULT_MCHBAR + 0x3000, 0);
+ printk(BIOS_SPEW, "CPA\n");
+}
+
+static void discover_edges_write(ramctr_timing * ctrl)
+{
+ int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int channel, slotrank, lane;
+
+ FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern5(ctrl, channel);
+ write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ }
+
+ /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
+ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ discover_edges_write_real(ctrl, channel, slotrank,
+ falling_edges[channel][slotrank]);
+ } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ discover_edges_write_real(ctrl, channel, slotrank,
+ rising_edges[channel][slotrank]);
+ } write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ ctrl->timings[channel][slotrank].lanes[lane].falling =
+ falling_edges[channel][slotrank][lane];
+ ctrl->timings[channel][slotrank].lanes[lane].rising =
+ rising_edges[channel][slotrank][lane];
+ } FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ 0);
+}} static void discover_timC_write(ramctr_timing * ctrl)
+{
+ const u8 rege3c_b24[3] = { 0, 0xf, 0x2f };
+ int i;
+
+ int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ int channel, slotrank, lane;
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ lower[channel][slotrank][lane] = 0;
+ upper[channel][slotrank][lane] = MAX_TIMC;
+ } write32(DEFAULT_MCHBAR + 0x4ea8, 1);
+
+ for (i = 0; i < 3; i++)
+ FOR_ALL_POPULATED_CHANNELS {
+ write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100),
+ (rege3c_b24[i] << 24)
+ | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))
+ & ~0x3f000000));
+ udelay(2);
+ FOR_ALL_POPULATED_RANKS {
+ int timC;
+ u32 raw_statistics[MAX_TIMC + 1];
+ int statistics[MAX_TIMC + 1];
+
+ /* FIXME: trace shows that vendor BIOS also tests with other patterns.
+ I'm not sure whether it's really needed.
+ */
+ fill_pattern5(ctrl, channel);
+ for (timC = 0; timC < MAX_TIMC + 1; timC++) {
+ FOR_ALL_LANES ctrl->timings[channel][slotrank].
+ lanes[lane].timC = timC;
+ program_timings(ctrl, channel);
+ wait_428c(channel);
+ write32(DEFAULT_MCHBAR + 0x4220 +
+ 0x400 * channel, 0x1f006);
+ write32(DEFAULT_MCHBAR + 0x4230 +
+ 0x400 * channel,
+ (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
+ << 10) | (ctrl->tRCD << 16) | 4);
+ write32(DEFAULT_MCHBAR + 0x4200 +
+ 0x400 * channel,
+ (slotrank << 24) | 0x60000);
+ write32(DEFAULT_MCHBAR + 0x4210 +
+ 0x400 * channel, 0x244);
+
+ write32(DEFAULT_MCHBAR + 0x4224 +
+ 0x400 * channel, 0x1f201);
+ write32(DEFAULT_MCHBAR + 0x4234 +
+ 0x400 * channel,
+ 0x80011e0 |
+ ((ctrl->tWTR + ctrl->CWL + 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4204 +
+ 0x400 * channel, (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4214 +
+ 0x400 * channel, 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x4228 +
+ 0x400 * channel, 0x1f105);
+ write32(DEFAULT_MCHBAR + 0x4238 +
+ 0x400 * channel,
+ 0x40011e0 | (max(ctrl->tRTP, 8) << 16));
+ write32(DEFAULT_MCHBAR + 0x4208 +
+ 0x400 * channel, (slotrank << 24));
+ write32(DEFAULT_MCHBAR + 0x4218 +
+ 0x400 * channel, 0x242);
+
+ write32(DEFAULT_MCHBAR + 0x422c +
+ 0x400 * channel, 0x1f002);
+ write32(DEFAULT_MCHBAR + 0x423c +
+ 0x400 * channel,
+ 0x1001 | (ctrl->tRP << 16));
+ write32(DEFAULT_MCHBAR + 0x420c +
+ 0x400 * channel,
+ (slotrank << 24) | 0x60400);
+ write32(DEFAULT_MCHBAR + 0x421c +
+ 0x400 * channel, 0);
+
+ write32(DEFAULT_MCHBAR + 0x4284 +
+ 0x400 * channel, 0xc0001);
+ wait_428c(channel);
+ raw_statistics[timC] =
+ MCHBAR32(0x436c + 0x400 * channel);
+ printk(BIOS_SPEW, "Cstat %02x %02x\n", timC,
+ raw_statistics[timC]);
+ }
+ FOR_ALL_LANES {
+ struct run rn;
+ for (timC = 0; timC <= MAX_TIMC; timC++)
+ statistics[timC] =
+ ! !(raw_statistics[timC] &
+ (1 << lane));
+ rn = get_longest_zero_run(statistics,
+ MAX_TIMC + 1);
+ if (rn.all)
+ die("timC write discovery failed");
+ printk(BIOS_SPEW,
+ "timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n",
+ channel, slotrank, i, rn.start,
+ rn.middle, rn.end,
+ rn.start + ctrl->timC_offset[i],
+ rn.end - ctrl->timC_offset[i]);
+ lower[channel][slotrank][lane] =
+ max(rn.start + ctrl->timC_offset[i],
+ lower[channel][slotrank][lane]);
+ upper[channel][slotrank][lane] =
+ min(rn.end - ctrl->timC_offset[i],
+ upper[channel][slotrank][lane]);
+
+ }
+ }
+ }
+
+ write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,
+ 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &
+ ~0x3f000000));
+ udelay(2);
+
+ write32(DEFAULT_MCHBAR + 0x4ea8, 0);
+
+ printk(BIOS_SPEW, "CPB\n");
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
+ printk(BIOS_SPEW, "timC [%d, %d, %d] = 0x%x\n", channel,
+ slotrank, lane,
+ (lower[channel][slotrank][lane] +
+ upper[channel][slotrank][lane]) / 2);
+ ctrl->timings[channel][slotrank].lanes[lane].timC =
+ (lower[channel][slotrank][lane] +
+ upper[channel][slotrank][lane]) / 2;
+ }
+ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+}
+
+static void normalize_training(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+ int mat = 0;
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ int delta;
+ FOR_ALL_LANES mat =
+ max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat);
+ delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028;
+ ctrl->timings[channel][slotrank].val_4024 += delta;
+ ctrl->timings[channel][slotrank].val_4028 += delta;
+ } FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel);
+}
+
+static void write_controller_mr(ramctr_timing * ctrl)
+{
+ int channel, slotrank;
+
+ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
+ write32(DEFAULT_MCHBAR | 0x0004 | (channel << 8) |
+ lane_registers[slotrank], make_mr0(ctrl, slotrank));
+ write32(DEFAULT_MCHBAR | 0x0008 | (channel << 8) |
+ lane_registers[slotrank], make_mr1(ctrl, slotrank));
+ }
+}
+
+static void channel_test(ramctr_timing * ctrl)
+{
+ int channel, slotrank, lane;
+
+ FOR_ALL_POPULATED_CHANNELS
+ if (read32(DEFAULT_MCHBAR | 0x42a0 | (channel << 10)) & 0xa000)
+ die("Mini channel test failed (1)\n");
+ FOR_ALL_POPULATED_CHANNELS {
+ fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
+
+ write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ }
+
+ for (slotrank = 0; slotrank < 4; slotrank++)
+ FOR_ALL_CHANNELS
+ if (ctrl->rankmap[channel] & (1 << slotrank)) {
+ FOR_ALL_LANES {
+ write32(DEFAULT_MCHBAR | (0x4f40 + 4 * lane), 0);
+ write32(DEFAULT_MCHBAR | (0x4d40 + 4 * lane), 0);
+ }
+ wait_428c(channel);
+ write32(DEFAULT_MCHBAR | 0x4220 | (channel << 10), 0x0001f006);
+ write32(DEFAULT_MCHBAR | 0x4230 | (channel << 10), 0x0028a004);
+ write32(DEFAULT_MCHBAR | 0x4200 | (channel << 10),
+ 0x00060000 | (slotrank << 24));
+ write32(DEFAULT_MCHBAR | 0x4210 | (channel << 10), 0x00000244);
+ write32(DEFAULT_MCHBAR | 0x4224 | (channel << 10), 0x0001f201);
+ write32(DEFAULT_MCHBAR | 0x4234 | (channel << 10), 0x08281064);
+ write32(DEFAULT_MCHBAR | 0x4204 | (channel << 10),
+ 0x00000000 | (slotrank << 24));
+ write32(DEFAULT_MCHBAR | 0x4214 | (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR | 0x4228 | (channel << 10), 0x0001f105);
+ write32(DEFAULT_MCHBAR | 0x4238 | (channel << 10), 0x04281064);
+ write32(DEFAULT_MCHBAR | 0x4208 | (channel << 10),
+ 0x00000000 | (slotrank << 24));
+ write32(DEFAULT_MCHBAR | 0x4218 | (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR | 0x422c | (channel << 10), 0x0001f002);
+ write32(DEFAULT_MCHBAR | 0x423c | (channel << 10), 0x00280c01);
+ write32(DEFAULT_MCHBAR | 0x420c | (channel << 10),
+ 0x00060400 | (slotrank << 24));
+ write32(DEFAULT_MCHBAR | 0x421c | (channel << 10), 0x00000240);
+ write32(DEFAULT_MCHBAR | 0x4284 | (channel << 10), 0x000c0001);
+ wait_428c(channel);
+ FOR_ALL_LANES
+ if (read32(DEFAULT_MCHBAR | 0x4340 | (channel << 10)))
+ die("Mini channel test failed (2)\n");
+ }
+}
+
+static void set_scrambling_seed(ramctr_timing * ctrl)
+{
+ int channel;
+
+ /* FIXME: we hardcode seeds. Do we need to use some PRNG for them?
+ I don't think so. */
+ static u32 seeds[NUM_CHANNELS][3] = {
+ {0x00009a36, 0xbafcfdcf, 0x46d1ab68},
+ {0x00028bfa, 0x53fe4b49, 0x19ed5483}
+ };
+ FOR_ALL_POPULATED_CHANNELS {
+ MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000;
+ write32(DEFAULT_MCHBAR | 0x4034, seeds[channel][0]);
+ write32(DEFAULT_MCHBAR | 0x403c, seeds[channel][1]);
+ write32(DEFAULT_MCHBAR | 0x4038, seeds[channel][2]);
+ }
+}
+
+static void set_4f8c(void)
+{
+ struct cpuid_result cpures;
+ u32 cpu;
+
+ cpures = cpuid(0);
+ cpu = (cpures.eax);
+ if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
+ MCHBAR32(0x4f8c) = 0x141D1519;
+ } else {
+ MCHBAR32(0x4f8c) = 0x551D1519;
+ }
+}
+
+static void prepare_training(ramctr_timing * ctrl)
+{
+ int channel;
+
+ FOR_ALL_POPULATED_CHANNELS {
+ // Always drive command bus
+ MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000;
+ }
+
+ udelay(1);
+
+ FOR_ALL_POPULATED_CHANNELS wait_428c(channel);
+}
+
+static void hardcode1(ramctr_timing * ctrl)
+{
+ int channel;
+ FOR_ALL_POPULATED_CHANNELS {
+ read32(DEFAULT_MCHBAR | 0x400c | (channel << 10)); // !!! = 0x000258b4
+ write32(DEFAULT_MCHBAR | 0x400c | (channel << 10), 0x000058b4); // FIXME: hardcoded
+ write32(DEFAULT_MCHBAR | 0x4008 | (channel << 10), 0x0a042220); // FIXME: hardcoded
+ }
+}
+
+static void set_42a0(ramctr_timing * ctrl)
+{
+ int channel;
+ FOR_ALL_POPULATED_CHANNELS {
+ write32(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel),
+ 0x00001000 | ctrl->rankmap[channel]);
+ MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
+ }
+}
+
+void init_dram_ddr3(spd_raw_data * spds, int mobile)
+{
+ int me_uma_size;
+
+ /* FIXME: hardcoded. */
+ write32(DEFAULT_MCHBAR | 0x5f00, 0x0000270f);
+
+ report_platform_info();
+
+ /* Wait for ME to be ready */
+ intel_early_me_init();
+ me_uma_size = intel_early_me_uma_size();
+
+ printk(BIOS_DEBUG, "Starting native Platform init\n");
+
+ pch_init();
+
+ u32 reg_5d10;
+
+ wait_txt_clear();
+
+ wrmsr(0x000002e6, (msr_t) {
+ .lo = 0,.hi = 0});
+
+ reg_5d10 = read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
+ && reg_5d10) {
+ /* Need reset. */
+ outb(0x6, 0xcf9);
+
+ while (1) ;
+ }
+
+ ramctr_timing ctrl;
+
+ dimm_info info;
+
+ ctrl.mobile = mobile;
+
+ /* Get DDR3 SPD data */
+ dram_find_spds_ddr3(spds, &info, &ctrl);
+
+ /* Find fastest common supported parameters */
+ dram_find_common_params(&info, &ctrl);
+
+ /* Calculate timings */
+ dram_timing(&ctrl);
+
+ /* Set MCU frequency */
+ dram_freq(&ctrl);
+
+ /* Set version register */
+ MCHBAR32(0x5034) = 0xC04EB002;
+
+ /* Enable crossover */
+ dram_xover(&ctrl);
+
+ /* Set timing and refresh registers */
+ dram_timing_regs(&ctrl);
+
+ /* Power mode preset */
+ MCHBAR32(0x4e80) = 0x5500;
+
+ /* Set scheduler parameters */
+ MCHBAR32(0x4c20) = 0x10100005;
+
+ /* Set cpu specific register */
+ set_4f8c();
+
+ /* Clear IO reset bit */
+ MCHBAR32(0x5030) &= ~0x20;
+
+ /* FIXME: Fix dimm map - Set MAD-DIMM registers */
+ dram_dimm_mapping(&info, &ctrl);
+ printk(BIOS_DEBUG, "Done dimm mapping\n");
+
+ /* Zone config */
+ dram_zones(&info, &ctrl, 1);
+
+ /* Set memory map */
+ dram_memorymap(&info, me_uma_size);
+ printk(BIOS_DEBUG, "Done memory map\n");
+
+ /* Set IO registers */
+ dram_ioregs(&ctrl);
+ printk(BIOS_DEBUG, "Done io registers\n");
+
+ udelay(1);
+
+ /* Do jedec ddr3 reset sequence */
+ dram_jedecreset(&ctrl);
+ printk(BIOS_DEBUG, "Done jedec reset\n");
+
+ /* MRS commands */
+ dram_mrscommands(&ctrl);
+ printk(BIOS_DEBUG, "Done MRS commands\n");
+ dram_mrscommands(&ctrl);
+
+ /* Prepare for memory training */
+ prepare_training(&ctrl);
+
+ read_training(&ctrl);
+ write_training(&ctrl);
+
+ printk(BIOS_SPEW, "CP5a\n");
+
+ discover_edges(&ctrl);
+
+ printk(BIOS_SPEW, "CP5b\n");
+
+ command_training(&ctrl);
+
+ printk(BIOS_SPEW, "CP5c\n");
+
+ discover_edges_write(&ctrl);
+
+ discover_timC_write(&ctrl);
+
+ normalize_training(&ctrl);
+
+ hardcode1(&ctrl);
+
+ write_controller_mr(&ctrl);
+
+ channel_test(&ctrl);
+
+ write32(DEFAULT_MCHBAR | 0x5024, 0x00a030ce); // FIXME: hardcoded
+
+ set_scrambling_seed(&ctrl);
+
+ set_42a0(&ctrl);
+
+ write32(DEFAULT_MCHBAR | 0x4cd4, 0x00000046); // FIXME: hardcoded
+
+ write32(DEFAULT_MCHBAR | 0x400c, (read32(DEFAULT_MCHBAR | 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR | 0x440c, (read32(DEFAULT_MCHBAR | 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR | 0x4cb0, 0x00000740); // FIXME: hardcoded
+ write32(DEFAULT_MCHBAR | 0x4380, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR | 0x4780, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR | 0x4f88, 0x5f7003ff); // OK
+ write32(DEFAULT_MCHBAR | 0x5064, 0x00073193); // FIXME: hardcoded
+ write32(DEFAULT_MCHBAR | 0x4384, 0x009b6ea1); // FIXME: hardcoded
+ write32(DEFAULT_MCHBAR | 0x4784, 0x009b6ea1); // FIXME: hardcoded
+ write32(DEFAULT_MCHBAR | 0x5880, 0xca9171e5); // FIXME: hardcoded
+ read32(DEFAULT_MCHBAR | 0x5888); // !!! = 0x00e4d5d0
+ write32(DEFAULT_MCHBAR | 0x5888, 0x00e4d5d0); // FIXME: hardcoded
+ read32(DEFAULT_MCHBAR | 0x58a8); // !!! = 0x00000000
+ write32(DEFAULT_MCHBAR | 0x58a8, 0x00000000); // FIXME: hardcoded
+ read32(DEFAULT_MCHBAR | 0x4294); // !!! = 0x000098ff
+ write32(DEFAULT_MCHBAR | 0x4294, 0x000198ff); // FIXME: hardcoded
+ read32(DEFAULT_MCHBAR | 0x4694); // !!! = 0x000098ff
+ write32(DEFAULT_MCHBAR | 0x4694, 0x000198ff); // FIXME: hardcoded
+
+ MCHBAR32(0x5030) |= 1; // OK
+ MCHBAR32(0x5030) |= 0x80; // OK
+ MCHBAR32(0x5f18) = 0xfa; // OK
+ read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ write32(DEFAULT_MCHBAR | 0x5d10, 0x2010040c); // FIXME: hardcoded
+
+ /* Zone config */
+ dram_zones(&info, &ctrl, 0);
+
+#if CONFIG_USBDEBUG_IN_ROMSTAGE
+ /* mrc.bin reconfigures USB, so reinit it to have debug */
+ usbdebug_init();
+#endif
+
+ intel_early_me_status();
+ intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+ intel_early_me_status();
- post_system_agent_init(pei_data);
+ post_system_agent_init();
report_memory_config();
}
diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index c3b1c2a..7e0b10e 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -20,17 +20,11 @@
#ifndef RAMINIT_H
#define RAMINIT_H
-#include "pei_data.h"
+#include <device/dram/ddr3.h>
-struct sys_info {
- u8 boot_path;
-#define BOOT_PATH_NORMAL 0
-#define BOOT_PATH_RESET 1
-#define BOOT_PATH_RESUME 2
-} __attribute__ ((packed));
-
-void sdram_initialize(struct pei_data *pei_data);
-void save_mrc_data(struct pei_data *pei_data);
-int fixup_sandybridge_errata(void);
+/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */
+void init_dram_ddr3(spd_raw_data *spds, int mobile);
+void pch_init(void);
+void read_spd(spd_raw_data *spd, u8 addr);
#endif /* RAMINIT_H */
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 670e1ce..ab54ffd 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -126,64 +126,136 @@ static inline void set_global_reset(int enable)
int intel_early_me_init_done(u8 status)
{
- u8 reset;
- int count;
+ u8 reset, errorcode, opmode;
+ u16 reg16;
u32 mebase_l, mebase_h;
- struct me_hfs hfs;
+ u32 millisec;
+ u32 hfs, me_fws2;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
+ u32 meDID;
+
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
+
+ opmode = (hfs & 0xf0) >> 4;
+ errorcode = hfs & 0xf;
+
+ if (opmode != ME_HFS_MODE_NORMAL) {
+ printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
+ //return 0;
+ }
+ if (errorcode) {
+ printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
+ //return 0;
+ }
+
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
+ printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
+ printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
+ printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
+ printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
+ printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
+ printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
+ printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
+ printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
+ printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
+ printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
+ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
+ printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
+
+ // Poll cpu replaced for 50ms
+ millisec = 0;
+ while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
+ udelay(1000);
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ millisec++;
+ }
+ if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
+ printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
+ } else if ((me_fws2 & 0x100) == 0x100) {
+ if ((me_fws2 & 0x80) == 0x80) {
+ printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
+ reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
+ pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
+ set_global_reset(0);
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
+ printk(BIOS_NOTICE, "Full training required\n");
+ }
+ }
+
+ printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
- /* Send message to ME */
- printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
- "UMA base: 0x%04x\n", status, did.uma_base);
+ meDID = did.uma_base | (1 << 28);// | (1 << 23);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
- pci_write_dword_ptr(&did, PCI_ME_H_GS);
+ udelay(1100);
/* Must wait for ME acknowledgement */
- for (count = ME_RETRY; count > 0; --count) {
- pci_read_dword_ptr(&hfs, PCI_ME_HFS);
- if (hfs.bios_msg_ack)
- break;
- udelay(ME_DELAY);
- }
- if (!count) {
- printk(BIOS_ERR, "ERROR: ME failed to respond\n");
- return -1;
+ millisec = 0;
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
+ while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
+ udelay(1000);
+ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
+ millisec++;
}
+ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
+ printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
+ printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
+ printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
+ printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
+ printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
+ printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
+ printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
+ printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
+ printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
+ printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
+ printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
+ printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
+ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
+ printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
+
+
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
- me_ack_values[hfs.ack_data]);
-
- /* Check status after acknowledgement */
- intel_early_me_status();
+ me_ack_values[(hfs & 0xe) >> 1]);
- reset = 0;
- switch (hfs.ack_data) {
+ reset = inb(0xcf9);
+ reset &= 0xf1;
+ switch ((hfs & 0xe) >> 1) {
+ case ME_HFS_ACK_NO_DID:
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
- reset = 0x06;
+ reset |= 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
- reset = 0x0e;
+ reset |= 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
- reset = 0x0e;
+ reset |= 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
1
0
Patch set updated for coreboot: b110eb0 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg) i945 subsystem added to Kconfig mainboard.c fixed The console is running To fix: RAM init ... and more ...
by HAOUAS Elyes 29 May '14
by HAOUAS Elyes 29 May '14
29 May '14
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5881
-gerrit
commit b110eb08cec24801f2e75b2101ee419a261e6cef
Author: Elyes <ehaouas(a)noos.fr>
Date: Thu May 29 12:04:25 2014 +0200
Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
i945 subsystem added to Kconfig
mainboard.c fixed
The console is running
To fix: RAM init ... and more ...
Change-Id: I7b00251e332ac005918cf7c3ed4bef8878bd145b
Signed-off-by: Elyes <ehaouas(a)noos.fr>
---
src/mainboard/nec/945g-m4/Kconfig | 43 +++
src/mainboard/nec/945g-m4/Makefile.inc | 20 ++
src/mainboard/nec/945g-m4/acpi/ec.asl | 49 ++++
src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 86 ++++++
src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 +++++++
src/mainboard/nec/945g-m4/acpi/platform.asl | 91 +++++++
src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++
src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++
src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++
src/mainboard/nec/945g-m4/acpi_tables.c | 230 ++++++++++++++++
src/mainboard/nec/945g-m4/board_info.txt | 3 +
src/mainboard/nec/945g-m4/cmos.layout | 194 ++++++++++++++
src/mainboard/nec/945g-m4/devicetree.cb | 149 +++++++++++
src/mainboard/nec/945g-m4/dsdt.asl | 43 +++
src/mainboard/nec/945g-m4/fadt.c | 155 +++++++++++
src/mainboard/nec/945g-m4/irq_tables.c | 61 +++++
src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++
src/mainboard/nec/945g-m4/mptable.c | 89 +++++++
src/mainboard/nec/945g-m4/romstage.c | 324 +++++++++++++++++++++++
src/mainboard/nec/945g-m4/smihandler.c | 49 ++++
src/mainboard/nec/945g-m4/superio_hwm.c | 161 +++++++++++
src/mainboard/nec/945g-m4/superio_hwm.h | 25 ++
src/mainboard/nec/Kconfig | 4 +
23 files changed, 2202 insertions(+)
diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig
new file mode 100644
index 0000000..cf8988f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_NEC_945G_M4
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select CHECK_SLFRCS_ON_RESUME
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627EHG
+ select EARLY_CBMEM_INIT
+ select HAVE_ACPI_TABLES
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+config MAINBOARD_DIR
+ string
+ default nec/945g-m4
+#config DCACHE_RAM_BASE
+# hex
+# default 0xfeffc000
+#config DCACHE_RAM_SIZE
+# hex
+# default 0x9900
+config MAINBOARD_PART_NUMBER
+ string
+ default "945G-M4"
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+config IRQ_SLOT_COUNT
+ int
+ default 18
+config MAX_CPUS
+ int
+ default 4
+#config VGA_BIOS_FILE
+# string
+# default "amipci_01.20"
+endif # BOARD_NEC_945G_M4
diff --git a/src/mainboard/nec/945g-m4/Makefile.inc b/src/mainboard/nec/945g-m4/Makefile.inc
new file mode 100644
index 0000000..30dfea9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+romstage-y += ../../../northbridge/intel/i945/raminit.c
+ramstage-y += superio_hwm.c
diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl
new file mode 100644
index 0000000..e6c30a0
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..bd3379b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ Package() { 0x0001ffff, 1, 0, 17 },
+ Package() { 0x0001ffff, 2, 0, 18 },
+ Package() { 0x0001ffff, 3, 0, 19 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 17 },
+ Package() { 0x001effff, 1, 0, 20 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 18 },
+ Package() { 0x001fffff, 1, 0, 19},
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..c108d3f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 20},
+ Package() { 0x0001ffff, 1, 0, 21},
+ Package() { 0x0001ffff, 2, 0, 22},
+ Package() { 0x0001ffff, 3, 0, 23},
+
+ Package() { 0x0002ffff, 0, 0, 21},
+ Package() { 0x0002ffff, 1, 0, 22},
+ Package() { 0x0002ffff, 2, 0, 23},
+ Package() { 0x0002ffff, 3, 0, 20},
+
+ Package() { 0x0003ffff, 0, 0, 22},
+ Package() { 0x0003ffff, 1, 0, 23},
+ Package() { 0x0003ffff, 2, 0, 20},
+ Package() { 0x0003ffff, 3, 0, 21},
+
+ Package() { 0x0004ffff, 0, 0, 23},
+ Package() { 0x0004ffff, 1, 0, 20},
+ Package() { 0x0004ffff, 2, 0, 21},
+ Package() { 0x0004ffff, 3, 0, 22},
+
+ Package() { 0x0005ffff, 0, 0, 19},
+ Package() { 0x0005ffff, 1, 0, 18},
+ Package() { 0x0005ffff, 2, 0, 17},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ Package() { 0x0006ffff, 0, 0, 18},
+ Package() { 0x0006ffff, 1, 0, 17},
+ Package() { 0x0006ffff, 2, 0, 16},
+ Package() { 0x0006ffff, 3, 0, 19},
+
+ Package() { 0x0009ffff, 0, 0, 21},
+ Package() { 0x0009ffff, 1, 0, 22},
+ Package() { 0x0009ffff, 2, 0, 23},
+ Package() { 0x0009ffff, 3, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl
new file mode 100644
index 0000000..2e4223c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/platform.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl
new file mode 100644
index 0000000..997a33a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/superio.asl
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+ Name (_HID, EISAID("PNP0A05"))
+ Name (_UID, 1)
+
+ Device (UAR1)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+ Name(_DDN, "COM1")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+
+ Device (UAR2)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 2)
+ Name(_DDN, "COM2")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl
new file mode 100644
index 0000000..d1774d4
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x64)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (0xf5c) // Value for Rocky
+ }
+
+ // Method (_AC1, 0, Serialized)
+ // {
+ // Return (0xf5c)
+ // }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (Add (0x0aac, 0x50)) // FIXME
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (0xaaf) // FIXME
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ Return (0xaac) // FIXME
+ }
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {\_PR.CPU1, \_PR.CPU2})
+ }
+ Return (Package() {\_PR.CPU1})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c
new file mode 100644
index 0000000..e6a517e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi_tables.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ current += 0x100;
+ ALIGN_CURRENT;
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt
new file mode 100644
index 0000000..ed23062
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/board_info.txt
@@ -0,0 +1,3 @@
+Category: µATX 24.4 cm x 24.4 cm Form Factor
+Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d…
+Flashrom support: y
diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout
new file mode 100644
index 0000000..b3e8c4e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cmos.layout
@@ -0,0 +1,194 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 40 r 0 unused
+
+# coreboot config options: mainboard specific options
+948 2 e 8 cpufan_cruise_control
+950 2 e 8 sysfan_cruise_control
+952 4 e 9 cpufan_speed
+#956 4 e 10 cpufan_temperature
+960 4 e 9 sysfan_speed
+#964 4 e 10 sysfan_temperature
+
+968 1 e 2 ethernet1
+969 1 e 2 ethernet2
+970 1 e 2 ethernet3
+
+#971 13 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# ram initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# Fan Cruise Control
+8 0 Disabled
+8 1 Speed
+#8 2 Thermal
+# Fan Speed (Rotations per Minute)
+9 0 5625
+9 1 5192
+9 2 4753
+9 3 4326
+9 4 3924
+9 5 3552
+9 6 3214
+9 7 2909
+9 8 2636
+9 9 2393
+9 10 2177
+9 11 1985
+9 12 1814
+9 13 1662
+9 14 1527
+9 15 1406
+#
+# Temperature (�C/�F)
+#10 0 30/86
+#10 1 33/91
+#10 2 36/96
+#10 3 39/102
+#10 4 42/107
+#10 5 45/113
+#10 6 48/118
+#10 7 51/123
+#10 8 54/129
+#10 9 57/134
+#10 10 60/140
+#10 11 63/145
+#10 12 66/150
+#10 13 69/156
+#10 14 72/161
+#10 15 75/167
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb
new file mode 100644
index 0000000..2f4020e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/devicetree.cb
@@ -0,0 +1,149 @@
+#lspci
+#-[0000:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+# +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60] <- PCIe card. integrated vga is an intel, desabled by vendor bios.
+# | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+# +-1c.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+# +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+# +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+# +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+# +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+# +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+# +-1e.0-[03]----02.0 Philips Semiconductors SAA7146 [1131:7146]
+# +-1e.2 Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+# +-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+# +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+# +-1f.2 Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+# \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+#end lspci
+chip northbridge/intel/i945
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge +-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+ device pci 01.0 on end # i945 PCIe root port
+ #+-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60]
+ # \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+ #device pci 02.0 on end # vga controller +-02.0 Intel Corporation 82945G/GZ Integrated Graphics Controller [8086:2772]
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8a" # OS will change it:"0x0a" found via dmesg (linux on vendor bios)
+ register "pirqb_routing" = "0x85" # OS will change it:"0x05" found via dmesg
+ register "pirqc_routing" = "0x8b" # OS will change it:"0x0b"found via dmesg
+ register "pirqd_routing" = "0x8b" # OS will change it:"0x0b" found via dmesg
+ register "pirqe_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqf_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqg_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqh_routing" = "0x8a" # OS will change it: "0x0a"found via dmsg
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x1"
+ device pci 1c.0 on end # Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+ device pci 1d.0 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+ device pci 1d.1 on end # Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+ device pci 1d.2 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+ device pci 1d.3 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+ device pci 1d.7 on end #Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+ device pci 1e.0 on end #-[02]----02.0 Philips Semiconductors SAA7146 [1131:7146]
+ device pci 1e.2 on end # Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+ device pci 1f.0 on # Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+
+ chip superio/winbond/w83627ehg # Super I/O
+ #Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e
+ #Register dump:
+ #idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+ #val 88 63 ff 00 44 00 00 ff 50 05 00 00 83 20 00 ff
+ #def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00
+ device pnp 2e.0 on #LDN 0x00 (Floppy)
+ io 0x60 = 0x3f0 #idx 30 60 61 70 74 f0 f1 f2 f4 f5
+ irq 0x70 = 6 #val 01 03 f0 06 02 8e 00 ff 00 00
+ drq 0x74 = 2 #def 01 03 f0 06 02 8e 00 ff 00 00
+ end
+
+ device pnp 2e.1 on #LDN 0x01 (Parallel port)
+ io 0x60 = 0x378 #idx 30 60 61 70 74 f0
+ irq 0x70 = 7 #val 01 03 78 07 04 3c
+ drq 0x74 = 3 #def 01 03 78 07 04 3f
+ end
+ device pnp 2e.2 on #LDN 0x02 (COM1)
+ io 0x60 = 0x3f8 #idx 30 60 61 70 f0
+ irq 0x70 = 4 #val 01 03 f8 04 00
+ #def 01 03 f8 04 00
+ end
+
+
+ device pnp 2e.3 off #LDN 0x03 (COM2)
+ io 0x60 = 0x2f8 #idx 30 60 61 70 f0 f1
+ irq 0x70 = 3 #val 01 02 f8 03 00 04
+ #def 01 02 f8 03 00 00
+ end
+
+ device pnp 2e.5 on #LDN 0x05 (Keyboard)
+ #idx 30 60 61 62 63 70 72 f0
+ #val 01 00 60 00 64 01 0c 82
+ #def 01 00 60 00 64 01 0c 83
+ end
+ device pnp 2e.106 on #LDN 0x06 (Serial flash interface)
+ io 0x60 = 0x100 #idx 30 62 63
+ #val 00 ff ff
+ #def 00 00 00
+ end
+ #----
+ #LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
+ #idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7
+ #val 01 00 00 00 00 00 5f 5f 00 00 ff ff ff 00
+ #def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00
+ device pnp 2e.007 on # GPIO 1
+ end
+ device pnp 2e.107 off # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.207 on # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 0xa
+ end
+ device pnp 2e.307 on # GPIO 6
+ end
+ device pnp 2e.8 off #LDN 0x08 (WDTO#, PLED)
+ #idx 30 f5 f6 f7
+ #val 00 ff 00 ff
+ #def 00 00 00 00
+ end
+ #----
+ #LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
+ #idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7
+ #val 0e df 00 20 ff ff ff 8c 8c 00 40 df 00 00 20
+ #def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00
+ device pnp 2e.009 on # GPIO 2
+ end
+ device pnp 2e.109 on # GPIO 3
+ end
+ device pnp 2e.209 on # GPIO 4
+ end
+ device pnp 2e.309 on # GPIO 5
+ end
+ device pnp 2e.a on #LDN 0x0a (ACPI)
+ #idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7
+ #val 01 00 01 00 ff 04 00 00 1c 10 09 7c 00 00 00 00
+ #def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00
+ end
+ device pnp 2e.b on #LDN 0x0b (Hardware monitor)
+ io 0x60 = 0x290 #idx 30 60 61 70 f0 f1
+ irq 0x70 = 0 #val 01 0a 10 00 c1 00
+ #def 00 00 00 00 c1 00
+ end
+ end
+ end
+ device pci 1f.1 on end # Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+ device pci 1f.2 on end # Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+ device pci 1f.3 on end # Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+ end
+ end
+end
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl
new file mode 100644
index 0000000..f30c12d
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ //#include "acpi/thermal.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c
new file mode 100644
index 0000000..b55f628
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/fadt.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x20;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+ fadt->pm2_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 85;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = 0x03;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c
new file mode 100644
index 0000000..5e2566b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO@TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 14, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xb, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+ {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0},
+ {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0},
+ {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0},
+ {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0},
+ {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0},
+ {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c
new file mode 100644
index 0000000..9d267cc
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mainboard.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include "superio_hwm.h"
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f35: /* Boot Display */
+ X86_AX = 0x005f; // Success
+ X86_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ X86_AX = 0x005f; // Success
+ X86_CL = 3; // Display ID
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+/* Audio Setup */
+
+extern u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ // Default VERB is fine on this mainboard.
+ cim_verb_data = NULL;
+ cim_verb_data_size = 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+ verb_setup();
+ hwm_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c
new file mode 100644
index 0000000..95a34da
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mptable.c
@@ -0,0 +1,89 @@
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#define INTA 0x00
+#define INTB 0x01
+#define INTC 0x02
+#define INTD 0x03
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ smp_write_processors(mc);
+ /* Bus: Bus ID Type */
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ my_smp_write_bus(mc, 2, "PCI ");
+ my_smp_write_bus(mc, 3, "PCI ");
+ my_smp_write_bus(mc, 4, "ISA ");
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000);
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13);
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+/* mptable_lintsrc(mc, isa_bus); */
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 1);
+ return (unsigned long)smp_write_config_table(v);
+}
+/*MP Config Extended Table Entries:
+--
+System Address Space
+ bus ID: 0 address type: I/O address
+ address base: 0x600000000000
+ address range: 0x148000000000
+Extended Table HOSED!
+*/
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c
new file mode 100644
index 0000000..f64a179
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+void setup_ich7_gpios(void)
+{ /*
+./inteltool -g
+CPU: ID 0xf65, Processor Type 0x0, Family 0xf, Model 0x6, Stepping 0x5
+Northbridge: 8086:2770 (945P) <-- in fact, it is a i945GC
+Southbridge: 8086:27b8 (ICH7)
+============= GPIOS =============
+GPIOBASE = 0x0480 (IO)
+gpiobase+0x0000: 0x1f9fffc3 (GPIO_USE_SEL)
+gpiobase+0x0004: 0xe0e8ffc3 (GP_IO_SEL)
+gpiobase+0x0008: 0x00000000 (RESERVED)
+gpiobase+0x000c: 0xebffffbf (GP_LVL)
+gpiobase+0x0010: 0x00000000 (RESERVED)
+gpiobase+0x0014: 0x00000000 (RESERVED)
+gpiobase+0x0018: 0x00000000 (GPO_BLINK)
+gpiobase+0x001c: 0x00000000 (RESERVED)
+gpiobase+0x0020: 0x00000000 (RESERVED)
+gpiobase+0x0024: 0x00000000 (RESERVED)
+gpiobase+0x0028: 0x00000000 (RESERVED)
+gpiobase+0x002c: 0x0000af03 (GPI_INV)
+gpiobase+0x0030: 0x000000ff (GPIO_USE_SEL2)
+gpiobase+0x0034: 0x000000f0 (GP_IO_SEL2)
+gpiobase+0x0038: 0x000000f7 (GP_LVL2)
+gpiobase+0x003c: 0x00000000 (RESERVED)
+*/
+ printk(BIOS_DEBUG, " GPIOS...");
+ /* General Registers */
+ outl(0x1f9fffc3, DEFAULT_GPIOBASE + GPIO_USE_SEL);
+ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + GP_IO_SEL);
+ outl(0xebffffbf, DEFAULT_GPIOBASE + GP_LVL);
+ /* Output Control Registers */
+ outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
+ /* Input Control Registers */
+ outl(0x0000af03, DEFAULT_GPIOBASE + GPI_INV);
+ outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL2);
+ outl(0x000000f0, DEFAULT_GPIOBASE + GP_IO_SEL2);
+ outl(0x000000f7, DEFAULT_GPIOBASE + GP_LVL2);
+}
+static void ich7_enable_lpc(void)
+{
+// see http://macbook.donderklumpen.de/coreboot/ section Stage 2: ROM stage
+/* lspci -nnvvvxxx -s 00:1f.0
+lspci -nnvvvxxx -s 00:1f.0
+00:1f.0 ISA bridge [0601]: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] (rev 01)
+ Subsystem: Packard Bell B.V. Device [1631:e015]
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Capabilities: [e0] Vendor Specific Information: Len=0c <?>
+ Kernel driver in use: lpc_ich
+ Kernel modules: intel_rng
+00: 86 80 b8 27 07 00 10 02 01 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 31 16 15 e0
+30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
+40: 01 08 00 00 80 00 00 00 81 04 00 00 10 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 8a 85 8b 8b d0 00 00 00 80 80 80 8a 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 10 00 0f 34 01 0a fc 00 01 47 fc 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 28 06 00 00 39 00 00 00 13 00 00 00 00 03 00 00
+b0: 00 00 f0 00 00 00 00 00 00 00 02 80 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 33 22 11 00 67 45 00 00 c0 80 00 00 00 00 00 00
+e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
+f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00*/
+ // Enable Serial IRQ
+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* datasheet page 363 default value 0x10 */
+ // LPC I/O decode range
+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* datasheet: default value 0x0000 */
+ // LPC Interface Enables
+ pci_write_config16(LPC_DEV, LPC_EN, 0x340f); /* datasheet: default value 0x0000 */
+// PIRQ [A-D] -> see devicetree.cb
+// pci_write_config8(LPC_DEV, 0x60, 0x8a);
+// pci_write_config8(LPC_DEV, 0x61, 0x85);
+// pci_write_config8(LPC_DEV, 0x62, 0x8b);
+// pci_write_config8(LPC_DEV, 0x63, 0x8b);
+// PIRQ [E-H]*/ > see devicetree.cb
+// pci_write_config8(LPC_DEV, 0x68, 0x80);
+// pci_write_config8(LPC_DEV, 0x69, 0x80);
+// pci_write_config8(LPC_DEV, 0x6a, 0x80);
+// pci_write_config8(LPC_DEV, 0x6b, 0x8a);
+/* GEN1_DEC. LPC interface generic decode Rang1 */
+ pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
+// pci_write_config16(LPC_DEV, 0x84, 0x0a01); /* datasheet page 364: conf32 - default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x86, 0x00fc);
+ /* GEN2_DEC. LPC interface generic decode Rang2 */
+ pci_write_config32(LPC_DEV, 0x88, 0x00fc4701);
+// pci_write_config16(LPC_DEV, 0x88, 0x4701); /* datasheet - conf32: default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x8a, 0x00fc);
+ /* GEN3_DEC. LPC interface generic decode Rang3 */
+// pci_write_config32(LPC_DEV, 0x8c,0x00000000);
+// pci_write_config16(LPC_DEV, 0x8c, 0x0000); /* datasheet - conf32: default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x8e, 0x0000);
+ /* GEN4_DEC. LPC interface generic decode Rang4 */
+// pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+// pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+}
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ /*./inteltool -r |grep -i 0x0014
+ 0x0014: 0x80000001 */
+// RCBA32(V0CTL) = 0x80000001; see i945/ ich7_setup_dmi_rcrb()
+ /* ./inteltool -r |grep -i 0x001C
+ 0x001c: 0x03128010 */
+// RCBA32(V1CAP) = 0x03128010; see i945/ ich7_setup_dmi_rcrb()
+ /* Device 1f interrupt pin register */
+ /*
+ ./inteltool -r |grep -i 0x3100
+ 0x3100: 0x00042210 */
+ RCBA32(D31IP) = 0x00042210;
+ /* Device 1d interrupt pin register */
+ /* ./inteltool -r |grep -i 0x310c
+ 0x310c: 0x00214321 */
+ RCBA32(D28IP) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(D27IP) = 0x00000001;
+ /* dev irq route register */
+ /*./inteltool -r |grep -i 0x3140
+ 0x3140: 0x32410132 */
+ RCBA16(D31IR) = 0x3241;
+ RCBA16(D30IR) = 0x0132;
+//
+ /* ./inteltool -r |grep -i 0x3144
+ 0x3144: 0x32100237*/
+ RCBA16(D29IR) = 0x3210;
+ RCBA16(D28IR) = 0x0237;
+ /*./inteltool -r |grep -i 0x3148
+ 0x3148: 0x00003210 */
+ RCBA16(D27IR) = 0x0000;
+//
+ /* Enable IOAPIC */
+ /*./inteltool -r |grep -i 0x31f
+ 0x31fc: 0x03000000 */
+ //RCBA8(0x31ff) = 0x00;
+ RCBA32(0x31fc) |= 3 << 24;
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
+ /* Enable PCIe Root Port Clock Gate */
+ /* ./inteltool -r |grep -i 0x341c
+ 0x341c: 0x00000001 */
+ RCBA32(CG) = 0x00000001;
+}
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ /*./inteltool -r |grep -i 0x0088
+ 0x0088: 0x0011d000 */
+ RCBA32(0x0088) = 0x0011d000;
+ /*./inteltool -r |grep -i 0x01fc
+ 0x01fc: 0x0000060f */
+ RCBA16(0x01fc) = 0x060f;
+ /*./inteltool -r |grep -i 0x01f4
+ 0x01f4: 0x86000040 */
+ RCBA32(0x01f4) = 0x86000040;
+ /* ./inteltool -r |grep -i 0x0214
+ 0x0214: 0x10030509*/
+ RCBA32(0x0214) = 0x10030549;
+ /*./inteltool -r |grep -i 0x0218
+ 0x0218: 0x00020504 */
+ RCBA32(0x0218) = 0x00020504;
+ /*./inteltool -r |grep -i 0x0220
+ 0x0220: 0x000000c5 */
+ RCBA8(0x0220) = 0xc5; /*c5;*/
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(FD) |= (1 << 0);
+ /*./inteltool -r |grep -i 0x0200
+ 0x0130: 0x02000002
+ 0x0200: 0x01102008 */
+// RCBA16(0x0200) = 0x0110;
+ RCBA32(0x0200) = 0x01102008;
+ /*./inteltool -r |grep -i 0x2028
+ 0x2028: 0x0038f221
+ ./inteltool -r |grep -i 0x2024
+ 0x2024: 0x0d303000*/
+ RCBA8(0x2027) = 0x00;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+void main(unsigned long bist)
+{
+ u32 reg32;
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ if (bist == 0)
+ enable_lapic();
+ ich7_enable_lpc();
+ /* Set up the console */
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ outb(0x6, 0xcf9);
+ while (1) asm("hlt");
+ }
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+ }
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ sdram_initialize(boot_mode, NULL);
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+ /* Chipset Errata! */
+ fixup_i945_errata();
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization();
+#if !CONFIG_HAVE_ACPI_RESUME
+ sdram_dump_mchbar_registers();
+#endif /* !CONFIG_HAVE_ACPI_RESUME */
+ quick_ram_check();
+ MCHBAR16(SSKPD) = 0xCAFE;
+ cbmem_was_initted = !cbmem_recovery(boot_mode==2);
+#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
+ }
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+}
diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c
new file mode 100644
index 0000000..d1f4f7b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/smihandler.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c
new file mode 100644
index 0000000..622f8e8
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
+
+#include "superio_hwm.h"
+
+/* Hardware Monitor */
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+#define HWM_BASE 0x290
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, HWM_BASE + 0x05); // Index port
+ outb(value, HWM_BASE + 0x06); // Data port
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x2e, bank);
+}
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h
new file mode 100644
index 0000000..346b97c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+void hwm_setup(void);
+
+#endif /* SUPERIO_HWM_H */
diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig
index 525121f..b8bb2d6 100644
--- a/src/mainboard/nec/Kconfig
+++ b/src/mainboard/nec/Kconfig
@@ -24,9 +24,13 @@ choice
config BOARD_NEC_POWERMATE_2000
bool "PowerMate 2000"
+config BOARD_NEC_945G_M4
+ bool "945g-m4"
+
endchoice
source "src/mainboard/nec/powermate2000/Kconfig"
+source "src/mainboard/nec/945g-m4/Kconfig"
config MAINBOARD_VENDOR
string
1
0
Patch set updated for coreboot: 82373ea Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg) i945 subsystem added to Kconfig The console is running To fix: RAM init ... and more ...
by HAOUAS Elyes 29 May '14
by HAOUAS Elyes 29 May '14
29 May '14
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5881
-gerrit
commit 82373ea759979a765eeda310200a050463e3ce64
Author: Elyes <ehaouas(a)noos.fr>
Date: Thu May 29 12:04:25 2014 +0200
Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
i945 subsystem added to Kconfig
The console is running
To fix: RAM init ... and more ...
Change-Id: I7b00251e332ac005918cf7c3ed4bef8878bd145b
Signed-off-by: Elyes <ehaouas(a)noos.fr>
---
src/mainboard/nec/945g-m4/Kconfig | 43 +++
src/mainboard/nec/945g-m4/Makefile.inc | 20 ++
src/mainboard/nec/945g-m4/acpi/ec.asl | 49 ++++
src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 86 ++++++
src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 +++++++
src/mainboard/nec/945g-m4/acpi/platform.asl | 91 +++++++
src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++
src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++
src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++
src/mainboard/nec/945g-m4/acpi_tables.c | 230 ++++++++++++++++
src/mainboard/nec/945g-m4/board_info.txt | 3 +
src/mainboard/nec/945g-m4/cmos.layout | 194 ++++++++++++++
src/mainboard/nec/945g-m4/devicetree.cb | 149 +++++++++++
src/mainboard/nec/945g-m4/dsdt.asl | 43 +++
src/mainboard/nec/945g-m4/fadt.c | 155 +++++++++++
src/mainboard/nec/945g-m4/irq_tables.c | 61 +++++
src/mainboard/nec/945g-m4/mainboard.c | 65 +++++
src/mainboard/nec/945g-m4/mptable.c | 89 +++++++
src/mainboard/nec/945g-m4/romstage.c | 324 +++++++++++++++++++++++
src/mainboard/nec/945g-m4/smihandler.c | 49 ++++
src/mainboard/nec/945g-m4/superio_hwm.c | 161 +++++++++++
src/mainboard/nec/945g-m4/superio_hwm.h | 25 ++
src/mainboard/nec/Kconfig | 4 +
23 files changed, 2173 insertions(+)
diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig
new file mode 100644
index 0000000..cf8988f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_NEC_945G_M4
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select CHECK_SLFRCS_ON_RESUME
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627EHG
+ select EARLY_CBMEM_INIT
+ select HAVE_ACPI_TABLES
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+config MAINBOARD_DIR
+ string
+ default nec/945g-m4
+#config DCACHE_RAM_BASE
+# hex
+# default 0xfeffc000
+#config DCACHE_RAM_SIZE
+# hex
+# default 0x9900
+config MAINBOARD_PART_NUMBER
+ string
+ default "945G-M4"
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+config IRQ_SLOT_COUNT
+ int
+ default 18
+config MAX_CPUS
+ int
+ default 4
+#config VGA_BIOS_FILE
+# string
+# default "amipci_01.20"
+endif # BOARD_NEC_945G_M4
diff --git a/src/mainboard/nec/945g-m4/Makefile.inc b/src/mainboard/nec/945g-m4/Makefile.inc
new file mode 100644
index 0000000..30dfea9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+romstage-y += ../../../northbridge/intel/i945/raminit.c
+ramstage-y += superio_hwm.c
diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl
new file mode 100644
index 0000000..e6c30a0
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..bd3379b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ Package() { 0x0001ffff, 1, 0, 17 },
+ Package() { 0x0001ffff, 2, 0, 18 },
+ Package() { 0x0001ffff, 3, 0, 19 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 17 },
+ Package() { 0x001effff, 1, 0, 20 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 18 },
+ Package() { 0x001fffff, 1, 0, 19},
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..c108d3f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 20},
+ Package() { 0x0001ffff, 1, 0, 21},
+ Package() { 0x0001ffff, 2, 0, 22},
+ Package() { 0x0001ffff, 3, 0, 23},
+
+ Package() { 0x0002ffff, 0, 0, 21},
+ Package() { 0x0002ffff, 1, 0, 22},
+ Package() { 0x0002ffff, 2, 0, 23},
+ Package() { 0x0002ffff, 3, 0, 20},
+
+ Package() { 0x0003ffff, 0, 0, 22},
+ Package() { 0x0003ffff, 1, 0, 23},
+ Package() { 0x0003ffff, 2, 0, 20},
+ Package() { 0x0003ffff, 3, 0, 21},
+
+ Package() { 0x0004ffff, 0, 0, 23},
+ Package() { 0x0004ffff, 1, 0, 20},
+ Package() { 0x0004ffff, 2, 0, 21},
+ Package() { 0x0004ffff, 3, 0, 22},
+
+ Package() { 0x0005ffff, 0, 0, 19},
+ Package() { 0x0005ffff, 1, 0, 18},
+ Package() { 0x0005ffff, 2, 0, 17},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ Package() { 0x0006ffff, 0, 0, 18},
+ Package() { 0x0006ffff, 1, 0, 17},
+ Package() { 0x0006ffff, 2, 0, 16},
+ Package() { 0x0006ffff, 3, 0, 19},
+
+ Package() { 0x0009ffff, 0, 0, 21},
+ Package() { 0x0009ffff, 1, 0, 22},
+ Package() { 0x0009ffff, 2, 0, 23},
+ Package() { 0x0009ffff, 3, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl
new file mode 100644
index 0000000..2e4223c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/platform.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl
new file mode 100644
index 0000000..997a33a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/superio.asl
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+ Name (_HID, EISAID("PNP0A05"))
+ Name (_UID, 1)
+
+ Device (UAR1)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+ Name(_DDN, "COM1")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+
+ Device (UAR2)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 2)
+ Name(_DDN, "COM2")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl
new file mode 100644
index 0000000..d1774d4
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x64)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (0xf5c) // Value for Rocky
+ }
+
+ // Method (_AC1, 0, Serialized)
+ // {
+ // Return (0xf5c)
+ // }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (Add (0x0aac, 0x50)) // FIXME
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (0xaaf) // FIXME
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ Return (0xaac) // FIXME
+ }
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {\_PR.CPU1, \_PR.CPU2})
+ }
+ Return (Package() {\_PR.CPU1})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c
new file mode 100644
index 0000000..e6a517e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi_tables.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ current += 0x100;
+ ALIGN_CURRENT;
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt
new file mode 100644
index 0000000..ed23062
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/board_info.txt
@@ -0,0 +1,3 @@
+Category: µATX 24.4 cm x 24.4 cm Form Factor
+Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d…
+Flashrom support: y
diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout
new file mode 100644
index 0000000..b3e8c4e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cmos.layout
@@ -0,0 +1,194 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 40 r 0 unused
+
+# coreboot config options: mainboard specific options
+948 2 e 8 cpufan_cruise_control
+950 2 e 8 sysfan_cruise_control
+952 4 e 9 cpufan_speed
+#956 4 e 10 cpufan_temperature
+960 4 e 9 sysfan_speed
+#964 4 e 10 sysfan_temperature
+
+968 1 e 2 ethernet1
+969 1 e 2 ethernet2
+970 1 e 2 ethernet3
+
+#971 13 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# ram initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# Fan Cruise Control
+8 0 Disabled
+8 1 Speed
+#8 2 Thermal
+# Fan Speed (Rotations per Minute)
+9 0 5625
+9 1 5192
+9 2 4753
+9 3 4326
+9 4 3924
+9 5 3552
+9 6 3214
+9 7 2909
+9 8 2636
+9 9 2393
+9 10 2177
+9 11 1985
+9 12 1814
+9 13 1662
+9 14 1527
+9 15 1406
+#
+# Temperature (�C/�F)
+#10 0 30/86
+#10 1 33/91
+#10 2 36/96
+#10 3 39/102
+#10 4 42/107
+#10 5 45/113
+#10 6 48/118
+#10 7 51/123
+#10 8 54/129
+#10 9 57/134
+#10 10 60/140
+#10 11 63/145
+#10 12 66/150
+#10 13 69/156
+#10 14 72/161
+#10 15 75/167
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb
new file mode 100644
index 0000000..2f4020e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/devicetree.cb
@@ -0,0 +1,149 @@
+#lspci
+#-[0000:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+# +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60] <- PCIe card. integrated vga is an intel, desabled by vendor bios.
+# | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+# +-1c.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+# +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+# +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+# +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+# +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+# +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+# +-1e.0-[03]----02.0 Philips Semiconductors SAA7146 [1131:7146]
+# +-1e.2 Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+# +-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+# +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+# +-1f.2 Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+# \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+#end lspci
+chip northbridge/intel/i945
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge +-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+ device pci 01.0 on end # i945 PCIe root port
+ #+-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60]
+ # \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+ #device pci 02.0 on end # vga controller +-02.0 Intel Corporation 82945G/GZ Integrated Graphics Controller [8086:2772]
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8a" # OS will change it:"0x0a" found via dmesg (linux on vendor bios)
+ register "pirqb_routing" = "0x85" # OS will change it:"0x05" found via dmesg
+ register "pirqc_routing" = "0x8b" # OS will change it:"0x0b"found via dmesg
+ register "pirqd_routing" = "0x8b" # OS will change it:"0x0b" found via dmesg
+ register "pirqe_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqf_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqg_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+ register "pirqh_routing" = "0x8a" # OS will change it: "0x0a"found via dmsg
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x1"
+ device pci 1c.0 on end # Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+ device pci 1d.0 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+ device pci 1d.1 on end # Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+ device pci 1d.2 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+ device pci 1d.3 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+ device pci 1d.7 on end #Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+ device pci 1e.0 on end #-[02]----02.0 Philips Semiconductors SAA7146 [1131:7146]
+ device pci 1e.2 on end # Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+ device pci 1f.0 on # Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+
+ chip superio/winbond/w83627ehg # Super I/O
+ #Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e
+ #Register dump:
+ #idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+ #val 88 63 ff 00 44 00 00 ff 50 05 00 00 83 20 00 ff
+ #def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00
+ device pnp 2e.0 on #LDN 0x00 (Floppy)
+ io 0x60 = 0x3f0 #idx 30 60 61 70 74 f0 f1 f2 f4 f5
+ irq 0x70 = 6 #val 01 03 f0 06 02 8e 00 ff 00 00
+ drq 0x74 = 2 #def 01 03 f0 06 02 8e 00 ff 00 00
+ end
+
+ device pnp 2e.1 on #LDN 0x01 (Parallel port)
+ io 0x60 = 0x378 #idx 30 60 61 70 74 f0
+ irq 0x70 = 7 #val 01 03 78 07 04 3c
+ drq 0x74 = 3 #def 01 03 78 07 04 3f
+ end
+ device pnp 2e.2 on #LDN 0x02 (COM1)
+ io 0x60 = 0x3f8 #idx 30 60 61 70 f0
+ irq 0x70 = 4 #val 01 03 f8 04 00
+ #def 01 03 f8 04 00
+ end
+
+
+ device pnp 2e.3 off #LDN 0x03 (COM2)
+ io 0x60 = 0x2f8 #idx 30 60 61 70 f0 f1
+ irq 0x70 = 3 #val 01 02 f8 03 00 04
+ #def 01 02 f8 03 00 00
+ end
+
+ device pnp 2e.5 on #LDN 0x05 (Keyboard)
+ #idx 30 60 61 62 63 70 72 f0
+ #val 01 00 60 00 64 01 0c 82
+ #def 01 00 60 00 64 01 0c 83
+ end
+ device pnp 2e.106 on #LDN 0x06 (Serial flash interface)
+ io 0x60 = 0x100 #idx 30 62 63
+ #val 00 ff ff
+ #def 00 00 00
+ end
+ #----
+ #LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
+ #idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7
+ #val 01 00 00 00 00 00 5f 5f 00 00 ff ff ff 00
+ #def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00
+ device pnp 2e.007 on # GPIO 1
+ end
+ device pnp 2e.107 off # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.207 on # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 0xa
+ end
+ device pnp 2e.307 on # GPIO 6
+ end
+ device pnp 2e.8 off #LDN 0x08 (WDTO#, PLED)
+ #idx 30 f5 f6 f7
+ #val 00 ff 00 ff
+ #def 00 00 00 00
+ end
+ #----
+ #LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
+ #idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7
+ #val 0e df 00 20 ff ff ff 8c 8c 00 40 df 00 00 20
+ #def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00
+ device pnp 2e.009 on # GPIO 2
+ end
+ device pnp 2e.109 on # GPIO 3
+ end
+ device pnp 2e.209 on # GPIO 4
+ end
+ device pnp 2e.309 on # GPIO 5
+ end
+ device pnp 2e.a on #LDN 0x0a (ACPI)
+ #idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7
+ #val 01 00 01 00 ff 04 00 00 1c 10 09 7c 00 00 00 00
+ #def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00
+ end
+ device pnp 2e.b on #LDN 0x0b (Hardware monitor)
+ io 0x60 = 0x290 #idx 30 60 61 70 f0 f1
+ irq 0x70 = 0 #val 01 0a 10 00 c1 00
+ #def 00 00 00 00 c1 00
+ end
+ end
+ end
+ device pci 1f.1 on end # Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+ device pci 1f.2 on end # Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+ device pci 1f.3 on end # Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+ end
+ end
+end
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl
new file mode 100644
index 0000000..f30c12d
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ //#include "acpi/thermal.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c
new file mode 100644
index 0000000..b55f628
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/fadt.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x20;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+ fadt->pm2_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 85;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = 0x03;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c
new file mode 100644
index 0000000..5e2566b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO@TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 14, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xb, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+ {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0},
+ {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0},
+ {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0},
+ {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0},
+ {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0},
+ {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c
new file mode 100644
index 0000000..568a5c3
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mainboard.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include "superio_hwm.h"
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f35: /* Boot Display */
+ X86_AX = 0x005f; // Success
+ X86_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ X86_AX = 0x005f; // Success
+ X86_CL = 3; // Display ID
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c
new file mode 100644
index 0000000..95a34da
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mptable.c
@@ -0,0 +1,89 @@
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#define INTA 0x00
+#define INTB 0x01
+#define INTC 0x02
+#define INTD 0x03
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ smp_write_processors(mc);
+ /* Bus: Bus ID Type */
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ my_smp_write_bus(mc, 2, "PCI ");
+ my_smp_write_bus(mc, 3, "PCI ");
+ my_smp_write_bus(mc, 4, "ISA ");
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000);
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13);
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+/* mptable_lintsrc(mc, isa_bus); */
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 1);
+ return (unsigned long)smp_write_config_table(v);
+}
+/*MP Config Extended Table Entries:
+--
+System Address Space
+ bus ID: 0 address type: I/O address
+ address base: 0x600000000000
+ address range: 0x148000000000
+Extended Table HOSED!
+*/
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c
new file mode 100644
index 0000000..f64a179
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+void setup_ich7_gpios(void)
+{ /*
+./inteltool -g
+CPU: ID 0xf65, Processor Type 0x0, Family 0xf, Model 0x6, Stepping 0x5
+Northbridge: 8086:2770 (945P) <-- in fact, it is a i945GC
+Southbridge: 8086:27b8 (ICH7)
+============= GPIOS =============
+GPIOBASE = 0x0480 (IO)
+gpiobase+0x0000: 0x1f9fffc3 (GPIO_USE_SEL)
+gpiobase+0x0004: 0xe0e8ffc3 (GP_IO_SEL)
+gpiobase+0x0008: 0x00000000 (RESERVED)
+gpiobase+0x000c: 0xebffffbf (GP_LVL)
+gpiobase+0x0010: 0x00000000 (RESERVED)
+gpiobase+0x0014: 0x00000000 (RESERVED)
+gpiobase+0x0018: 0x00000000 (GPO_BLINK)
+gpiobase+0x001c: 0x00000000 (RESERVED)
+gpiobase+0x0020: 0x00000000 (RESERVED)
+gpiobase+0x0024: 0x00000000 (RESERVED)
+gpiobase+0x0028: 0x00000000 (RESERVED)
+gpiobase+0x002c: 0x0000af03 (GPI_INV)
+gpiobase+0x0030: 0x000000ff (GPIO_USE_SEL2)
+gpiobase+0x0034: 0x000000f0 (GP_IO_SEL2)
+gpiobase+0x0038: 0x000000f7 (GP_LVL2)
+gpiobase+0x003c: 0x00000000 (RESERVED)
+*/
+ printk(BIOS_DEBUG, " GPIOS...");
+ /* General Registers */
+ outl(0x1f9fffc3, DEFAULT_GPIOBASE + GPIO_USE_SEL);
+ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + GP_IO_SEL);
+ outl(0xebffffbf, DEFAULT_GPIOBASE + GP_LVL);
+ /* Output Control Registers */
+ outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
+ /* Input Control Registers */
+ outl(0x0000af03, DEFAULT_GPIOBASE + GPI_INV);
+ outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL2);
+ outl(0x000000f0, DEFAULT_GPIOBASE + GP_IO_SEL2);
+ outl(0x000000f7, DEFAULT_GPIOBASE + GP_LVL2);
+}
+static void ich7_enable_lpc(void)
+{
+// see http://macbook.donderklumpen.de/coreboot/ section Stage 2: ROM stage
+/* lspci -nnvvvxxx -s 00:1f.0
+lspci -nnvvvxxx -s 00:1f.0
+00:1f.0 ISA bridge [0601]: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] (rev 01)
+ Subsystem: Packard Bell B.V. Device [1631:e015]
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Capabilities: [e0] Vendor Specific Information: Len=0c <?>
+ Kernel driver in use: lpc_ich
+ Kernel modules: intel_rng
+00: 86 80 b8 27 07 00 10 02 01 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 31 16 15 e0
+30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
+40: 01 08 00 00 80 00 00 00 81 04 00 00 10 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 8a 85 8b 8b d0 00 00 00 80 80 80 8a 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 10 00 0f 34 01 0a fc 00 01 47 fc 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 28 06 00 00 39 00 00 00 13 00 00 00 00 03 00 00
+b0: 00 00 f0 00 00 00 00 00 00 00 02 80 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 33 22 11 00 67 45 00 00 c0 80 00 00 00 00 00 00
+e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
+f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00*/
+ // Enable Serial IRQ
+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* datasheet page 363 default value 0x10 */
+ // LPC I/O decode range
+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* datasheet: default value 0x0000 */
+ // LPC Interface Enables
+ pci_write_config16(LPC_DEV, LPC_EN, 0x340f); /* datasheet: default value 0x0000 */
+// PIRQ [A-D] -> see devicetree.cb
+// pci_write_config8(LPC_DEV, 0x60, 0x8a);
+// pci_write_config8(LPC_DEV, 0x61, 0x85);
+// pci_write_config8(LPC_DEV, 0x62, 0x8b);
+// pci_write_config8(LPC_DEV, 0x63, 0x8b);
+// PIRQ [E-H]*/ > see devicetree.cb
+// pci_write_config8(LPC_DEV, 0x68, 0x80);
+// pci_write_config8(LPC_DEV, 0x69, 0x80);
+// pci_write_config8(LPC_DEV, 0x6a, 0x80);
+// pci_write_config8(LPC_DEV, 0x6b, 0x8a);
+/* GEN1_DEC. LPC interface generic decode Rang1 */
+ pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
+// pci_write_config16(LPC_DEV, 0x84, 0x0a01); /* datasheet page 364: conf32 - default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x86, 0x00fc);
+ /* GEN2_DEC. LPC interface generic decode Rang2 */
+ pci_write_config32(LPC_DEV, 0x88, 0x00fc4701);
+// pci_write_config16(LPC_DEV, 0x88, 0x4701); /* datasheet - conf32: default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x8a, 0x00fc);
+ /* GEN3_DEC. LPC interface generic decode Rang3 */
+// pci_write_config32(LPC_DEV, 0x8c,0x00000000);
+// pci_write_config16(LPC_DEV, 0x8c, 0x0000); /* datasheet - conf32: default value 0x00000000 */
+// pci_write_config16(LPC_DEV, 0x8e, 0x0000);
+ /* GEN4_DEC. LPC interface generic decode Rang4 */
+// pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+// pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+}
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ /*./inteltool -r |grep -i 0x0014
+ 0x0014: 0x80000001 */
+// RCBA32(V0CTL) = 0x80000001; see i945/ ich7_setup_dmi_rcrb()
+ /* ./inteltool -r |grep -i 0x001C
+ 0x001c: 0x03128010 */
+// RCBA32(V1CAP) = 0x03128010; see i945/ ich7_setup_dmi_rcrb()
+ /* Device 1f interrupt pin register */
+ /*
+ ./inteltool -r |grep -i 0x3100
+ 0x3100: 0x00042210 */
+ RCBA32(D31IP) = 0x00042210;
+ /* Device 1d interrupt pin register */
+ /* ./inteltool -r |grep -i 0x310c
+ 0x310c: 0x00214321 */
+ RCBA32(D28IP) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(D27IP) = 0x00000001;
+ /* dev irq route register */
+ /*./inteltool -r |grep -i 0x3140
+ 0x3140: 0x32410132 */
+ RCBA16(D31IR) = 0x3241;
+ RCBA16(D30IR) = 0x0132;
+//
+ /* ./inteltool -r |grep -i 0x3144
+ 0x3144: 0x32100237*/
+ RCBA16(D29IR) = 0x3210;
+ RCBA16(D28IR) = 0x0237;
+ /*./inteltool -r |grep -i 0x3148
+ 0x3148: 0x00003210 */
+ RCBA16(D27IR) = 0x0000;
+//
+ /* Enable IOAPIC */
+ /*./inteltool -r |grep -i 0x31f
+ 0x31fc: 0x03000000 */
+ //RCBA8(0x31ff) = 0x00;
+ RCBA32(0x31fc) |= 3 << 24;
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
+ /* Enable PCIe Root Port Clock Gate */
+ /* ./inteltool -r |grep -i 0x341c
+ 0x341c: 0x00000001 */
+ RCBA32(CG) = 0x00000001;
+}
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ /*./inteltool -r |grep -i 0x0088
+ 0x0088: 0x0011d000 */
+ RCBA32(0x0088) = 0x0011d000;
+ /*./inteltool -r |grep -i 0x01fc
+ 0x01fc: 0x0000060f */
+ RCBA16(0x01fc) = 0x060f;
+ /*./inteltool -r |grep -i 0x01f4
+ 0x01f4: 0x86000040 */
+ RCBA32(0x01f4) = 0x86000040;
+ /* ./inteltool -r |grep -i 0x0214
+ 0x0214: 0x10030509*/
+ RCBA32(0x0214) = 0x10030549;
+ /*./inteltool -r |grep -i 0x0218
+ 0x0218: 0x00020504 */
+ RCBA32(0x0218) = 0x00020504;
+ /*./inteltool -r |grep -i 0x0220
+ 0x0220: 0x000000c5 */
+ RCBA8(0x0220) = 0xc5; /*c5;*/
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(FD) |= (1 << 0);
+ /*./inteltool -r |grep -i 0x0200
+ 0x0130: 0x02000002
+ 0x0200: 0x01102008 */
+// RCBA16(0x0200) = 0x0110;
+ RCBA32(0x0200) = 0x01102008;
+ /*./inteltool -r |grep -i 0x2028
+ 0x2028: 0x0038f221
+ ./inteltool -r |grep -i 0x2024
+ 0x2024: 0x0d303000*/
+ RCBA8(0x2027) = 0x00;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+void main(unsigned long bist)
+{
+ u32 reg32;
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ if (bist == 0)
+ enable_lapic();
+ ich7_enable_lpc();
+ /* Set up the console */
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ outb(0x6, 0xcf9);
+ while (1) asm("hlt");
+ }
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+ }
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ sdram_initialize(boot_mode, NULL);
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+ /* Chipset Errata! */
+ fixup_i945_errata();
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization();
+#if !CONFIG_HAVE_ACPI_RESUME
+ sdram_dump_mchbar_registers();
+#endif /* !CONFIG_HAVE_ACPI_RESUME */
+ quick_ram_check();
+ MCHBAR16(SSKPD) = 0xCAFE;
+ cbmem_was_initted = !cbmem_recovery(boot_mode==2);
+#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
+ }
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+}
diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c
new file mode 100644
index 0000000..d1f4f7b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/smihandler.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c
new file mode 100644
index 0000000..622f8e8
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
+
+#include "superio_hwm.h"
+
+/* Hardware Monitor */
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+#define HWM_BASE 0x290
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, HWM_BASE + 0x05); // Index port
+ outb(value, HWM_BASE + 0x06); // Data port
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x2e, bank);
+}
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h
new file mode 100644
index 0000000..346b97c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+void hwm_setup(void);
+
+#endif /* SUPERIO_HWM_H */
diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig
index 525121f..b8bb2d6 100644
--- a/src/mainboard/nec/Kconfig
+++ b/src/mainboard/nec/Kconfig
@@ -24,9 +24,13 @@ choice
config BOARD_NEC_POWERMATE_2000
bool "PowerMate 2000"
+config BOARD_NEC_945G_M4
+ bool "945g-m4"
+
endchoice
source "src/mainboard/nec/powermate2000/Kconfig"
+source "src/mainboard/nec/945g-m4/Kconfig"
config MAINBOARD_VENDOR
string
1
0