coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

1 participants
1066 discussions

Patch merged into coreboot/master: f646f6d amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit f646f6d5822e648d9ba647a97981407c5c953b92 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 6 14:10:04 2014 +0300 amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT Removed function only read ACPI MMIO base address from a couple of registers in IO space. Change-Id: I25a31b7ac1706b9eebc5db0b9604039928328b0a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5683 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5683 for details. -gerrit

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Patch merged into coreboot/master: 6b4b151 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit 6b4b1513a5026b6c9f2883bf6687341405579689 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 12:05:53 2014 +0300 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP Change-Id: I9f27e1e814a80864d8ca315fe816a083c55708c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5682 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5682 for details. -gerrit

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Patch merged into coreboot/master: 838e211 AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptask
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit 838e211013d76cb8de86d8210bb52f396b9e369c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 12:21:04 2014 +0300 AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptask Pass parameter Func like fam14, fam15tn and fam16kb. Change-Id: I262bf88e431f7035e668ac8f3fb29ac0690b3e52 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5681 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5681 for details. -gerrit

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Patch merged into coreboot/master: 5e19fa4 AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit 5e19fa4c510a09abd9338fcc615be0c6cfbe3d6e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun May 4 23:13:54 2014 +0300 AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET This is x86 "standard" 0xcf9 reset mechanism. Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5680 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5680 for details. -gerrit

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Patch merged into coreboot/master: f1bb19a AGESA fam14: Comment lack of PCI-e slot resets
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit f1bb19abee7a81d5463c5885b57fe2cbc5d21715 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun May 4 17:23:49 2014 +0300 AGESA fam14: Comment lack of PCI-e slot resets These boards return with AGESA_UNSUPPORTED, while other boards return AGESA_SUCCESS here when there is no hardware for external reset signalling. Change-Id: I5aed211b1812888af55a691cfbfa8d7b5aff91bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5679 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5679 for details. -gerrit

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Patch merged into coreboot/master: c459f96 AGESA: Add common callouts
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit c459f9658b73ccb6a4300a00eafef90412fc4984 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun May 4 17:07:45 2014 +0300 AGESA: Add common callouts Most of the callouts are not specific to board or even family. Start new file with default callouts doing nothing and returning either AGESA_SUCCESS or AGESA_UNSUPPORTED. Also add callout for returning empty IdsIdData. This feature is not used and could be easily overriden at board-level at later time. Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5678 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5678 for details. -gerrit

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Patch merged into coreboot/master: cc84a00 build system: re-enable clang use
by gerrit＠coreboot.org 26 May '14

26 May '14

the following patch was just integrated into master: commit cc84a001b8b71d457f30e5520c1583bbd297d691 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 14 21:05:35 2014 +0200 build system: re-enable clang use Change-Id: I6e07fdec449d0b259d77986f65a60aa36d367cc8 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5747 Tested-by: build bot (Jenkins) See http://review.coreboot.org/5747 for details. -gerrit

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Patch set updated for coreboot: a4915b3 superio/winbond/w83627ehg: Remove pnp_enter symbol from global
by Edward O'Callaghan 26 May '14

26 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5871 -gerrit commit a4915b3b1e1daad4bbd04fc62e8a66f4da28958d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 04:35:48 2014 +1000 superio/winbond/w83627ehg: Remove pnp_enter symbol from global Part 2/2: Break this poor relationship between boards and Super I/O support to be more well-defined. The Super I/O pnp_entry/exit functions should not be exposed into the global name-space, rather should be static-local. Change-Id: Ie39235f2926a2165092319a6b1375e505b7dac14 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 13 +++++++++++++ src/mainboard/asus/a8v-e_se/romstage.c | 13 +++++++++++++ src/mainboard/ibase/mb899/romstage.c | 13 +++++++++++++ src/mainboard/msi/ms7260/romstage.c | 5 +---- src/mainboard/msi/ms9652_fam10/romstage.c | 7 +------ src/superio/winbond/w83627ehg/Makefile.inc | 1 - src/superio/winbond/w83627ehg/early_serial.c | 16 ++++++++++++---- src/superio/winbond/w83627ehg/w83627ehg.h | 6 ++++-- 8 files changed, 57 insertions(+), 17 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1dea57b..ce8bec0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -97,6 +97,19 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index abe5f84..bc159c2 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -97,6 +97,19 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0957795..3b83d17 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -69,6 +69,19 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..072bae9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -119,12 +119,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ - pnp_write_config(SERIAL_DEV, 0x24, 0); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..eff291b 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -103,7 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; - u8 reg; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -121,11 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc index 6914411..3b59350 100644 --- a/src/superio/winbond/w83627ehg/Makefile.inc +++ b/src/superio/winbond/w83627ehg/Makefile.inc @@ -19,5 +19,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..a79f0ff 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,15 +22,24 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } + +void w83627ehg_serial_clk(device_t) +{ + pnp_enter_ext_func_mode(dev); + /* We have 24MHz input. */ + u8 reg = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (reg & 0xbf)); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..b514488 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,9 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +#include <arch/io.h> +#include <device/pnp.h> + +void w83627ehg_serial_clk(device_t); #endif /* SUPERIO_WINBOND_W83627EHG_H */

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Patch set updated for coreboot: fb2ae2b superio/winbond/w83627ehg: EOL model specific early_serial.c
by Edward O'Callaghan 26 May '14

26 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5871 -gerrit commit fb2ae2b9b461ae17a12d861cb15343576c4bf90a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 04:35:48 2014 +1000 superio/winbond/w83627ehg: EOL model specific early_serial.c NOTFORMERGE: boards break because of this poor relationship.. Change-Id: Ie39235f2926a2165092319a6b1375e505b7dac14 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/winbond/w83627ehg/Makefile.inc | 1 - src/superio/winbond/w83627ehg/early_serial.c | 37 ---------------------------- src/superio/winbond/w83627ehg/w83627ehg.h | 3 --- 3 files changed, 41 deletions(-) diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc index 6914411..3b59350 100644 --- a/src/superio/winbond/w83627ehg/Makefile.inc +++ b/src/superio/winbond/w83627ehg/Makefile.inc @@ -19,5 +19,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c deleted file mode 100644 index 346d6cf..0000000 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "w83627ehg.h" - -void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..e2084c5 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,4 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); - #endif /* SUPERIO_WINBOND_W83627EHG_H */

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Patch set updated for coreboot: ebb2418 superio/winbond/w83627ehg: Depreciate romstage component
by Edward O'Callaghan 26 May '14

26 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5870 -gerrit commit ebb2418383c6d040185c747d14a8c91142d317c4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 04:03:24 2014 +1000 superio/winbond/w83627ehg: Depreciate romstage component Part 1/2: These are actually not necessary if Super I/O support is properly utilized. Change-Id: I39b621e582f8d0762276d29492c91dce500f0665 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/nvidia/l1_2pvv/romstage.c | 3 ++- src/superio/winbond/w83627ehg/Makefile.inc | 1 - src/superio/winbond/w83627ehg/early_init.c | 38 ------------------------------ src/superio/winbond/w83627ehg/w83627ehg.h | 5 ---- 4 files changed, 2 insertions(+), 45 deletions(-) diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d411354..df78a0c 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -36,6 +36,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -119,11 +120,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc index 19f069f..6914411 100644 --- a/src/superio/winbond/w83627ehg/Makefile.inc +++ b/src/superio/winbond/w83627ehg/Makefile.inc @@ -19,6 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_init.c romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c diff --git a/src/superio/winbond/w83627ehg/early_init.c b/src/superio/winbond/w83627ehg/early_init.c deleted file mode 100644 index d767aa0..0000000 --- a/src/superio/winbond/w83627ehg/early_init.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "w83627ehg.h" - -void w83627ehg_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void w83627ehg_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 02041fc..221de7b 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,11 +54,6 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -#if defined(__PRE_RAM__) -void w83627ehg_enable_dev(device_t dev, u16 iobase); -void w83627ehg_disable_dev(device_t dev); -#endif - void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev);

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coreboot-gerrit May 2014