coreboot-gerrit May 2014

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New patch to review for coreboot: c559937 ChromeOS: Rename chromeos.c in vendorcode
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5645 -gerrit commit c559937bd05ff0636b61674dc7e71d370e001610 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 28 23:25:01 2014 +0300 ChromeOS: Rename chromeos.c in vendorcode Rename the file to vboot_handoff.c and compile it conditionally with VBOOT_VERIFY_FIRMWARE. Change-Id: I8b6fd91063b54cb8f5927c6483a398b75e1d262a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Makefile.inc | 4 +- src/vendorcode/google/chromeos/chromeos.c | 120 ------------------------- src/vendorcode/google/chromeos/vboot_handoff.c | 115 ++++++++++++++++++++++++ 3 files changed, 117 insertions(+), 122 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 4eb3817..eca8084 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-y += chromeos.c -ramstage-y += chromeos.c romstage-$(CONFIG_ARCH_X86) += vbnv.c ramstage-$(CONFIG_ARCH_X86) += vbnv.c romstage-$(CONFIG_ARCH_X86) += vboot.c @@ -35,6 +33,8 @@ CFLAGS += -DMOCK_TPM=0 endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) +romstage-y += vboot_handoff.c +ramstage-y += vboot_handoff.c romstage-y += vboot_loader.c rmodules-y += vboot_wrapper.c diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c deleted file mode 100644 index f8dd7dc..0000000 --- a/src/vendorcode/google/chromeos/chromeos.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include "chromeos.h" -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include "vboot_handoff.h" -#endif -#include <boot/coreboot_tables.h> -#include <cbmem.h> -#include <console/console.h> - -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <payload_loader.h> - -int vboot_enable_developer(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) { - printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", - __func__); - return 0; - } - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); -} - -int vboot_enable_recovery(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); -} - -static void *vboot_get_payload(size_t *len) -{ - struct vboot_handoff *vboot_handoff; - struct firmware_component *fwc; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return NULL; - - if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { - printk(BIOS_ERR, "Invalid boot loader index: %d\n", - CONFIG_VBOOT_BOOT_LOADER_INDEX); - return NULL; - } - - fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; - - if (len != NULL) - *len = fwc->size; - - printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", - fwc->size, fwc->address); - - return (void *)fwc->address; -} - -static int vboot_locate_payload(struct payload *payload) -{ - void *buffer; - size_t size; - - buffer = vboot_get_payload(&size); - - if (buffer == NULL) - return -1; - - payload->backing_store.data = buffer; - payload->backing_store.size = size; - - return 0; -} - -const struct payload_loader_ops vboot_payload_loader = { - .name = "VBOOT", - .locate = vboot_locate_payload, -}; - -int vboot_get_handoff_info(void **addr, uint32_t *size) -{ - struct vboot_handoff *vboot_handoff; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return -1; - - *addr = vboot_handoff; - *size = sizeof(*vboot_handoff); - return 0; -} -#endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c new file mode 100644 index 0000000..937b2e3 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include "chromeos.h" +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <console/console.h> +#include <payload_loader.h> +#include "vboot_handoff.h" + +int vboot_enable_developer(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) { + printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", + __func__); + return 0; + } + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); +} + +static void *vboot_get_payload(size_t *len) +{ + struct vboot_handoff *vboot_handoff; + struct firmware_component *fwc; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff == NULL) + return NULL; + + if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { + printk(BIOS_ERR, "Invalid boot loader index: %d\n", + CONFIG_VBOOT_BOOT_LOADER_INDEX); + return NULL; + } + + fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; + + if (len != NULL) + *len = fwc->size; + + printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", + fwc->size, fwc->address); + + return (void *)fwc->address; +} + +static int vboot_locate_payload(struct payload *payload) +{ + void *buffer; + size_t size; + + buffer = vboot_get_payload(&size); + + if (buffer == NULL) + return -1; + + payload->backing_store.data = buffer; + payload->backing_store.size = size; + + return 0; +} + +const struct payload_loader_ops vboot_payload_loader = { + .name = "VBOOT", + .locate = vboot_locate_payload, +}; + +int vboot_get_handoff_info(void **addr, uint32_t *size) +{ + struct vboot_handoff *vboot_handoff; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff == NULL) + return -1; + + *addr = vboot_handoff; + *size = sizeof(*vboot_handoff); + return 0; +}

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New patch to review for coreboot: 3eeece3 ChromeOS: Rename init_chromeos() to init_trusted_platform()
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5644 -gerrit commit 3eeece3369afe80cd9220dc089acd4f90da739f6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 20 23:57:17 2013 +0200 ChromeOS: Rename init_chromeos() to init_trusted_platform() The function does TPM hardware initialisation but is not really related to use of ChromeOS. Change-Id: Ie67c6e2b07485bdf861f74f9a8768882d9495a01 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 8 ++------ src/drivers/pc80/Kconfig | 9 +++++++++ src/include/bootmode.h | 1 + src/lib/bootmode.c | 26 ++++++++++++++++++++++++++ src/mainboard/google/butterfly/chromeos.c | 2 +- src/mainboard/google/butterfly/romstage.c | 8 ++------ src/mainboard/google/link/chromeos.c | 2 +- src/mainboard/google/link/romstage.c | 8 ++------ src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/parrot/romstage.c | 8 ++------ src/mainboard/google/pit/chromeos.c | 2 +- src/mainboard/google/snow/chromeos.c | 2 +- src/mainboard/google/stout/acpi_tables.c | 2 +- src/mainboard/google/stout/chromeos.c | 2 +- src/mainboard/google/stout/romstage.c | 7 +------ src/mainboard/intel/emeraldlake2/chromeos.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 8 ++------ src/mainboard/samsung/lumpy/romstage.c | 7 +------ src/mainboard/samsung/stumpy/romstage.c | 7 +------ src/vendorcode/google/chromeos/Kconfig | 8 -------- src/vendorcode/google/chromeos/chromeos.h | 2 +- src/vendorcode/google/chromeos/vboot.c | 24 +----------------------- 22 files changed, 59 insertions(+), 88 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9e27668..a77cb0c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -36,9 +36,7 @@ #include <ramstage_cache.h> #include <romstage_handoff.h> #include <reset.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <bootmode.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> #endif @@ -279,9 +277,7 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 485dd64..656d361 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -23,3 +23,12 @@ config TPM Enable this option to enable TPM support in coreboot. If unsure, say N. + +config NO_TPM_RESUME + bool + default n + depends on TPM + help + On some boards the TPM stays powered up in S3. On those + boards, booting Windows will break if the TPM resume command + is sent during an S3 resume. diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 1b8d1be..eeb11da 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -38,4 +38,5 @@ static inline int recovery_mode_enabled(void) { return 0; } static inline int developer_mode_enabled(void) { return 0; } #endif +void init_trusted_platform(int bootmode); #endif /* __BOOTMODE_H__ */ diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 9818490..2f815d3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -18,6 +18,8 @@ */ #include <rules.h> +#include <kconfig.h> +#include <console/console.h> #include <bootmode.h> #if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> @@ -78,3 +80,27 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + +#if ENV_ROMSTAGE +void init_trusted_platform(int bootmode) +{ +#if IS_ENABLED(CONFIG_TPM) + /* With CONFIG_CHROMEOS, u-boot does TPM init on power-on. + * Doing TPM startup when we're not coming in on the S3 resume path + * saves us roughly 20ms in boot time only. This does not seem to + * be worth an API change to vboot_reference-firmware right now, so + * just bail out early: + */ + if (IS_ENABLED(CONFIG_CHROMEOS) && bootmode != 2) + return; + + /* On some boards the TPM stays powered up in S3. */ + if (IS_ENABLED(CONFIG_NO_TPM_RESUME) && bootmode == 2) + return; + + init_vboot(bootmode); +#else + printk(BIOS_DEBUG, "TPM: support not enabled in build.\n"); +#endif +} +#endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 8f249c6..61097c3 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d32f3f0..0b2f5c9 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -38,9 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <bootmode.h> #include <cbfs.h> static void pch_enable_lpc(void) @@ -273,8 +271,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index bf6d428..4bdda85 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66d2067..f4fd09e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -40,9 +40,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <bootmode.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -317,8 +315,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index fcf6374..be45735 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 361c19b..7cf1055 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -38,9 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <bootmode.h> #include <cbfs.h> #include "ec/compal/ene932/ec.h" @@ -273,8 +271,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c index 08b4e99..42ffe44 100644 --- a/src/mainboard/google/pit/chromeos.c +++ b/src/mainboard/google/pit/chromeos.c @@ -22,7 +22,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <cpu/samsung/exynos5420/cpu.h> #include <cpu/samsung/exynos5420/gpio.h> diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index c525a81..0e88ef2 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -22,7 +22,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/gpio.h> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 62d5891..d600aec 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -31,7 +31,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" #include "onboard.h" diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 74955de..2032c05 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f53c07d..011ff7d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -39,9 +39,6 @@ #include <cpu/x86/msr.h> #include "gpio.h" #include <bootmode.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -327,8 +324,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 72adaf7..bc99667 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9308e96..93c02de 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -38,9 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <bootmode.h> #define SIO_PORT 0x164e @@ -325,8 +323,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index ef5a836..1882efe 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -45,9 +45,6 @@ #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif static void pch_enable_lpc(void) { @@ -345,8 +342,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 8d2a3e4..6e7b05e 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -45,9 +45,6 @@ #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG_USE_OPTION_TABLE @@ -352,8 +349,6 @@ void main(unsigned long bist) } #endif post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + init_trusted_platform(boot_mode); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a1a9d9a..6c074c7 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -124,13 +124,5 @@ config VBOOT_REFCODE_INDEX This is the index of the reference code component in the verified firmware block. -config NO_TPM_RESUME - bool - default n - help - On some boards the TPM stays powered up in S3. On those - boards, booting Windows will break if the TPM resume command - is sent during an S3 resume. - endif endmenu diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index dc34dc3..acb2052 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -32,7 +32,7 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); /* functions implemented in vboot.c */ -void init_chromeos(int bootmode); +void init_vboot(int bootmode); #if CONFIG_VBOOT_VERIFY_FIRMWARE /* Returns 0 on success < 0 on error. */ diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index 03d759c..58f96bd 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -25,7 +25,6 @@ #include "chromeos.h" //#define EXTRA_LOGGING -#define UBOOT_DOES_TPM_STARTUP #define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ @@ -39,11 +38,6 @@ #define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) #define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) -#if CONFIG_NO_TPM_RESUME -static void init_vboot(int bootmode) -{ -} -#else static const struct { u8 buffer[12]; } tpm_resume_cmd = { @@ -182,21 +176,11 @@ static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) return result; } -static void init_vboot(int bootmode) +void init_vboot(int bootmode) { u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; -#ifdef UBOOT_DOES_TPM_STARTUP - /* Doing TPM startup when we're not coming in on the S3 resume path - * saves us roughly 20ms in boot time only. This does not seem to - * be worth an API change to vboot_reference-firmware right now, so - * let's keep the code around, but just bail out early: - */ - if (bootmode != 2) - return; -#endif - printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); printk(BIOS_SPEW, "TPM: Init\n"); @@ -236,9 +220,3 @@ static void init_vboot(int bootmode) hard_reset(); #endif } -#endif - -void init_chromeos(int bootmode) -{ - init_vboot(bootmode); -}

1 0

New patch to review for coreboot: 36196a6 ChromeOS boards: Always build code for bootmode straps
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5643 -gerrit commit 36196a698c98539bf152cd3a790c592deac3d4ea Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 28 23:41:06 2014 +0300 ChromeOS boards: Always build code for bootmode straps Leave it under BOOTMODE_STRAPS to control whether these have any functional meaning on the build. Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/coreboot_table.c | 2 +- src/mainboard/google/bolt/Makefile.inc | 4 ++-- src/mainboard/google/butterfly/Makefile.inc | 4 ++-- src/mainboard/google/falco/Makefile.inc | 4 ++-- src/mainboard/google/link/Makefile.inc | 4 ++-- src/mainboard/google/parrot/Makefile.inc | 4 ++-- src/mainboard/google/peppy/Makefile.inc | 4 ++-- src/mainboard/google/rambi/Makefile.inc | 6 +++--- src/mainboard/google/slippy/Makefile.inc | 4 ++-- src/mainboard/google/stout/Makefile.inc | 4 ++-- src/mainboard/intel/baskingridge/Makefile.inc | 4 ++-- src/mainboard/intel/emeraldlake2/Makefile.inc | 4 ++-- src/mainboard/intel/wtm2/Makefile.inc | 4 ++-- src/mainboard/samsung/lumpy/Makefile.inc | 4 ++-- src/mainboard/samsung/stumpy/Makefile.inc | 4 ++-- 15 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index fbc1902..65a0c3a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -144,7 +144,6 @@ static void lb_framebuffer(struct lb_header *header) #endif } -#if CONFIG_CHROMEOS void fill_lb_gpio(struct lb_gpio *gpio, int num, int polarity, const char *name, int value) { @@ -156,6 +155,7 @@ void fill_lb_gpio(struct lb_gpio *gpio, int num, strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); } +#if CONFIG_CHROMEOS static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; diff --git a/src/mainboard/google/bolt/Makefile.inc b/src/mainboard/google/bolt/Makefile.inc index 4e71be7..e30d0ae 100644 --- a/src/mainboard/google/bolt/Makefile.inc +++ b/src/mainboard/google/bolt/Makefile.inc @@ -19,8 +19,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 5b4e74c..f735e9c 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 3269d2d..b9a1e04 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -19,8 +19,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ba9a5aa..b8899e3 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -19,8 +19,8 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 5ad5454..2275bec 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -19,5 +19,5 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc index 7f8cae3..21c4c96 100644 --- a/src/mainboard/google/peppy/Makefile.inc +++ b/src/mainboard/google/peppy/Makefile.inc @@ -19,8 +19,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 77b2f2c..d3e5ad8 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -19,9 +19,9 @@ subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += gpio.c +romstage-y += chromeos.c +ramstage-y += chromeos.c +ramstage-y += gpio.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 7a62022..9e3c310 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -19,8 +19,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 2ebf74b..4dae171 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -19,8 +19,8 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 80385d6..b215ad7 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index c595a62..a1f72e1 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index a4afb7e..e519bb2 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 4c6d647..a6be0c2 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -19,8 +19,8 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index c595a62..a1f72e1 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c

1 0

New patch to review for coreboot: c60bf90 Declare get_write_protect_state() without ChromeOS
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5642 -gerrit commit c60bf9035e1b8681df9e95d1b9efa380f56ee4a8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 28 23:41:06 2014 +0300 Declare get_write_protect_state() without ChromeOS Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/bootmode.h | 2 ++ src/mainboard/google/bolt/chromeos.c | 2 +- src/mainboard/google/falco/chromeos.c | 2 +- src/mainboard/google/peppy/chromeos.c | 2 +- src/mainboard/google/rambi/chromeos.c | 2 +- src/mainboard/google/slippy/chromeos.c | 2 +- src/mainboard/intel/baskingridge/chromeos.c | 2 +- src/mainboard/intel/wtm2/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 3 --- 9 files changed, 9 insertions(+), 10 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 4a9b4e7..1b8d1be 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -20,6 +20,8 @@ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__ +/* functions implemented per mainboard: */ +int get_write_protect_state(void); int get_developer_mode_switch(void); int get_recovery_mode_switch(void); diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c index f003f42..8bbf0d4 100644 --- a/src/mainboard/google/bolt/chromeos.c +++ b/src/mainboard/google/bolt/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 0056dfd..fbe05be 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index 0056dfd..fbe05be 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 9223858..cf52f20 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 0056dfd..fbe05be 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 7efd065..c667fd4 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 9c4c3b4..1c11876 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 88c6d86..dc34dc3 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -24,9 +24,6 @@ #include <stdint.h> #include <bootmode.h> -/* functions implemented per mainboard: */ -int get_write_protect_state(void); - /* functions implemented in vbnv.c: */ int get_recovery_mode_from_vbnv(void); int vboot_wants_oprom(void);

1 0

New patch to review for coreboot: 3dfe41f Rename from save_chromeos_gpios() to init_bootmode_straps()
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5641 -gerrit commit 3dfe41f4173f931196575d31d3ec5d71603f5fb8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 3 10:45:28 2014 +0300 Rename from save_chromeos_gpios() to init_bootmode_straps() This feature is no longer specific to ChromeOS builds. Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/bootmode.h | 2 ++ src/mainboard/samsung/lumpy/chromeos.c | 8 ++++---- src/mainboard/samsung/lumpy/romstage.c | 5 ++--- src/mainboard/samsung/stumpy/chromeos.c | 8 ++++---- src/mainboard/samsung/stumpy/romstage.c | 5 ++--- src/vendorcode/google/chromeos/chromeos.h | 3 --- 6 files changed, 14 insertions(+), 17 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index a2c3411..4a9b4e7 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -27,9 +27,11 @@ int gfx_get_init_done(void); void gfx_set_init_done(int done); #if CONFIG_BOOTMODE_STRAPS +void init_bootmode_straps(void); int developer_mode_enabled(void); int recovery_mode_enabled(void); #else +static inline void init_bootmode_straps(void) { } static inline int recovery_mode_enabled(void) { return 0; } static inline int developer_mode_enabled(void) { return 0; } #endif diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index bdc0148..acbbb46 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -111,9 +111,9 @@ int get_recovery_mode_switch(void) return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) +void init_bootmode_straps(void) { +#ifdef __PRE_RAM__ u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; u32 gp_lvl2 = inl(gpio_base + GP_LVL2); u32 gp_lvl = inl(gpio_base + GP_LVL); @@ -130,5 +130,5 @@ void save_chromeos_gpios(void) flags |= (1 << FLAG_DEV_MODE); pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} #endif +} diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 55c1f0a..ef5a836 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -31,6 +31,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <bootmode.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" @@ -201,9 +202,7 @@ void main(unsigned long bist) console_init(); -#if CONFIG_CHROMEOS - save_chromeos_gpios(); -#endif + init_bootmode_straps(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 731126c..6b296c0 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -18,7 +18,7 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -108,9 +108,9 @@ int get_recovery_mode_switch(void) return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) +void init_bootmode_straps(void) { +#ifdef __PRE_RAM__ u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; u32 gp_lvl3 = inl(gpio_base + GP_LVL3); u32 gp_lvl2 = inl(gpio_base + GP_LVL2); @@ -128,5 +128,5 @@ void save_chromeos_gpios(void) flags |= (1 << FLAG_DEV_MODE); pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} #endif +} diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 3e27a6a..8d2a3e4 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <bootmode.h> #include "superio/ite/it8772f/it8772f.h" #include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" @@ -238,9 +239,7 @@ void main(unsigned long bist) CONFIG_TTYS0_BASE); console_init(); -#if CONFIG_CHROMEOS - save_chromeos_gpios(); -#endif + init_bootmode_straps(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index e501427..88c6d86 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,9 +26,6 @@ /* functions implemented per mainboard: */ int get_write_protect_state(void); -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void); -#endif /* functions implemented in vbnv.c: */ int get_recovery_mode_from_vbnv(void);

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New patch to review for coreboot: f117a03 ChromeOS boards: Use explicit include of chromeos.c
by Kyösti Mälkki 03 May '14

03 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5640 -gerrit commit f117a0357ac80c42626040c668d9cc6a1eef4a0b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 28 23:41:06 2014 +0300 ChromeOS boards: Use explicit include of chromeos.c Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/emeraldlake2/Makefile.inc | 21 +++++++++++++++++++++ src/mainboard/samsung/lumpy/Makefile.inc | 5 ++++- src/mainboard/samsung/stumpy/Makefile.inc | 21 +++++++++++++++++++++ src/vendorcode/google/chromeos/Makefile.inc | 4 ---- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc new file mode 100644 index 0000000..c595a62 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index bb412ce..4c6d647 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -19,6 +19,9 @@ ramstage-y += ec.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + SPD_BIN = $(obj)/spd.bin # Include spd rom data diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc new file mode 100644 index 0000000..c595a62 --- /dev/null +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 21e1750..4eb3817 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -27,10 +27,6 @@ romstage-y += fmap.c ramstage-y += fmap.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c smm-y += fmap.c -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/chromeos.c),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c -romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c -endif ifeq ($(MOCK_TPM),1) CFLAGS += -DMOCK_TPM=1

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Patch merged into coreboot/master: ae16d3d AMD: Drop redundant test for CONFIG_RAMTOP
by gerrit＠coreboot.org 03 May '14

03 May '14

the following patch was just integrated into master: commit ae16d3dfbd2eb5bfd0cbaa8b63c16e35ee39261d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 30 01:37:58 2014 +0300 AMD: Drop redundant test for CONFIG_RAMTOP Same test is already done in x86/mtrr.h. Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5620 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5620 for details. -gerrit

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Patch merged into coreboot/master: f771e56 Drop useless mainboard-romstage defines
by gerrit＠coreboot.org 03 May '14

03 May '14

the following patch was just integrated into master: commit f771e569d72d6b7166ca0d92afaaf2e635a9ba1c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 3 09:12:55 2014 +0200 Drop useless mainboard-romstage defines Some src/mainboard/*/*/romstage.c files use defines which later modify the behaviour of included .c files. Since it's a pain to work out what is affected by these, drop values that are only defined in the board but never used, or defined to identical values as in spd.h (and use that one instead). Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5639 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5639 for details. -gerrit

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New patch to review for coreboot: e61acff Drop useless mainboard-romstage defines
by Patrick Georgi 03 May '14

03 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5639 -gerrit commit e61acff7500accfe2f5e20b5f7cc418e3c7ac8f6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 3 09:12:55 2014 +0200 Drop useless mainboard-romstage defines Some src/mainboard/*/*/romstage.c files use defines which later modify the behaviour of included .c files. Since it's a pain to work out what is affected by these, drop values that are only defined in the board but never used, or defined to identical values as in spd.h (and use that one instead). Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/amd/bimini_fam10/romstage.c | 3 --- src/mainboard/amd/dbm690t/romstage.c | 5 ----- src/mainboard/amd/mahogany/romstage.c | 5 ----- src/mainboard/asrock/939a785gmh/romstage.c | 5 ----- src/mainboard/kontron/kt690/romstage.c | 5 ----- src/mainboard/siemens/sitemp_g1p1/romstage.c | 10 +--------- src/mainboard/supermicro/h8scm_fam10/romstage.c | 9 --------- src/mainboard/technexion/tim5690/romstage.c | 5 ----- src/mainboard/technexion/tim8690/romstage.c | 5 ----- 9 files changed, 1 insertion(+), 51 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 9f930e8..5c5b44f 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -67,9 +67,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..7a0c8f9 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index b77d4b5..93870c5 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index ce0a6ac..417f9a7 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -18,11 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 4e45dc4..24cae41 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -18,11 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..6ae4989 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -19,15 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 - -#define ICS951462_ADDRESS 0x69 -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -36,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index e6ce5a8..216e5df 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -68,15 +68,6 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..e6483c0 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..2f3ad71 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define SMBUS_HUB 0x71 - #include <stdint.h> #include <string.h> #include <device/pci_def.h>

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New patch to review for coreboot: d5d7202 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
by Trevor Mosey 03 May '14

03 May '14

Trevor Mosey (uberushaximus(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5638 -gerrit commit d5d720211baf79aa4f36d74983422211f8401567 Author: Trevor Mosey <uberushaximus(a)gmail.com> Date: Fri May 2 20:07:03 2014 -0500 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String The Linux thinkpad_acpi.c driver looks for this string while reading information about the system it is running on. This commit does not make the module load but it is one of several things that the module looks for on a ThinkPad. Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845 Signed-off-by: Trevor Mosey <uberushaximus(a)gmail.com> --- src/mainboard/lenovo/t60/mainboard.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 623031a..a25c92c 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -33,6 +33,7 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, @@ -78,9 +79,24 @@ static void mainboard_init(device_t dev) ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); } +static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + const char *oem_strings[] = { + tpec, + }; + + h8_build_id_and_function_spec_version(tpec + 35, 17); + len = smbios_write_type11(current, (*handle)++, oem_strings, ARRAY_SIZE(oem_strings)); + + return len; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; } struct chip_operations mainboard_ops = {

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coreboot-gerrit May 2014