coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8b6f623 EC
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5323 -gerrit commit 8b6f6235dc42c3a7e2be8fff6201e601d926bdc0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 20:24:21 2014 +0100 EC Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi/ec.asl | 218 ++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/apple/macbook21/dsdt.asl | 1 - 3 files changed, 220 insertions(+), 4 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index e69de29..01bfb0c 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -0,0 +1,218 @@ +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + HPAC, 1, + Offset(0x02), + WKLD, 1, /* Lid wake */ + + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, + } + Field(ERAM, ByteAcc, Lock, Preserve) + { + Offset(0x24), + SBDW, 16, + } + + Method(SBPC, 0, NotSerialized) + { + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } + } + + Method(SBRW, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) + } + + Method(SBRB, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) + } + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_INI, 0, NotSerialized) + { + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } + + Device(BAT0) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } + } +} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 3a740e0..d7814f4 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -57,9 +57,8 @@ chip northbridge/intel/i945 # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "1" - register "gpi8_routing" = "2" + register "gpi1_routing" = "2" + register "gpi7_routing" = "2" register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index e654d20..5ba7b09 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ -#define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0

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Patch set updated for coreboot: 3f13621 A new port apple/macbook21.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5321 -gerrit commit 3f136213b6b16ac0178e097307f8e55f3d430b4b Author: Mono <mono(a)posteo.de> Date: Sun Mar 2 18:40:36 2014 +0100 A new port apple/macbook21. Current problems: - Complete lack of EC support (no battery indicator, no temperature, ...) - No audio support Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/apple/Kconfig | 19 + src/mainboard/apple/macbook21/Kconfig | 61 +++ src/mainboard/apple/macbook21/Makefile.inc | 19 + src/mainboard/apple/macbook21/acpi/ec.asl | 0 src/mainboard/apple/macbook21/acpi/gpe.asl | 0 .../apple/macbook21/acpi/i945_pci_irqs.asl | 71 ++++ .../apple/macbook21/acpi/ich7_pci_irqs.asl | 74 ++++ src/mainboard/apple/macbook21/acpi/mainboard.asl | 0 src/mainboard/apple/macbook21/acpi/platform.asl | 192 ++++++++++ src/mainboard/apple/macbook21/acpi/superio.asl | 0 src/mainboard/apple/macbook21/acpi/video.asl | 53 +++ src/mainboard/apple/macbook21/acpi_tables.c | 271 ++++++++++++++ src/mainboard/apple/macbook21/board_info.txt | 6 + src/mainboard/apple/macbook21/cmos.default | 21 ++ src/mainboard/apple/macbook21/cmos.layout | 162 ++++++++ src/mainboard/apple/macbook21/devicetree.cb | 108 ++++++ src/mainboard/apple/macbook21/dsdt.asl | 58 +++ src/mainboard/apple/macbook21/fadt.c | 158 ++++++++ src/mainboard/apple/macbook21/irq_tables.c | 61 +++ src/mainboard/apple/macbook21/mainboard.c | 94 +++++ src/mainboard/apple/macbook21/mptable.c | 76 ++++ src/mainboard/apple/macbook21/romstage.c | 414 +++++++++++++++++++++ src/mainboard/apple/macbook21/smi.h | 23 ++ src/mainboard/apple/macbook21/smihandler.c | 91 +++++ 25 files changed, 2035 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index d823b22..0c60cc9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -18,6 +18,8 @@ config VENDOR_AMD bool "AMD" config VENDOR_AOPEN bool "AOpen" +config VENDOR_APPLE + bool "Apple" config VENDOR_ARIMA bool "Arima" config VENDOR_ARTECGROUP @@ -153,6 +155,7 @@ source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" source "src/mainboard/aopen/Kconfig" +source "src/mainboard/apple/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" diff --git a/src/mainboard/apple/Kconfig b/src/mainboard/apple/Kconfig new file mode 100644 index 0000000..037c79a --- /dev/null +++ b/src/mainboard/apple/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_APPLE + +choice + prompt "Mainboard model" + +config BOARD_APPLE_MACBOOK21 + bool "Macbook2,1 ICH7 TESTING" + help + Testing coreboot port for Macbook2,1 + +endchoice + +source "src/mainboard/apple/macbook21/Kconfig" + +config MAINBOARD_VENDOR + string + default "Apple" + +endif # VENDOR_APPLE diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig new file mode 100644 index 0000000..56c61e9 --- /dev/null +++ b/src/mainboard/apple/macbook21/Kconfig @@ -0,0 +1,61 @@ +if BOARD_APPLE_MACBOOK21 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MFCPGA478 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select GFXUMA + select BOARD_ROMSIZE_KB_2048 + select CHANNEL_XOR_RANDOMIZATION + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select USE_OPTION_TABLE + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_EDID + select EARLY_CBMEM_INIT + select INTEL_EDID + +config MAINBOARD_DIR + string + default apple/macbook21 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "MacBook2,1" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Apple Inc." + +config SEABIOS_PS2_TIMEOUT + int + default 3000 + +endif diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc new file mode 100644 index 0000000..1ba662e --- /dev/null +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/gpe.asl b/src/mainboard/apple/macbook21/acpi/gpe.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..6047def --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001FFFF, 0, 0, 0x10 }, + Package() { 0x0002FFFF, 0, 0, 0x10 }, + Package() { 0x0007FFFF, 0, 0, 0x10 }, + Package() { 0x001BFFFF, 0, 0, 0x16 }, + Package() { 0x001CFFFF, 0, 0, 0x11 }, + Package() { 0x001CFFFF, 1, 0, 0x10 }, + Package() { 0x001CFFFF, 2, 0, 0x12 }, + Package() { 0x001CFFFF, 3, 0, 0x13 }, + Package() { 0x001DFFFF, 0, 0, 0x15 }, + Package() { 0x001DFFFF, 1, 0, 0x13 }, + Package() { 0x001DFFFF, 2, 0, 0x12 }, + Package() { 0x001DFFFF, 3, 0, 0x10 }, + Package() { 0x001EFFFF, 0, 0, 0x16 }, + Package() { 0x001EFFFF, 1, 0, 0x14 }, + Package() { 0x001FFFFF, 0, 0, 0x12 }, + Package() { 0x001FFFFF, 1, 0, 0x13 }, + Package() { 0x001FFFFF, 3, 0, 0x10 } + }) + } Else { + Return (Package() { + Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + } +} diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..5354901 --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} diff --git a/src/mainboard/apple/macbook21/acpi/mainboard.asl b/src/mainboard/apple/macbook21/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl new file mode 100644 index 0000000..1c6ac6e --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} + diff --git a/src/mainboard/apple/macbook21/acpi/superio.asl b/src/mainboard/apple/macbook21/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl new file mode 100644 index 0000000..50a0947 --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/video.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) + { + Offset (0xf4), + BRTC, 8 + } + + Method(BRTD, 0, NotSerialized) + { + Store(BRTC, Local0) + if (LGreater (Local0, 15)) + { + Subtract(Local0, 16, Local0) + Store(Local0, BRTC) + } + } + + Method(BRTU, 0, NotSerialized) + { + Store (BRTC, Local0) + if (LLess(Local0, 0xff)) + { + Add (Local0, 16, Local0) + Store(Local0, BRTC) + } + } +} diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c new file mode 100644 index 0000000..f6ed4ae --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -0,0 +1,271 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + void *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x0000052f Moved GDT + * 0x00000530 - 0x00000b64 coreboot table + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + + /* Enable Dummy DCC ON# for DVI */ + printk(BIOS_DEBUG, "Laptop handling...\n"); + outb(inb(0x60f) & ~(1 << 5), 0x60f); + + return current; +} diff --git a/src/mainboard/apple/macbook21/board_info.txt b/src/mainboard/apple/macbook21/board_info.txt new file mode 100644 index 0000000..b620278 --- /dev/null +++ b/src/mainboard/apple/macbook21/board_info.txt @@ -0,0 +1,6 @@ +Board name: Macbook2,1 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default new file mode 100644 index 0000000..0185e94 --- /dev/null +++ b/src/mainboard/apple/macbook21/cmos.default @@ -0,0 +1,21 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +boot_default=0x40 +cmos_defaults_loaded=Yes +lpt=Enable +volume=0x3 +tft_brightness=0xff +first_battery=Primary +bluetooth=Enable +wlan=Enable +wwan=Enable +trackpoint=Enable +fn_ctrl_swap=Disable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout new file mode 100644 index 0000000..469371e --- /dev/null +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -0,0 +1,162 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 h 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +1064 8 h 0 volume +1072 8 h 0 tft_brightness +1080 1 e 9 first_battery +1081 1 e 1 bluetooth +1082 1 e 1 wwan +1083 1 e 1 wlan +1084 1 e 1 trackpoint +1085 1 e 1 fn_ctrl_swap +1086 1 e 1 sticky_fn +1087 1 e 1 power_management_beeps +1088 1 e 1 low_battery_beep +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb new file mode 100644 index 0000000..3a740e0 --- /dev/null +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -0,0 +1,108 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_is_dual_channel" = "0" + register "gpu_backlight" = "0x1280128" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x8086 0x7270 + end + device pci 02.0 on # VGA controller + subsystemid 0x8086 0x7270 + end + device pci 02.1 on # display controller + subsystemid 0x17aa 0x201a + end + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + register "gpi12_routing" = "1" + register "gpi8_routing" = "2" + + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x04" + + register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" + + register "ide_enable_primary" = "1" + register "ide_enable_secondary" = "1" + + register "c4onc3_enable" = "1" + device pci 1b.0 on # Audio Cnotroller + subsystemid 0x17aa 0x2010 + end + device pci 1c.0 on end # Ethernet + device pci 1c.1 on end # Atheros WLAN + device pci 1d.0 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.1 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.2 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.3 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.7 on # USB2 EHCI + subsystemid 0x8086 0x7270 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.1 on # IDE + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 + end + end + end +end diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl new file mode 100644 index 0000000..e654d20 --- /dev/null +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 28 +#define BRIGHTNESS_UP \DSPC.BRTU +#define BRIGHTNESS_DOWN \DSPC.BRTD +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/apple/macbook21/fadt.c b/src/mainboard/apple/macbook21/fadt.c new file mode 100644 index 0000000..06b0346 --- /dev/null +++ b/src/mainboard/apple/macbook21/fadt.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x23; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/apple/macbook21/irq_tables.c b/src/mainboard/apple/macbook21/irq_tables.c new file mode 100644 index 0000000..8991d7f --- /dev/null +++ b/src/mainboard/apple/macbook21/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 15, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf5, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ + {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ + {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ + {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ + {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ + {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ + {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ + {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ + {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ + {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ + {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ + {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ + {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c new file mode 100644 index 0000000..a136a4c --- /dev/null +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <x86emu/x86emu.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, + unsigned int gfx); + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(void) +{ + /* The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = PANEL; + break; + case 0x5f40: /* Boot Panel Type */ + X86_AX = 0x005f; // Success + X86_CL = 3; + printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL); + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} + +static void mainboard_init(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c new file mode 100644 index 0000000..cc97e52 --- /dev/null +++ b/src/mainboard/apple/macbook21/mptable.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ + + mptable_lintsrc(mc, isa_bus); + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c new file mode 100644 index 0000000..e7ff902 --- /dev/null +++ b/src/mainboard/apple/macbook21/romstage.c @@ -0,0 +1,414 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <cbmem.h> +#include <timestamp.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + /* X60 GPIO: + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ + + outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // I/O Decode Ranges + // X60: 0x0210 == 00000010 00010000 + // Macbook21: 0x0010 == 00000000 00010000 + // Bit 9:8 LPT Decode Range. This field determines which range to + // decode for the LPT Port. + // 00 = 378h 37Fh and 778h 77Fh + // 10 = 3BCh 3BEh and 7BCh 7BEh + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + // LPC_EN--LPC I/F Enables Register + // X60: 0x1f0d == 00011111 00001101 + // Macbook21: 0x3807 == 00111000 00000111 + // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + // to the LPC interface. This range is used for + // Super I/O devices. + // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 62h and 66h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 60h and 64h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 208h to 20Fh + // to the LPC interface. This range is used for a gameport. + // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 200h to 207h + // to the LPC interface. This range is used for a gameport. + // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + // 0 = Disable. + // 1 = Enables the decoding of the FDD range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 12). + // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + // 0 = Disable. + // 1 = Enables the decoding of the LPT range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 9:8). + // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMB range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 6:4). + // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMA range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 3:2). + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); + + /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ + // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + // Bit 31:24 Reserved. + // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + // bit position indicates that any value in the corresponding + // address bit in a received cycle will be treated as a + // match. The corresponding bit in the Address field, below, + // is ignored. The mask is only provided for the lower 6 bits + // of the DWord address, allowing for decoding blocks up to + // 256 bytes in size. + // Bit 17:16 Reserved. + // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + // address is aligned on a 128-byte boundary, and must have + // address lines 31:16 as 0. NOTE: The Intel ICH7 does not + // provide decode down to the word or byte level. + // Bit 1 Reserved. + // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + // 0 = Disable. + // 1 = Enable the GEN1 I/O range to be forwarded to the LPC + // I/F + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); + + /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ + // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + + /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ + // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + // Macbook21: 0x0000 0x0000 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + + /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ + // X60: 0x0000 0x0000 + // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); +} + +static void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + RCBA32(0x3108) = 0x10004321; + + /* PCIe Interrupts */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0232; + RCBA16(0x3142) = 0x3246; + RCBA16(0x3144) = 0x0235; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x3216; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + // RCBA32(0x1e84) = 0x00020001; + // RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; + + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + while (1) + asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_mode, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if !CONFIG_HAVE_ACPI_RESUME +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEBUG_RAM_SETUP + sdram_dump_mchbar_registers(); + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif +#endif +#endif + + MCHBAR16(SSKPD) = 0xCAFE; + + cbmem_was_initted = !cbmem_recovery(boot_mode==2); + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, + SKPAD_ACPI_S3_MAGIC); + } +#endif + + timestamp_add_now(TS_END_ROMSTAGE); + +} diff --git a/src/mainboard/apple/macbook21/smi.h b/src/mainboard/apple/macbook21/smi.h new file mode 100644 index 0000000..92186bf --- /dev/null +++ b/src/mainboard/apple/macbook21/smi.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_APPLE_MACBOOK21_SMI_H +#define MAINBOARD_APPLE_MACBOOK21_SMI_H + +#endif diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c new file mode 100644 index 0000000..0b3d615 --- /dev/null +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include "smi.h" + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +}

1 0

Patch set updated for coreboot: 7426f36 apple/macbook21: Fix audio.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5324 -gerrit commit 7426f3631342e38d7685da896f34d0bfa6ab6a65 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Mar 3 00:44:38 2014 +0100 apple/macbook21: Fix audio. Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/devicetree.cb | 2 +- src/mainboard/apple/macbook21/hda_verb.h | 93 +++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/mainboard.c | 7 ++- 3 files changed, 99 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index d7814f4..66e5fa4 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -71,7 +71,7 @@ chip northbridge/intel/i945 register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller - subsystemid 0x17aa 0x2010 + subsystemid 0x8384 0x7680 end device pci 1c.0 on end # Ethernet device pci 1c.1 on end # Atheros WLAN diff --git a/src/mainboard/apple/macbook21/hda_verb.h b/src/mainboard/apple/macbook21/hda_verb.h new file mode 100644 index 0000000..4e1687d --- /dev/null +++ b/src/mainboard/apple/macbook21/hda_verb.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ + 0x106b2200, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + 0x00172000, + 0x00172122, + 0x0017226B, + 0x00172310, + + /* NID 0x0A. */ + 0x00A71C1F, + 0x00A71DE2, + 0x00A71E21, + 0x00A71F03, + + /* NID 0x0B. */ + 0x00B71C2E, + 0x00B71DE0, + 0x00B71EA1, + 0x00B71F03, + + /* NID 0x0C. */ + 0x00C71C10, + 0x00C71DE1, + 0x00C71E17, + 0x00C71F90, + + /* NID 0x0D. */ + 0x00D71C1F, + 0x00D71DE1, + 0x00D71E17, + 0x00D71F90, + + /* NID 0x0E. */ + 0x00E71CFE, + 0x00E71D00, + 0x00E71E00, + 0x00E71F40, + + /* NID 0x0F */ + 0x00F71C20, + 0x00F71DE0, + 0x00F71E81, + 0x00F71F03, + + /* NID 0x10 */ + 0x01071C30, + 0x01071DE2, + 0x01071E45, + 0x01071F13, + + /* NID 0x11 */ + 0x01171C40, + 0x01171DE2, + 0x01171EC5, + 0x01171F13, + + /* NID 0x15 */ + 0x01571CFC, + 0x01571D00, + 0x01571E00, + 0x01571F40, + + /* NID 0x1B. */ + 0x01B71CFB, + 0x01B71D00, + 0x01B71E00, + 0x01B71F40, + +}; diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index a136a4c..9a025dd 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -34,10 +34,11 @@ #include <arch/x86/include/arch/acpigen.h> #include <smbios.h> #include <x86emu/x86emu.h> +#include "hda_verb.h" #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(void) @@ -86,6 +87,8 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: 58962c3 EC
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5323 -gerrit commit 58962c38eaede569aa71622ad91f058b4dd5eb3f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 20:24:21 2014 +0100 EC Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi/ec.asl | 218 ++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/apple/macbook21/dsdt.asl | 1 - 3 files changed, 220 insertions(+), 4 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index e69de29..01bfb0c 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -0,0 +1,218 @@ +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + HPAC, 1, + Offset(0x02), + WKLD, 1, /* Lid wake */ + + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, + } + Field(ERAM, ByteAcc, Lock, Preserve) + { + Offset(0x24), + SBDW, 16, + } + + Method(SBPC, 0, NotSerialized) + { + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } + } + + Method(SBRW, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) + } + + Method(SBRB, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) + } + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_INI, 0, NotSerialized) + { + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } + + Device(BAT0) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } + } +} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 0876543..2141819 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -57,9 +57,8 @@ chip northbridge/intel/i945 # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "1" - register "gpi8_routing" = "2" + register "gpi1_routing" = "2" + register "gpi7_routing" = "2" register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index e654d20..5ba7b09 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ -#define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0

1 0

Patch set updated for coreboot: 15630f5 smbios: Supply tag type 2 (base board information)
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5322 -gerrit commit 15630f5982f16aa8841e977270b858de913a2a1c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 19:14:44 2014 +0100 smbios: Supply tag type 2 (base board information) Information really contained in it is mostly the same as in type 1 tag. However Linux uses type 2 to match hardware. Duplicate the info. Change-Id: I75e13d764464053ecab4a833fbb83836cedf26e6 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/smbios.c | 19 +++++++++++++++++++ src/include/smbios.h | 12 ++++++++++++ 2 files changed, 31 insertions(+) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..0e84acc 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -217,6 +217,24 @@ static int smbios_write_type1(unsigned long *current, int handle) return len; } +static int smbios_write_type2(unsigned long *current, int handle) +{ + struct smbios_type2 *t = (struct smbios_type2 *)*current; + int len = sizeof(struct smbios_type2); + + memset(t, 0, sizeof(struct smbios_type2)); + t->type = SMBIOS_BOARD_INFORMATION; + t->handle = handle; + t->length = len - 2; + t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer()); + t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); + t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); + t->version = smbios_add_string(t->eos, smbios_mainboard_version()); + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + static int smbios_write_type3(unsigned long *current, int handle) { struct smbios_type3 *t = (struct smbios_type3 *)*current; @@ -372,6 +390,7 @@ unsigned long smbios_write_tables(unsigned long current) tables = current; len = smbios_write_type0(&current, handle++); len += smbios_write_type1(&current, handle++); + len += smbios_write_type2(&current, handle++); len += smbios_write_type3(&current, handle++); len += smbios_write_type4(&current, handle++); #if CONFIG_ELOG diff --git a/src/include/smbios.h b/src/include/smbios.h index 42c5d2d..0ab074d 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -37,6 +37,7 @@ void smbios_mainboard_set_uuid(u8 *uuid); typedef enum { SMBIOS_BIOS_INFORMATION=0, SMBIOS_SYSTEM_INFORMATION=1, + SMBIOS_BOARD_INFORMATION=2, SMBIOS_SYSTEM_ENCLOSURE=3, SMBIOS_PROCESSOR_INFORMATION=4, SMBIOS_CACHE_INFORMATION=7, @@ -102,6 +103,17 @@ struct smbios_type1 { char eos[2]; } __attribute__((packed)); +struct smbios_type2 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + char eos[2]; +} __attribute__((packed)); + struct smbios_type3 { u8 type; u8 length;

1 0

Patch set updated for coreboot: 87b8485 A new port apple/macbook21.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5321 -gerrit commit 87b8485961661d2124c438fa57c6eafa224bb433 Author: Mono <mono(a)posteo.de> Date: Sun Mar 2 18:40:36 2014 +0100 A new port apple/macbook21. Current problems: - Complete lack of EC support (no battery indicator, no temperature, ...) - No audio support Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/apple/Kconfig | 19 + src/mainboard/apple/macbook21/Kconfig | 61 +++ src/mainboard/apple/macbook21/Makefile.inc | 19 + src/mainboard/apple/macbook21/acpi/ec.asl | 0 src/mainboard/apple/macbook21/acpi/gpe.asl | 0 .../apple/macbook21/acpi/i945_pci_irqs.asl | 71 ++++ .../apple/macbook21/acpi/ich7_pci_irqs.asl | 74 ++++ src/mainboard/apple/macbook21/acpi/mainboard.asl | 0 src/mainboard/apple/macbook21/acpi/platform.asl | 192 ++++++++++ src/mainboard/apple/macbook21/acpi/superio.asl | 0 src/mainboard/apple/macbook21/acpi/video.asl | 53 +++ src/mainboard/apple/macbook21/acpi_tables.c | 271 ++++++++++++++ src/mainboard/apple/macbook21/board_info.txt | 6 + src/mainboard/apple/macbook21/cmos.default | 21 ++ src/mainboard/apple/macbook21/cmos.layout | 162 ++++++++ src/mainboard/apple/macbook21/devicetree.cb | 105 ++++++ src/mainboard/apple/macbook21/dsdt.asl | 58 +++ src/mainboard/apple/macbook21/fadt.c | 158 ++++++++ src/mainboard/apple/macbook21/irq_tables.c | 61 +++ src/mainboard/apple/macbook21/mainboard.c | 94 +++++ src/mainboard/apple/macbook21/mptable.c | 76 ++++ src/mainboard/apple/macbook21/romstage.c | 414 +++++++++++++++++++++ src/mainboard/apple/macbook21/smi.h | 23 ++ src/mainboard/apple/macbook21/smihandler.c | 91 +++++ 25 files changed, 2032 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index d823b22..0c60cc9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -18,6 +18,8 @@ config VENDOR_AMD bool "AMD" config VENDOR_AOPEN bool "AOpen" +config VENDOR_APPLE + bool "Apple" config VENDOR_ARIMA bool "Arima" config VENDOR_ARTECGROUP @@ -153,6 +155,7 @@ source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" source "src/mainboard/aopen/Kconfig" +source "src/mainboard/apple/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" diff --git a/src/mainboard/apple/Kconfig b/src/mainboard/apple/Kconfig new file mode 100644 index 0000000..037c79a --- /dev/null +++ b/src/mainboard/apple/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_APPLE + +choice + prompt "Mainboard model" + +config BOARD_APPLE_MACBOOK21 + bool "Macbook2,1 ICH7 TESTING" + help + Testing coreboot port for Macbook2,1 + +endchoice + +source "src/mainboard/apple/macbook21/Kconfig" + +config MAINBOARD_VENDOR + string + default "Apple" + +endif # VENDOR_APPLE diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig new file mode 100644 index 0000000..56c61e9 --- /dev/null +++ b/src/mainboard/apple/macbook21/Kconfig @@ -0,0 +1,61 @@ +if BOARD_APPLE_MACBOOK21 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MFCPGA478 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select GFXUMA + select BOARD_ROMSIZE_KB_2048 + select CHANNEL_XOR_RANDOMIZATION + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select USE_OPTION_TABLE + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_EDID + select EARLY_CBMEM_INIT + select INTEL_EDID + +config MAINBOARD_DIR + string + default apple/macbook21 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "MacBook2,1" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Apple Inc." + +config SEABIOS_PS2_TIMEOUT + int + default 3000 + +endif diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc new file mode 100644 index 0000000..1ba662e --- /dev/null +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/gpe.asl b/src/mainboard/apple/macbook21/acpi/gpe.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..6047def --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001FFFF, 0, 0, 0x10 }, + Package() { 0x0002FFFF, 0, 0, 0x10 }, + Package() { 0x0007FFFF, 0, 0, 0x10 }, + Package() { 0x001BFFFF, 0, 0, 0x16 }, + Package() { 0x001CFFFF, 0, 0, 0x11 }, + Package() { 0x001CFFFF, 1, 0, 0x10 }, + Package() { 0x001CFFFF, 2, 0, 0x12 }, + Package() { 0x001CFFFF, 3, 0, 0x13 }, + Package() { 0x001DFFFF, 0, 0, 0x15 }, + Package() { 0x001DFFFF, 1, 0, 0x13 }, + Package() { 0x001DFFFF, 2, 0, 0x12 }, + Package() { 0x001DFFFF, 3, 0, 0x10 }, + Package() { 0x001EFFFF, 0, 0, 0x16 }, + Package() { 0x001EFFFF, 1, 0, 0x14 }, + Package() { 0x001FFFFF, 0, 0, 0x12 }, + Package() { 0x001FFFFF, 1, 0, 0x13 }, + Package() { 0x001FFFFF, 3, 0, 0x10 } + }) + } Else { + Return (Package() { + Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + } +} diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..5354901 --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} diff --git a/src/mainboard/apple/macbook21/acpi/mainboard.asl b/src/mainboard/apple/macbook21/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl new file mode 100644 index 0000000..1c6ac6e --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} + diff --git a/src/mainboard/apple/macbook21/acpi/superio.asl b/src/mainboard/apple/macbook21/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl new file mode 100644 index 0000000..50a0947 --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi/video.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) + { + Offset (0xf4), + BRTC, 8 + } + + Method(BRTD, 0, NotSerialized) + { + Store(BRTC, Local0) + if (LGreater (Local0, 15)) + { + Subtract(Local0, 16, Local0) + Store(Local0, BRTC) + } + } + + Method(BRTU, 0, NotSerialized) + { + Store (BRTC, Local0) + if (LLess(Local0, 0xff)) + { + Add (Local0, 16, Local0) + Store(Local0, BRTC) + } + } +} diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c new file mode 100644 index 0000000..f6ed4ae --- /dev/null +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -0,0 +1,271 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + void *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x0000052f Moved GDT + * 0x00000530 - 0x00000b64 coreboot table + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + + /* Enable Dummy DCC ON# for DVI */ + printk(BIOS_DEBUG, "Laptop handling...\n"); + outb(inb(0x60f) & ~(1 << 5), 0x60f); + + return current; +} diff --git a/src/mainboard/apple/macbook21/board_info.txt b/src/mainboard/apple/macbook21/board_info.txt new file mode 100644 index 0000000..b620278 --- /dev/null +++ b/src/mainboard/apple/macbook21/board_info.txt @@ -0,0 +1,6 @@ +Board name: Macbook2,1 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default new file mode 100644 index 0000000..0185e94 --- /dev/null +++ b/src/mainboard/apple/macbook21/cmos.default @@ -0,0 +1,21 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +boot_default=0x40 +cmos_defaults_loaded=Yes +lpt=Enable +volume=0x3 +tft_brightness=0xff +first_battery=Primary +bluetooth=Enable +wlan=Enable +wwan=Enable +trackpoint=Enable +fn_ctrl_swap=Disable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout new file mode 100644 index 0000000..469371e --- /dev/null +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -0,0 +1,162 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 h 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +1064 8 h 0 volume +1072 8 h 0 tft_brightness +1080 1 e 9 first_battery +1081 1 e 1 bluetooth +1082 1 e 1 wwan +1083 1 e 1 wlan +1084 1 e 1 trackpoint +1085 1 e 1 fn_ctrl_swap +1086 1 e 1 sticky_fn +1087 1 e 1 power_management_beeps +1088 1 e 1 low_battery_beep +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb new file mode 100644 index 0000000..0876543 --- /dev/null +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_is_dual_channel" = "0" + register "gpu_backlight" = "0x1280128" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x8086 0x7270 + end + device pci 02.0 on # VGA controller + subsystemid 0x8086 0x7270 + end + device pci 02.1 on # display controller + subsystemid 0x17aa 0x201a + end + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + register "gpi12_routing" = "1" + register "gpi8_routing" = "2" + + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x04" + + register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" + device pci 1b.0 on # Audio Cnotroller + subsystemid 0x17aa 0x2010 + end + device pci 1c.0 on end # Ethernet + device pci 1c.1 on end # Atheros WLAN + device pci 1d.0 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.1 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.2 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.3 on # USB UHCI + subsystemid 0x8086 0x7270 + end + device pci 1d.7 on # USB2 EHCI + subsystemid 0x8086 0x7270 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.1 on # IDE + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 + end + end + end +end diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl new file mode 100644 index 0000000..e654d20 --- /dev/null +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 28 +#define BRIGHTNESS_UP \DSPC.BRTU +#define BRIGHTNESS_DOWN \DSPC.BRTD +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/apple/macbook21/fadt.c b/src/mainboard/apple/macbook21/fadt.c new file mode 100644 index 0000000..06b0346 --- /dev/null +++ b/src/mainboard/apple/macbook21/fadt.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x23; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/apple/macbook21/irq_tables.c b/src/mainboard/apple/macbook21/irq_tables.c new file mode 100644 index 0000000..8991d7f --- /dev/null +++ b/src/mainboard/apple/macbook21/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 15, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf5, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ + {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ + {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ + {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ + {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ + {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ + {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ + {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ + {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ + {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ + {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ + {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ + {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c new file mode 100644 index 0000000..a136a4c --- /dev/null +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <x86emu/x86emu.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, + unsigned int gfx); + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(void) +{ + /* The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = PANEL; + break; + case 0x5f40: /* Boot Panel Type */ + X86_AX = 0x005f; // Success + X86_CL = 3; + printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL); + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} + +static void mainboard_init(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c new file mode 100644 index 0000000..cc97e52 --- /dev/null +++ b/src/mainboard/apple/macbook21/mptable.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ + + mptable_lintsrc(mc, isa_bus); + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c new file mode 100644 index 0000000..e7ff902 --- /dev/null +++ b/src/mainboard/apple/macbook21/romstage.c @@ -0,0 +1,414 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <cbmem.h> +#include <timestamp.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + /* X60 GPIO: + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ + + outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // I/O Decode Ranges + // X60: 0x0210 == 00000010 00010000 + // Macbook21: 0x0010 == 00000000 00010000 + // Bit 9:8 LPT Decode Range. This field determines which range to + // decode for the LPT Port. + // 00 = 378h 37Fh and 778h 77Fh + // 10 = 3BCh 3BEh and 7BCh 7BEh + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + // LPC_EN--LPC I/F Enables Register + // X60: 0x1f0d == 00011111 00001101 + // Macbook21: 0x3807 == 00111000 00000111 + // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + // to the LPC interface. This range is used for + // Super I/O devices. + // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 62h and 66h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 60h and 64h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 208h to 20Fh + // to the LPC interface. This range is used for a gameport. + // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 200h to 207h + // to the LPC interface. This range is used for a gameport. + // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + // 0 = Disable. + // 1 = Enables the decoding of the FDD range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 12). + // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + // 0 = Disable. + // 1 = Enables the decoding of the LPT range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 9:8). + // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMB range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 6:4). + // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMA range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 3:2). + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); + + /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ + // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + // Bit 31:24 Reserved. + // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + // bit position indicates that any value in the corresponding + // address bit in a received cycle will be treated as a + // match. The corresponding bit in the Address field, below, + // is ignored. The mask is only provided for the lower 6 bits + // of the DWord address, allowing for decoding blocks up to + // 256 bytes in size. + // Bit 17:16 Reserved. + // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + // address is aligned on a 128-byte boundary, and must have + // address lines 31:16 as 0. NOTE: The Intel ICH7 does not + // provide decode down to the word or byte level. + // Bit 1 Reserved. + // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + // 0 = Disable. + // 1 = Enable the GEN1 I/O range to be forwarded to the LPC + // I/F + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); + + /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ + // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + + /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ + // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + // Macbook21: 0x0000 0x0000 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + + /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ + // X60: 0x0000 0x0000 + // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); +} + +static void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + RCBA32(0x3108) = 0x10004321; + + /* PCIe Interrupts */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0232; + RCBA16(0x3142) = 0x3246; + RCBA16(0x3144) = 0x0235; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x3216; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + // RCBA32(0x1e84) = 0x00020001; + // RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; + + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + while (1) + asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_mode, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if !CONFIG_HAVE_ACPI_RESUME +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEBUG_RAM_SETUP + sdram_dump_mchbar_registers(); + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif +#endif +#endif + + MCHBAR16(SSKPD) = 0xCAFE; + + cbmem_was_initted = !cbmem_recovery(boot_mode==2); + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, + SKPAD_ACPI_S3_MAGIC); + } +#endif + + timestamp_add_now(TS_END_ROMSTAGE); + +} diff --git a/src/mainboard/apple/macbook21/smi.h b/src/mainboard/apple/macbook21/smi.h new file mode 100644 index 0000000..92186bf --- /dev/null +++ b/src/mainboard/apple/macbook21/smi.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_APPLE_MACBOOK21_SMI_H +#define MAINBOARD_APPLE_MACBOOK21_SMI_H + +#endif diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c new file mode 100644 index 0000000..0b3d615 --- /dev/null +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include "smi.h" + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +}

1 0

Patch set updated for coreboot: 9fe02ca i945: Replace video gfx init.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5320 -gerrit commit 9fe02cafbe5222c07ed42fb6cc9b0be5be3f5429 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 17:28:20 2014 +0100 i945: Replace video gfx init. Old init was a replay not even meant to have been committed. This one really computes values and does its job. Tested on Macbook2,1 (1280x800). Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/Makefile.inc | 3 - src/mainboard/lenovo/x60/devicetree.cb | 5 + src/mainboard/lenovo/x60/drm_dp_helper.h | 239 -- src/mainboard/lenovo/x60/i915.c | 373 --- src/mainboard/lenovo/x60/i915_reg.h | 3878 ------------------------------ src/mainboard/lenovo/x60/i915io.c | 2273 ----------------- src/mainboard/lenovo/x60/i915io.h | 86 - src/mainboard/lenovo/x60/intel_dp.c | 167 -- src/northbridge/intel/i945/chip.h | 6 + src/northbridge/intel/i945/gma.c | 339 ++- 11 files changed, 345 insertions(+), 7025 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index ecb7ce5..0b01fe4 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -20,6 +20,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c romstage-y += dock.c ramstage-y += dock.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..416c1f8 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,6 +22,11 @@ chip northbridge/intel/i945 + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_is_dual_channel" = "0" + register "gpu_backlight" = "0x1280128" + device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/x60/drm_dp_helper.h b/src/mainboard/lenovo/x60/drm_dp_helper.h deleted file mode 100644 index f2e06c3..0000000 --- a/src/mainboard/lenovo/x60/drm_dp_helper.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -/* From the VESA DisplayPort spec */ - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) - -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) - -/* AUX CH addresses */ -/* DPCD */ -#define DP_DPCD_REV 0x000 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 - -/* link configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_PSR_EN_CFG 0x170 -# define DP_PSR_ENABLE (1 << 0) -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) -# define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_EDP_CONFIGURATION_SET 0x10a - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c deleted file mode 100644 index 4870fd8..0000000 --- a/src/mainboard/lenovo/x60/i915.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <stdlib.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <delay.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> -#include <cbfs_core.h> - -#include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <edid.h> -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; - -#define PGETLB_CTL 0x2020 - -static int verbose = 0; - -static unsigned int *mmio; -static unsigned int graphics; -static unsigned short addrport; -static unsigned short dataport; -static unsigned int physbase; - -#define PGETBL_CTL 0x2020 -#define PGETBL_ENABLED 0x00000001 - - -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; -#define READ32(addr) io_i915_READ32(addr) -#define WRITE32(val, addr) io_i915_WRITE32(val, addr) - -static char *regname(unsigned long addr) -{ - static char name[16]; - snprintf(name, sizeof (name), "0x%lx", addr); - return name; -} - -unsigned long io_i915_READ32(unsigned long addr) -{ - unsigned long val; - outl(addr, addrport); - val = inl(dataport); - if (verbose & vio) - printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); - return val; -} - -void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n", - __func__, start, end, base, inc); - - for (i = start; i < end; i++) { - u32 word = base + i*inc; - WRITE32(word|1, (i*4)|1); - } -} - -int gtt_setup(unsigned int mmiobase); -int gtt_setup(unsigned int mmiobase) -{ - unsigned long PGETBL_save; - - PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; - PGETBL_save |= PGETBL_ENABLED; - - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; - PGETBL_save |= 2; /* set GTT to 256kb */ - - write32(mmiobase + GFX_FLSH_CNTL, 0); - - write32(mmiobase + PGETBL_CTL, PGETBL_save); - - /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); - } else { - printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); - return 1; - } - write32(mmiobase + GFX_FLSH_CNTL, 0); - - return 0; -} - - -static unsigned long tickspermicrosecond = 1795; -static unsigned long long globalstart; - -static unsigned long -microseconds(unsigned long long start, unsigned long long end) -{ - unsigned long ret; - ret = ((end - start)/tickspermicrosecond); - return ret; -} - -static unsigned long globalmicroseconds(void) -{ - return microseconds(globalstart, rdtscll()); -} - -extern struct iodef iodefs[]; -extern int niodefs; - -/* fill the palette. This runs when the P opcode is hit. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for (i = 0; i < 256; i++, color += 0x010101) - io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = 0; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for (i = index, id = &iodefs[i]; id->op; i++, id++) { - switch (id->op) { - case M: - if (verbose & vmsg) - printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr) { - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++) - u = READ32(id->addr); - - if (verbose & vspin) - printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL) { - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: - break; - case 7: - break; - default: - udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", - 100000); - } - } - break; - case V: - if (id->count < 8) { - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", - id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); - -int i915lightup(unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) -{ - static struct edid edid; - - int index; - unsigned long temp; - mmio = (void *)pmmio; - addrport = piobase; - dataport = addrport + 4; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", - (void *)graphics, mmio, addrport, physbase); - globalstart = rdtscll(); - - - decode_edid((unsigned char *)&x60_edid_data, - sizeof(x60_edid_data), &edid); - - htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (edid.ha + edid.hso - 1) | - ((edid.ha + edid.hso + edid.hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); - - vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); - - vsync = (edid.va + edid.vso - 1) | - ((edid.va + edid.vso + edid.vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); - - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); - - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); - - verbose = 0; - /* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * There are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. We will be exploiting this - * trick in a later rev of this code. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - - if (gtt_setup(pmmio)) { - printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); - return 0; - } - - setgtt(0, 800 , physbase, 4096); - - temp = READ32(PGETLB_CTL); - printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); - - if (temp & 1) - printk(BIOS_INFO, "GTT Enabled\n"); - else - printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); - - printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0x00, FRAME_BUFFER_BYTES); - - printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); - - set_vbe_mode_info_valid(&edid, graphics); - - return 0; -} diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h deleted file mode 100644 index 382b822..0000000 --- a/src/mainboard/lenovo/x60/i915_reg.h +++ /dev/null @@ -1,3878 +0,0 @@ -/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _I915_REG_H_ -#define _I915_REG_H_ - -#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) - -/* - * The Bridge device's PCI config space has information about the - * fb aperture size and the amount of pre-reserved memory. - * This is all handled in the intel-gtt.ko module. i915.ko only - * cares about the vga bit for the vga rbiter. - */ -#define INTEL_GMCH_CTRL 0x52 -#define INTEL_GMCH_VGA_DISABLE (1 << 1) - -/* PCI config space */ - -#define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (0xf << 0) -#define GC_CLOCK_133_200 (0 << 0) -#define GC_CLOCK_100_200 (1 << 0) -#define GC_CLOCK_100_133 (2 << 0) -#define GC_CLOCK_166_250 (3 << 0) -#define GCFGC2 0xda -#define GCFGC 0xf0 /* 915+ only */ -#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -#define GC_DISPLAY_CLOCK_MASK (7 << 4) -#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) -#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) -#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) -#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) -#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) -#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) -#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) -#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) -#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) -#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) -#define I945_GC_RENDER_CLOCK_MASK (7 << 0) -#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) -#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) -#define I915_GC_RENDER_CLOCK_MASK (7 << 0) -#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) -#define LBB 0xf4 - -/* Graphics reset regs */ -#define I965_GDRST 0xc0 /* PCI config register */ -#define ILK_GDSR 0x2ca4 /* MCHBAR offset */ -#define GRDOM_FULL (0<<2) -#define GRDOM_RENDER (1<<2) -#define GRDOM_MEDIA (3<<2) - -#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ -#define GEN6_MBC_SNPCR_SHIFT 21 -#define GEN6_MBC_SNPCR_MASK (3<<21) -#define GEN6_MBC_SNPCR_MAX (0<<21) -#define GEN6_MBC_SNPCR_MED (1<<21) -#define GEN6_MBC_SNPCR_LOW (2<<21) -#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ - -#define GEN6_MBCTL 0x0907c -#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) -#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) -#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) -#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) -#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) - -#define GEN6_GDRST 0x941c -#define GEN6_GRDOM_FULL (1 << 0) -#define GEN6_GRDOM_RENDER (1 << 1) -#define GEN6_GRDOM_MEDIA (1 << 2) -#define GEN6_GRDOM_BLT (1 << 3) - -/* PPGTT stuff */ -#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) - -#define GEN6_PDE_VALID (1 << 0) -#define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */ -/* gen6+ has bit 11-4 for physical addr bit 39-32 */ -#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - -#define GEN6_PTE_VALID (1 << 0) -#define GEN6_PTE_UNCACHED (1 << 1) -#define GEN6_PTE_CACHE_LLC (2 << 1) -#define GEN6_PTE_CACHE_LLC_MLC (3 << 1) -#define GEN6_PTE_CACHE_BITS (3 << 1) -#define GEN6_PTE_GFDT (1 << 3) -#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - -#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) -#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) -#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) -#define PP_DIR_DCLV_2G 0xffffffff - -#define GAM_ECOCHK 0x4090 -#define ECOCHK_SNB_BIT (1<<10) -#define ECOCHK_PPGTT_CACHE64B (0x3<<3) -#define ECOCHK_PPGTT_CACHE4B (0x0<<3) - -/* VGA stuff */ - -#define VGA_ST01_MDA 0x3ba -#define VGA_ST01_CGA 0x3da - -#define VGA_MSR_WRITE 0x3c2 -#define VGA_MSR_READ 0x3cc -#define VGA_MSR_MEM_EN (1<<1) -#define VGA_MSR_CGA_MODE (1<<0) - -#define VGA_SR_INDEX 0x3c4 -#define VGA_SR_DATA 0x3c5 - -#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) -#define VGA_AR_DATA_WRITE 0x3c0 -#define VGA_AR_DATA_READ 0x3c1 - -#define VGA_GR_INDEX 0x3ce -#define VGA_GR_DATA 0x3cf -/* GR05 */ -#define VGA_GR_MEM_READ_MODE_SHIFT 3 -#define VGA_GR_MEM_READ_MODE_PLANE 1 -/* GR06 */ -#define VGA_GR_MEM_MODE_MASK 0xc -#define VGA_GR_MEM_MODE_SHIFT 2 -#define VGA_GR_MEM_A0000_AFFFF 0 -#define VGA_GR_MEM_A0000_BFFFF 1 -#define VGA_GR_MEM_B0000_B7FFF 2 -#define VGA_GR_MEM_B0000_BFFFF 3 - -#define VGA_DACMASK 0x3c6 -#define VGA_DACRX 0x3c7 -#define VGA_DACWX 0x3c8 -#define VGA_DACDATA 0x3c9 - -#define VGA_CR_INDEX_MDA 0x3b4 -#define VGA_CR_DATA_MDA 0x3b5 -#define VGA_CR_INDEX_CGA 0x3d4 -#define VGA_CR_DATA_CGA 0x3d5 - -/* - * Memory interface instructions used by the kernel - */ -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) - -#define MI_NOOP MI_INSTR(0, 0) -#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) -#define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ -#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) -#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) -#define MI_REPORT_HEAD MI_INSTR(0x07, 0) -#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON (0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) -#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) -#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) -#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) -#define MI_SET_CONTEXT MI_INSTR(0x18, 0) -#define MI_MM_SPACE_GTT (1<<8) -#define MI_MM_SPACE_PHYSICAL (0<<8) -#define MI_SAVE_EXT_STATE_EN (1<<3) -#define MI_RESTORE_EXT_STATE_EN (1<<2) -#define MI_FORCE_RESTORE (1<<1) -#define MI_RESTORE_INHIBIT (1<<0) -#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ -#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 -/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: - * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw - * simply ignores the register load under certain conditions. - * - One can actually load arbitrary many arbitrary registers: Simply issue x - * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! - */ -#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) -#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) -#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) -#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) -#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ -#define MI_SEMAPHORE_GLOBAL_GTT (1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER (1<<18) -#define MI_SEMAPHORE_SYNC_RV (2<<16) -#define MI_SEMAPHORE_SYNC_RB (0<<16) -#define MI_SEMAPHORE_SYNC_VR (0<<16) -#define MI_SEMAPHORE_SYNC_VB (2<<16) -#define MI_SEMAPHORE_SYNC_BR (2<<16) -#define MI_SEMAPHORE_SYNC_BV (0<<16) -#define MI_SEMAPHORE_SYNC_INVALID (1<<0) -/* - * 3D instructions used by the kernel - */ -#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) - -#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) -#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) -#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) -#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) -#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) -#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) -#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ -#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ -#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) -#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) -#define PIPE_CONTROL_CS_STALL (1<<20) -#define PIPE_CONTROL_QW_WRITE (1<<14) -#define PIPE_CONTROL_DEPTH_STALL (1<<13) -#define PIPE_CONTROL_WRITE_FLUSH (1<<12) -#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ -#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ -#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ -#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_NOTIFY (1<<8) -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ - - -/* - * Reset registers - */ -#define DEBUG_RESET_I830 0x6070 -#define DEBUG_RESET_FULL (1<<7) -#define DEBUG_RESET_RENDER (1<<8) -#define DEBUG_RESET_DISPLAY (1<<9) - - -/* - * Fence registers - */ -#define FENCE_REG_830_0 0x2000 -#define FENCE_REG_945_8 0x3000 -#define I830_FENCE_START_MASK 0x07f80000 -#define I830_FENCE_TILING_Y_SHIFT 12 -#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) -#define I830_FENCE_PITCH_SHIFT 4 -#define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 4 -#define I830_FENCE_MAX_PITCH_VAL 6 -#define I830_FENCE_MAX_SIZE_VAL (1<<8) - -#define I915_FENCE_START_MASK 0x0ff00000 -#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) - -#define FENCE_REG_965_0 0x03000 -#define I965_FENCE_PITCH_SHIFT 2 -#define I965_FENCE_TILING_Y_SHIFT 1 -#define I965_FENCE_REG_VALID (1<<0) -#define I965_FENCE_MAX_PITCH_VAL 0x0400 - -#define FENCE_REG_SANDYBRIDGE_0 0x100000 -#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 - -/* control register for cpu gtt access */ -#define TILECTL 0x101000 -#define TILECTL_SWZCTL (1 << 0) -#define TILECTL_TLB_PREFETCH_DIS (1 << 2) -#define TILECTL_BACKSNOOP_DIS (1 << 3) - -/* - * Instruction and interrupt control regs - */ -#define PGTBL_ER 0x02024 -#define RENDER_RING_BASE 0x02000 -#define BSD_RING_BASE 0x04000 -#define GEN6_BSD_RING_BASE 0x12000 -#define BLT_RING_BASE 0x22000 -#define RING_TAIL(base) ((base)+0x30) -#define RING_HEAD(base) ((base)+0x34) -#define RING_START(base) ((base)+0x38) -#define RING_CTL(base) ((base)+0x3c) -#define RING_SYNC_0(base) ((base)+0x40) -#define RING_SYNC_1(base) ((base)+0x44) -#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) -#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) -#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) -#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) -#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) -#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) -#define RING_MAX_IDLE(base) ((base)+0x54) -#define RING_HWS_PGA(base) ((base)+0x80) -#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) -#define ARB_MODE 0x04030 -#define ARB_MODE_SWIZZLE_SNB (1<<4) -#define ARB_MODE_SWIZZLE_IVB (1<<5) -#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) -#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) -#define RENDER_HWS_PGA_GEN7 (0x04080) -#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) -#define DONE_REG 0x40b0 -#define BSD_HWS_PGA_GEN7 (0x04180) -#define BLT_HWS_PGA_GEN7 (0x04280) -#define RING_ACTHD(base) ((base)+0x74) -#define RING_NOPID(base) ((base)+0x94) -#define RING_IMR(base) ((base)+0xa8) -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ -#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ -#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ -#if 1 -#define PRB0_TAIL 0x02030 -#define PRB0_HEAD 0x02034 -#define PRB0_START 0x02038 -#define PRB0_CTL 0x0203c -#define PRB1_TAIL 0x02040 /* 915+ only */ -#define PRB1_HEAD 0x02044 /* 915+ only */ -#define PRB1_START 0x02048 /* 915+ only */ -#define PRB1_CTL 0x0204c /* 915+ only */ -#endif -#define IPEIR_I965 0x02064 -#define IPEHR_I965 0x02068 -#define INSTDONE_I965 0x0206c -#define RING_IPEIR(base) ((base)+0x64) -#define RING_IPEHR(base) ((base)+0x68) -#define RING_INSTDONE(base) ((base)+0x6c) -#define RING_INSTPS(base) ((base)+0x70) -#define RING_DMA_FADD(base) ((base)+0x78) -#define RING_INSTPM(base) ((base)+0xc0) -#define INSTPS 0x02070 /* 965+ only */ -#define INSTDONE1 0x0207c /* 965+ only */ -#define ACTHD_I965 0x02074 -#define HWS_PGA 0x02080 -#define HWS_ADDRESS_MASK 0xfffff000 -#define HWS_START_ADDRESS_SHIFT 4 -#define PWRCTXA 0x2088 /* 965GM+ only */ -#define PWRCTX_EN (1<<0) -#define IPEIR 0x02088 -#define IPEHR 0x0208c -#define INSTDONE 0x02090 -#define NOPID 0x02094 -#define HWSTAM 0x02098 - -#define ERROR_GEN6 0x040a0 - -/* GM45+ chicken bits -- debug workaround bits that may be required - * for various sorts of correct behavior. The top 16 bits of each are - * the enables for writing to the corresponding low bit. - */ -#define _3D_CHICKEN 0x02084 -#define _3D_CHICKEN2 0x0208c -/* Disables pipelining of read flushes past the SF-WIZ interface. - * Required on all Ironlake steppings according to the B-Spec, but the - * particular danger of not doing so is not specified. - */ -# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) -#define _3D_CHICKEN3 0x02090 - -#define MI_MODE 0x0209c -# define VS_TIMER_DISPATCH (1 << 6) -# define MI_FLUSH_ENABLE (1 << 12) - -#define GFX_MODE 0x02520 -#define GFX_MODE_GEN7 0x0229c -#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) -#define GFX_RUN_LIST_ENABLE (1<<15) -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) -#define GFX_SURFACE_FAULT_ENABLE (1<<12) -#define GFX_REPLAY_MODE (1<<11) -#define GFX_PSMI_GRANULARITY (1<<10) -#define GFX_PPGTT_ENABLE (1<<9) - -#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) -#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) - -#define SCPD0 0x0209c /* 915+ only */ -#define IER 0x020a0 -#define IIR 0x020a4 -#define IMR 0x020a8 -#define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) -#define EIR 0x020b0 -#define EMR 0x020b4 -#define ESR 0x020b8 -#define GM45_ERROR_PAGE_TABLE (1<<5) -#define GM45_ERROR_MEM_PRIV (1<<4) -#define I915_ERROR_PAGE_TABLE (1<<4) -#define GM45_ERROR_CP_PRIV (1<<3) -#define I915_ERROR_MEMORY_REFRESH (1<<1) -#define I915_ERROR_INSTRUCTION (1<<0) -#define INSTPM 0x020c0 -#define INSTPM_SELF_EN (1<<12) /* 915GM only */ -#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts - will not assert AGPBUSY# and will only - be delivered when out of C3. */ -#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ -#define ACTHD 0x020c8 -#define FW_BLC 0x020d8 -#define FW_BLC2 0x020dc -#define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1<<31) -#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ -#define MM_BURST_LENGTH 0x00700000 -#define MM_FIFO_WATERMARK 0x0001F000 -#define LM_BURST_LENGTH 0x00000700 -#define LM_FIFO_WATERMARK 0x0000001F -#define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ - -/* Make render/texture TLB fetches lower priorty than associated data - * fetches. This is not turned on by default - */ -#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) - -/* Isoch request wait on GTT enable (Display A/B/C streams). - * Make isoch requests stall on the TLB update. May cause - * display underruns (test mode only) - */ -#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) - -/* Block grant count for isoch requests when block count is - * set to a finite value. - */ -#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) -#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ -#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ -#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ -#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ - -/* Enable render writes to complete in C2/C3/C4 power states. - * If this isn't enabled, render writes are prevented in low - * power states. That seems bad to me. - */ -#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) - -/* This acknowledges an async flip immediately instead - * of waiting for 2TLB fetches. - */ -#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) - -/* Enables non-sequential data reads through arbiter - */ -#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) - -/* Disable FSB snooping of cacheable write cycles from binner/render - * command stream - */ -#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) - -/* Arbiter time slice for non-isoch streams */ -#define MI_ARB_TIME_SLICE_MASK (7 << 5) -#define MI_ARB_TIME_SLICE_1 (0 << 5) -#define MI_ARB_TIME_SLICE_2 (1 << 5) -#define MI_ARB_TIME_SLICE_4 (2 << 5) -#define MI_ARB_TIME_SLICE_6 (3 << 5) -#define MI_ARB_TIME_SLICE_8 (4 << 5) -#define MI_ARB_TIME_SLICE_10 (5 << 5) -#define MI_ARB_TIME_SLICE_14 (6 << 5) -#define MI_ARB_TIME_SLICE_16 (7 << 5) - -/* Low priority grace period page size */ -#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ -#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) - -/* Disable display A/B trickle feed */ -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) - -/* Set display plane priority */ -#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ -#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ - -#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) -#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) -#define BB_ADDR 0x02140 /* 8 bytes */ -#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ -#define ECOSKPD 0x021d0 -#define ECO_GATING_CX_ONLY (1<<3) -#define ECO_FLIP_DONE (1<<0) - -/* GEN6 interrupt control */ -#define GEN6_RENDER_HWSTAM 0x2098 -#define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) - -#define GEN6_BLITTER_HWSTAM 0x22098 -#define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) - -#define GEN6_BLITTER_ECOSKPD 0x221d0 -#define GEN6_BLITTER_LOCK_SHIFT 16 -#define GEN6_BLITTER_FBC_NOTIFY (1<<3) - -#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) - -#define GEN6_BSD_HWSTAM 0x12098 -#define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) - -#define GEN6_BSD_RNCID 0x12198 - -/* - * Framebuffer compression (915+ only) - */ - -#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ -#define FBC_LL_BASE 0x03204 /* 4k page aligned */ -#define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_C3_IDLE (1<<13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) -#define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) -#define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) -#define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) -#define FBC_FENCE_OFF 0x0321b -#define FBC_TAG 0x03300 - -#define FBC_LL_SIZE (1536) - -/* Framebuffer compression for GM45+ */ -#define DPFC_CB_BASE 0x3200 -#define DPFC_CONTROL 0x3208 -#define DPFC_CTL_EN (1<<31) -#define DPFC_CTL_PLANEA (0<<30) -#define DPFC_CTL_PLANEB (1<<30) -#define DPFC_CTL_FENCE_EN (1<<29) -#define DPFC_CTL_PERSISTENT_MODE (1<<25) -#define DPFC_SR_EN (1<<10) -#define DPFC_CTL_LIMIT_1X (0<<6) -#define DPFC_CTL_LIMIT_2X (1<<6) -#define DPFC_CTL_LIMIT_4X (2<<6) -#define DPFC_RECOMP_CTL 0x320c -#define DPFC_RECOMP_STALL_EN (1<<27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) -#define DPFC_STATUS 0x3210 -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000003ff) -#define DPFC_STATUS2 0x3214 -#define DPFC_FENCE_YOFF 0x3218 -#define DPFC_CHICKEN 0x3224 -#define DPFC_HT_MODIFY (1<<31) - -/* Framebuffer compression for Ironlake */ -#define ILK_DPFC_CB_BASE 0x43200 -#define ILK_DPFC_CONTROL 0x43208 -/* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) -#define ILK_DPFC_RECOMP_CTL 0x4320c -#define ILK_DPFC_STATUS 0x43210 -#define ILK_DPFC_FENCE_YOFF 0x43218 -#define ILK_DPFC_CHICKEN 0x43224 -#define ILK_FBC_RT_BASE 0x2128 -#define ILK_FBC_RT_VALID (1<<0) - -#define ILK_DISPLAY_CHICKEN1 0x42000 -#define ILK_FBCQ_DIS (1<<22) -#define ILK_PABSTRETCH_DIS (1<<21) - - -/* - * Framebuffer compression for Sandybridge - * - * The following two registers are of type GTTMMADR - */ -#define SNB_DPFC_CTL_SA 0x100100 -#define SNB_CPU_FENCE_ENABLE (1<<29) -#define DPFC_CPU_FENCE_OFFSET 0x100104 - - -/* - * GPIO regs - */ -#define GPIOA 0x5010 -#define GPIOB 0x5014 -#define GPIOC 0x5018 -#define GPIOD 0x501c -#define GPIOE 0x5020 -#define GPIOF 0x5024 -#define GPIOG 0x5028 -#define GPIOH 0x502c -# define GPIO_CLOCK_DIR_MASK (1 << 0) -# define GPIO_CLOCK_DIR_IN (0 << 1) -# define GPIO_CLOCK_DIR_OUT (1 << 1) -# define GPIO_CLOCK_VAL_MASK (1 << 2) -# define GPIO_CLOCK_VAL_OUT (1 << 3) -# define GPIO_CLOCK_VAL_IN (1 << 4) -# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) -# define GPIO_DATA_DIR_MASK (1 << 8) -# define GPIO_DATA_DIR_IN (0 << 9) -# define GPIO_DATA_DIR_OUT (1 << 9) -# define GPIO_DATA_VAL_MASK (1 << 10) -# define GPIO_DATA_VAL_OUT (1 << 11) -# define GPIO_DATA_VAL_IN (1 << 12) -# define GPIO_DATA_PULLUP_DISABLE (1 << 13) - -#define GMBUS0 0x5100 /* clock/port select */ -#define GMBUS_RATE_100KHZ (0<<8) -#define GMBUS_RATE_50KHZ (1<<8) -#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ -#define GMBUS_RATE_MASK (3<<8) -#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) -#define GMBUS_PORT_MASK 7 -#define GMBUS1 0x5104 /* command/status */ -#define GMBUS_SW_CLR_INT (1<<31) -#define GMBUS_SW_RDY (1<<30) -#define GMBUS_ENT (1<<29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0<<25) -#define GMBUS_CYCLE_WAIT (1<<25) -#define GMBUS_CYCLE_INDEX (2<<25) -#define GMBUS_CYCLE_STOP (4<<25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1<<0) -#define GMBUS_SLAVE_WRITE (0<<0) -#define GMBUS2 0x5108 /* status */ -#define GMBUS_INUSE (1<<15) -#define GMBUS_HW_WAIT_PHASE (1<<14) -#define GMBUS_STALL_TIMEOUT (1<<13) -#define GMBUS_INT (1<<12) -#define GMBUS_HW_RDY (1<<11) -#define GMBUS_SATOER (1<<10) -#define GMBUS_ACTIVE (1<<9) -#define GMBUS3 0x510c /* data buffer bytes 3-0 */ -#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ -#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) -#define GMBUS_NAK_EN (1<<3) -#define GMBUS_IDLE_EN (1<<2) -#define GMBUS_HW_WAIT_EN (1<<1) -#define GMBUS_HW_RDY_EN (1<<0) -#define GMBUS5 0x5120 /* byte index */ -#define GMBUS_2BYTE_INDEX_EN (1<<31) - -/* - * Clock control & power management - */ - -#define VGA0 0x6000 -#define VGA1 0x6004 -#define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) -#define _DPLL_A 0x06014 -#define _DPLL_B 0x06018 -#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ - -#define SRX_INDEX 0x3c4 -#define SRX_DATA 0x3c5 -#define SR01 1 -#define SR01_SCREEN_OFF (1<<5) - -#define PPCR 0x61204 -#define PPCR_ON (1<<0) - -#define DVOB 0x61140 -#define DVOB_ON (1<<31) -#define DVOC 0x61160 -#define DVOC_ON (1<<31) -#define LVDS 0x61180 -#define LVDS_ON (1<<31) - -/* Scratch pad debug 0 reg: - */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 -/* - * The i830 generation, in LVDS mode, defines P1 as the bit number set within - * this field (only one bit may be set). - */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 -/* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 -/* Ironlake */ -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) -# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff - -/* - * Parallel to Serial Load Pulse phase selection. - * Selects the phase for the 10X DPLL clock for the PCIe - * digital display port. The range is 4 to 13; 10 or more - * is just a flip delay. The default is 6 - */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) -/* - * SDVO multiplier for 945G/GM. Not used on 965. - */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD 0x0601c /* 965+ only */ -/* - * UDI pixel divider, controlling how many pixels are stuffed into a packet. - * - * Value is pixels minus 1. Must be set to 1 pixel for SDVO. - */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 -/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 -/* - * SDVO/UDI pixel multiplier. - * - * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus - * clock rate is 10 times the DPLL clock. At low resolution/refresh rate - * modes, the bus rate would be below the limits, so SDVO allows for stuffing - * dummy bytes in the datastream at an increased clock rate, with both sides of - * the link knowing how many bytes are fill. - * - * So, for a mode with a dotclock of 65Mhz, we would want to double the clock - * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be - * set to 130Mhz, and the SDVO multiplier set to 2x in this register and - * through an SDVO command. - * - * This register field has values of multiplication factor minus 1, with - * a maximum multiplier of 5 for SDVO. - */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 -/* - * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. - * This best be set to the default value (3) or the CRT won't work. No, - * I don't entirely understand what this does... - */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 -#define _DPLL_B_MD 0x06020 /* 965+ only */ -#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) -#define _FPA0 0x06040 -#define _FPA1 0x06044 -#define _FPB0 0x06048 -#define _FPB1 0x0604c -#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) -#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 -#define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) -#define D_STATE 0x6104 -#define DSTATE_GFX_RESET_I830 (1<<6) -#define DSTATE_PLL_D3_OFF (1<<3) -#define DSTATE_GFX_CLOCK_GATING (1<<1) -#define DSTATE_DOT_CLOCK_GATING (1<<0) -#define DSPCLK_GATE_D 0x6200 -# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ -# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ -# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ -# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ -# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ -# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ -# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ -# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ -# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ -# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ -# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ -# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ -# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ -# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ -# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ -# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ -# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ -# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ -# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ -# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) -# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) -# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) -# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) -# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ -# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ -# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ -# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) -# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) -/** - * This bit must be set on the 830 to prevent hangs when turning off the - * overlay scaler. - */ -# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) -# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) -# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) -# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ -# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ - -#define RENCLK_GATE_D1 0x6204 -# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ -# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ -# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) -# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) -# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) -# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) -# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) -# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) -# define MAG_CLOCK_GATE_DISABLE (1 << 5) -/** This bit must be unset on 855,865 */ -# define MECI_CLOCK_GATE_DISABLE (1 << 4) -# define DCMP_CLOCK_GATE_DISABLE (1 << 3) -# define MEC_CLOCK_GATE_DISABLE (1 << 2) -# define MECO_CLOCK_GATE_DISABLE (1 << 1) -/** This bit must be set on 855,865. */ -# define SV_CLOCK_GATE_DISABLE (1 << 0) -# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) -# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) -# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) -# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) -# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) -# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) -# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) -# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) -# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) -# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) -# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) -# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) -# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) -# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) -# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) -# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) -# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) - -# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) -/** This bit must always be set on 965G/965GM */ -# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) -# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) -# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) -# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) -# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) -# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) -/** This bit must always be set on 965G */ -# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) -# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) -# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) -# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) -# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) -# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) -# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) -# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) -# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) -# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) -# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) -# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) -# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) -# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) -# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) -# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) -# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) -# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) -# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) - -#define RENCLK_GATE_D2 0x6208 -#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) -#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) -#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) -#define RAMCLK_GATE_D 0x6210 /* CRL only */ -#define DEUC 0x6214 /* CRL only */ - -/* - * Palette regs - */ - -#define _PALETTE_A 0x0a000 -#define _PALETTE_B 0x0a800 -#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) - -/* MCH MMIO space */ - -/* - * MCHBAR mirror. - * - * This mirrors the MCHBAR MMIO space whose location is determined by - * device 0 function 0's pci config register 0x44 or 0x48 and matches it in - * every way. It is not accessible from the CP register read instructions. - * - */ -#define MCHBAR_MIRROR_BASE 0x10000 - -#define MCHBAR_MIRROR_BASE_SNB 0x140000 - -/** 915-945 and GM965 MCH register controlling DRAM channel access */ -#define DCC 0x10200 -#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) -#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) -#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) -#define DCC_ADDRESSING_MODE_MASK (3 << 0) -#define DCC_CHANNEL_XOR_DISABLE (1 << 10) -#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) - -/** Pineview MCH register contains DDR3 setting */ -#define CSHRDDR3CTL 0x101a8 -#define CSHRDDR3CTL_DDR3 (1 << 2) - -/** 965 MCH register controlling DRAM channel configuration */ -#define C0DRB3 0x10206 -#define C1DRB3 0x10606 - -/** snb MCH registers for reading the DRAM channel configuration */ -#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) -#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) -#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) -#define MAD_DIMM_ECC_MASK (0x3 << 24) -#define MAD_DIMM_ECC_OFF (0x0 << 24) -#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) -#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) -#define MAD_DIMM_ECC_ON (0x3 << 24) -#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) -#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) -#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ -#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ -#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) -#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) -#define MAD_DIMM_A_SELECT (0x1 << 16) -/* DIMM sizes are in multiples of 256mb. */ -#define MAD_DIMM_B_SIZE_SHIFT 8 -#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) -#define MAD_DIMM_A_SIZE_SHIFT 0 -#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) - - -/* Clocking configuration register */ -#define CLKCFG 0x10c00 -#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ -#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ -#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ -#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ -#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ -#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ -/* Note, below two are guess */ -#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ -#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ -#define CLKCFG_FSB_MASK (7 << 0) -#define CLKCFG_MEM_533 (1 << 4) -#define CLKCFG_MEM_667 (2 << 4) -#define CLKCFG_MEM_800 (3 << 4) -#define CLKCFG_MEM_MASK (7 << 4) - -#define TSC1 0x11001 -#define TSE (1<<0) -#define TR1 0x11006 -#define TSFS 0x11020 -#define TSFS_SLOPE_MASK 0x0000ff00 -#define TSFS_SLOPE_SHIFT 8 -#define TSFS_INTR_MASK 0x000000ff - -#define CRSTANDVID 0x11100 -#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ -#define PXVFREQ_PX_MASK 0x7f000000 -#define PXVFREQ_PX_SHIFT 24 -#define VIDFREQ_BASE 0x11110 -#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ -#define VIDFREQ2 0x11114 -#define VIDFREQ3 0x11118 -#define VIDFREQ4 0x1111c -#define VIDFREQ_P0_MASK 0x1f000000 -#define VIDFREQ_P0_SHIFT 24 -#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 -#define VIDFREQ_P0_CSCLK_SHIFT 20 -#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 -#define VIDFREQ_P0_CRCLK_SHIFT 16 -#define VIDFREQ_P1_MASK 0x00001f00 -#define VIDFREQ_P1_SHIFT 8 -#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 -#define VIDFREQ_P1_CSCLK_SHIFT 4 -#define VIDFREQ_P1_CRCLK_MASK 0x0000000f -#define INTTOEXT_BASE_ILK 0x11300 -#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ -#define INTTOEXT_MAP3_SHIFT 24 -#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) -#define INTTOEXT_MAP2_SHIFT 16 -#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) -#define INTTOEXT_MAP1_SHIFT 8 -#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) -#define INTTOEXT_MAP0_SHIFT 0 -#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) -#define MEMSWCTL 0x11170 /* Ironlake only */ -#define MEMCTL_CMD_MASK 0xe000 -#define MEMCTL_CMD_SHIFT 13 -#define MEMCTL_CMD_RCLK_OFF 0 -#define MEMCTL_CMD_RCLK_ON 1 -#define MEMCTL_CMD_CHFREQ 2 -#define MEMCTL_CMD_CHVID 3 -#define MEMCTL_CMD_VMMOFF 4 -#define MEMCTL_CMD_VMMON 5 -#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears - when command complete */ -#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ -#define MEMCTL_FREQ_SHIFT 8 -#define MEMCTL_SFCAVM (1<<7) -#define MEMCTL_TGT_VID_MASK 0x007f -#define MEMIHYST 0x1117c -#define MEMINTREN 0x11180 /* 16 bits */ -#define MEMINT_RSEXIT_EN (1<<8) -#define MEMINT_CX_SUPR_EN (1<<7) -#define MEMINT_CONT_BUSY_EN (1<<6) -#define MEMINT_AVG_BUSY_EN (1<<5) -#define MEMINT_EVAL_CHG_EN (1<<4) -#define MEMINT_MON_IDLE_EN (1<<3) -#define MEMINT_UP_EVAL_EN (1<<2) -#define MEMINT_DOWN_EVAL_EN (1<<1) -#define MEMINT_SW_CMD_EN (1<<0) -#define MEMINTRSTR 0x11182 /* 16 bits */ -#define MEM_RSEXIT_MASK 0xc000 -#define MEM_RSEXIT_SHIFT 14 -#define MEM_CONT_BUSY_MASK 0x3000 -#define MEM_CONT_BUSY_SHIFT 12 -#define MEM_AVG_BUSY_MASK 0x0c00 -#define MEM_AVG_BUSY_SHIFT 10 -#define MEM_EVAL_CHG_MASK 0x0300 -#define MEM_EVAL_BUSY_SHIFT 8 -#define MEM_MON_IDLE_MASK 0x00c0 -#define MEM_MON_IDLE_SHIFT 6 -#define MEM_UP_EVAL_MASK 0x0030 -#define MEM_UP_EVAL_SHIFT 4 -#define MEM_DOWN_EVAL_MASK 0x000c -#define MEM_DOWN_EVAL_SHIFT 2 -#define MEM_SW_CMD_MASK 0x0003 -#define MEM_INT_STEER_GFX 0 -#define MEM_INT_STEER_CMR 1 -#define MEM_INT_STEER_SMI 2 -#define MEM_INT_STEER_SCI 3 -#define MEMINTRSTS 0x11184 -#define MEMINT_RSEXIT (1<<7) -#define MEMINT_CONT_BUSY (1<<6) -#define MEMINT_AVG_BUSY (1<<5) -#define MEMINT_EVAL_CHG (1<<4) -#define MEMINT_MON_IDLE (1<<3) -#define MEMINT_UP_EVAL (1<<2) -#define MEMINT_DOWN_EVAL (1<<1) -#define MEMINT_SW_CMD (1<<0) -#define MEMMODECTL 0x11190 -#define MEMMODE_BOOST_EN (1<<31) -#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ -#define MEMMODE_BOOST_FREQ_SHIFT 24 -#define MEMMODE_IDLE_MODE_MASK 0x00030000 -#define MEMMODE_IDLE_MODE_SHIFT 16 -#define MEMMODE_IDLE_MODE_EVAL 0 -#define MEMMODE_IDLE_MODE_CONT 1 -#define MEMMODE_HWIDLE_EN (1<<15) -#define MEMMODE_SWMODE_EN (1<<14) -#define MEMMODE_RCLK_GATE (1<<13) -#define MEMMODE_HW_UPDATE (1<<12) -#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ -#define MEMMODE_FSTART_SHIFT 8 -#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ -#define MEMMODE_FMAX_SHIFT 4 -#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ -#define RCBMAXAVG 0x1119c -#define MEMSWCTL2 0x1119e /* Cantiga only */ -#define SWMEMCMD_RENDER_OFF (0 << 13) -#define SWMEMCMD_RENDER_ON (1 << 13) -#define SWMEMCMD_SWFREQ (2 << 13) -#define SWMEMCMD_TARVID (3 << 13) -#define SWMEMCMD_VRM_OFF (4 << 13) -#define SWMEMCMD_VRM_ON (5 << 13) -#define CMDSTS (1<<12) -#define SFCAVM (1<<11) -#define SWFREQ_MASK 0x0380 /* P0-7 */ -#define SWFREQ_SHIFT 7 -#define TARVID_MASK 0x001f -#define MEMSTAT_CTG 0x111a0 -#define RCBMINAVG 0x111a0 -#define RCUPEI 0x111b0 -#define RCDNEI 0x111b4 -#define RSTDBYCTL 0x111b8 -#define RS1EN (1<<31) -#define RS2EN (1<<30) -#define RS3EN (1<<29) -#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ -#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ -#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ -#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ -#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ -#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ -#define RSX_STATUS_MASK (7<<20) -#define RSX_STATUS_ON (0<<20) -#define RSX_STATUS_RC1 (1<<20) -#define RSX_STATUS_RC1E (2<<20) -#define RSX_STATUS_RS1 (3<<20) -#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ -#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ -#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ -#define RSX_STATUS_RSVD2 (7<<20) -#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ -#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ -#define JRSC (1<<17) /* rsx coupled to cpu c-state */ -#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ -#define RS1CONTSAV_MASK (3<<14) -#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ -#define RS1CONTSAV_RSVD (1<<14) -#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ -#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ -#define NORMSLEXLAT_MASK (3<<12) -#define SLOW_RS123 (0<<12) -#define SLOW_RS23 (1<<12) -#define SLOW_RS3 (2<<12) -#define NORMAL_RS123 (3<<12) -#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ -#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ -#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ -#define RS_CSTATE_MASK (3<<4) -#define RS_CSTATE_C367_RS1 (0<<4) -#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) -#define RS_CSTATE_RSVD (2<<4) -#define RS_CSTATE_C367_RS2 (3<<4) -#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ -#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ -#define VIDCTL 0x111c0 -#define VIDSTS 0x111c8 -#define VIDSTART 0x111cc /* 8 bits */ -#define MEMSTAT_ILK 0x111f8 -#define MEMSTAT_VID_MASK 0x7f00 -#define MEMSTAT_VID_SHIFT 8 -#define MEMSTAT_PSTATE_MASK 0x00f8 -#define MEMSTAT_PSTATE_SHIFT 3 -#define MEMSTAT_MON_ACTV (1<<2) -#define MEMSTAT_SRC_CTL_MASK 0x0003 -#define MEMSTAT_SRC_CTL_CORE 0 -#define MEMSTAT_SRC_CTL_TRB 1 -#define MEMSTAT_SRC_CTL_THM 2 -#define MEMSTAT_SRC_CTL_STDBY 3 -#define RCPREVBSYTUPAVG 0x113b8 -#define RCPREVBSYTDNAVG 0x113bc -#define PMMISC 0x11214 -#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ -#define SDEW 0x1124c -#define CSIEW0 0x11250 -#define CSIEW1 0x11254 -#define CSIEW2 0x11258 -#define PEW 0x1125c -#define DEW 0x11270 -#define MCHAFE 0x112c0 -#define CSIEC 0x112e0 -#define DMIEC 0x112e4 -#define DDREC 0x112e8 -#define PEG0EC 0x112ec -#define PEG1EC 0x112f0 -#define GFXEC 0x112f4 -#define RPPREVBSYTUPAVG 0x113b8 -#define RPPREVBSYTDNAVG 0x113bc -#define ECR 0x11600 -#define ECR_GPFE (1<<31) -#define ECR_IMONE (1<<30) -#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ -#define OGW0 0x11608 -#define OGW1 0x1160c -#define EG0 0x11610 -#define EG1 0x11614 -#define EG2 0x11618 -#define EG3 0x1161c -#define EG4 0x11620 -#define EG5 0x11624 -#define EG6 0x11628 -#define EG7 0x1162c -#define PXW 0x11664 -#define PXWL 0x11680 -#define LCFUSE02 0x116c0 -#define LCFUSE_HIV_MASK 0x000000ff -#define CSIPLL0 0x12c10 -#define DDRMPLL1 0X12c20 -#define PEG_BAND_GAP_DATA 0x14d68 - -#define GEN6_GT_THREAD_STATUS_REG 0x13805c -#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 - -#define GEN6_GT_PERF_STATUS 0x145948 -#define GEN6_RP_STATE_LIMITS 0x145994 -#define GEN6_RP_STATE_CAP 0x145998 - -/* - * Logical Context regs - */ -#define CCID 0x2180 -#define CCID_EN (1<<0) -/* - * Overlay regs - */ - -#define OVADD 0x30000 -#define DOVSTA 0x30008 -#define OC_BUF (0x3<<20) -#define OGAMC5 0x30010 -#define OGAMC4 0x30014 -#define OGAMC3 0x30018 -#define OGAMC2 0x3001c -#define OGAMC1 0x30020 -#define OGAMC0 0x30024 - -/* - * Display engine regs - */ - -/* Pipe A timing regs */ -#define _HTOTAL_A 0x60000 -#define _HBLANK_A 0x60004 -#define _HSYNC_A 0x60008 -#define _VTOTAL_A 0x6000c -#define _VBLANK_A 0x60010 -#define _VSYNC_A 0x60014 -#define _PIPEASRC 0x6001c -#define _BCLRPAT_A 0x60020 -#define _VSYNCSHIFT_A 0x60028 - -/* Pipe B timing regs */ -#define _HTOTAL_B 0x61000 -#define _HBLANK_B 0x61004 -#define _HSYNC_B 0x61008 -#define _VTOTAL_B 0x6100c -#define _VBLANK_B 0x61010 -#define _VSYNC_B 0x61014 -#define _PIPEBSRC 0x6101c -#define _BCLRPAT_B 0x61020 -#define _VSYNCSHIFT_B 0x61028 - - -#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) -#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) -#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) -#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) -#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) -#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) -#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) -#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) - -/* VGA port control */ -#define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) - - -/* Hotplug control (945+ only) */ -#define PORT_HOTPLUG_EN 0x61110 -#define HDMIB_HOTPLUG_INT_EN (1 << 29) -#define DPB_HOTPLUG_INT_EN (1 << 29) -#define HDMIC_HOTPLUG_INT_EN (1 << 28) -#define DPC_HOTPLUG_INT_EN (1 << 28) -#define HDMID_HOTPLUG_INT_EN (1 << 27) -#define DPD_HOTPLUG_INT_EN (1 << 27) -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) -#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) -/* must use period 64 on GM45 according to docs */ -#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) -#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) -#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) -#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) -#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) -#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) -#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) -#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) -#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) -#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) -#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) -#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) - -#define PORT_HOTPLUG_STAT 0x61114 -#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) -#define DPB_HOTPLUG_INT_STATUS (1 << 29) -#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) -#define DPC_HOTPLUG_INT_STATUS (1 << 28) -#define HDMID_HOTPLUG_INT_STATUS (1 << 27) -#define DPD_HOTPLUG_INT_STATUS (1 << 27) -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) - -/* SDVO port control */ -#define SDVOB 0x61140 -#define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) -/** - * 915G/GM SDVO pixel multiplier. - * - * Programmed value is multiplier - 1, up to 5x. - * - * \sa DPLL_MD_UDI_MULTIPLIER_MASK - */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_ENCODING_SDVO (0x0 << 10) -#define SDVO_ENCODING_HDMI (0x2 << 10) -/** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) -#define SDVO_COLOR_RANGE_16_235 (1 << 8) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVO_AUDIO_ENABLE (1 << 6) -/** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) -/** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) -/* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) - -/* DVO port control */ -#define DVOA 0x61120 -#define DVOB 0x61140 -#define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) -#define DVOA_SRCDIM 0x61124 -#define DVOB_SRCDIM 0x61144 -#define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 - -/* LVDS port control */ -#define LVDS 0x61180 -/* - * Enables the LVDS port. This bit must be set before DPLLs are enabled, as - * the DPLL semantics change when the LVDS is assigned to that pipe. - */ -#define LVDS_PORT_EN (1 << 31) -/* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -#define LVDS_PIPE_MASK (1 << 30) -#define LVDS_PIPE(pipe) ((pipe) << 30) -/* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) -/* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) - -/* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) -/* - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per - * pixel. - */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) -/* - * Controls the A3 data pair, which contains the additional LSBs for 24 bit - * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be - * on. - */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) -/* - * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP - * is set. - */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) -/* - * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 - * setting for whether we are in dual-channel mode. The B3 pair will - * additionally only be powered up when LVDS_A3_POWER_UP is set. - */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) - -/* Video Data Island Packet control */ -#define VIDEO_DIP_DATA 0x61178 -#define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT_B (1 << 29) -#define VIDEO_DIP_PORT_C (2 << 29) -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) - -/* Panel power sequencing */ -#define PP_STATUS 0x61200 -#define PP_ON (1 << 31) -/* - * Indicates that all dependencies of the panel are on: - * - * - PLL enabled - * - pipe enabled - * - LVDS/DVOB/DVOC on - */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_POWER_UP (1 << 28) -#define PP_SEQUENCE_POWER_DOWN (2 << 28) -#define PP_SEQUENCE_MASK (3 << 28) -#define PP_SEQUENCE_SHIFT 28 -#define PP_CYCLE_DELAY_ACTIVE (1 << 27) -#define PP_SEQUENCE_STATE_MASK 0x0000000f -#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) -#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) -#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) -#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) -#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) -#define PP_SEQUENCE_STATE_RESET (0xf << 0) -#define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) -#define PP_ON_DELAYS 0x61208 -#define PP_OFF_DELAYS 0x6120c -#define PP_DIVISOR 0x61210 - -/* Panel fitting */ -#define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_FILTER_FUZZY (0 << 24) -#define PFIT_SCALING_AUTO (0 << 26) -#define PFIT_SCALING_PROGRAMMED (1 << 26) -#define PFIT_SCALING_PILLAR (2 << 26) -#define PFIT_SCALING_LETTER (3 << 26) -#define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 -/* Pre-965 */ -#define PFIT_VERT_SCALE_SHIFT 20 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_SHIFT 4 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 -/* 965+ */ -#define PFIT_VERT_SCALE_SHIFT_965 16 -#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 -#define PFIT_HORIZ_SCALE_SHIFT_965 0 -#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff - -#define PFIT_AUTO_RATIOS 0x61238 - -/* Backlight control */ -#define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) -#define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) -/* - * This is the most significant 15 bits of the number of backlight cycles in a - * complete cycle of the modulated backlight control. - * - * The actual value is this field multiplied by two. - */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) -/* - * This is the number of cycles out of the backlight modulation cycle for which - * the backlight is on. - * - * This field must be no greater than the number of cycles in the complete - * backlight modulation cycle. - */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) - -#define BLC_HIST_CTL 0x61260 - -/* TV port control */ -#define TV_CTL 0x68000 -/** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) -/** Sources the TV encoder input from pipe B instead of A. */ -# define TV_ENC_PIPEB_SELECT (1 << 30) -/** Outputs composite video (DAC A only) */ -# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) -/** Outputs SVideo video (DAC B/C) */ -# define TV_ENC_OUTPUT_SVIDEO (1 << 28) -/** Outputs Component video (DAC A/B/C) */ -# define TV_ENC_OUTPUT_COMPONENT (2 << 28) -/** Outputs Composite and SVideo (DAC A/B/C) */ -# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) -# define TV_TRILEVEL_SYNC (1 << 21) -/** Enables slow sync generation (945GM only) */ -# define TV_SLOW_SYNC (1 << 20) -/** Selects 4x oversampling for 480i and 576p */ -# define TV_OVERSAMPLE_4X (0 << 18) -/** Selects 2x oversampling for 720p and 1080i */ -# define TV_OVERSAMPLE_2X (1 << 18) -/** Selects no oversampling for 1080p */ -# define TV_OVERSAMPLE_NONE (2 << 18) -/** Selects 8x oversampling */ -# define TV_OVERSAMPLE_8X (3 << 18) -/** Selects progressive mode rather than interlaced */ -# define TV_PROGRESSIVE (1 << 17) -/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ -# define TV_PAL_BURST (1 << 16) -/** Field for setting delay of Y compared to C */ -# define TV_YC_SKEW_MASK (7 << 12) -/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ -# define TV_ENC_SDP_FIX (1 << 11) -/** - * Enables a fix for the 915GM only. - * - * Not sure what it does. - */ -# define TV_ENC_C0_FIX (1 << 10) -/** Bits that must be preserved by software */ -# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) -# define TV_FUSE_STATE_MASK (3 << 4) -/** Read-only state that reports all features enabled */ -# define TV_FUSE_STATE_ENABLED (0 << 4) -/** Read-only state that reports that Macrovision is disabled in hardware*/ -# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) -/** Read-only state that reports that TV-out is disabled in hardware. */ -# define TV_FUSE_STATE_DISABLED (2 << 4) -/** Normal operation */ -# define TV_TEST_MODE_NORMAL (0 << 0) -/** Encoder test pattern 1 - combo pattern */ -# define TV_TEST_MODE_PATTERN_1 (1 << 0) -/** Encoder test pattern 2 - full screen vertical 75% color bars */ -# define TV_TEST_MODE_PATTERN_2 (2 << 0) -/** Encoder test pattern 3 - full screen horizontal 75% color bars */ -# define TV_TEST_MODE_PATTERN_3 (3 << 0) -/** Encoder test pattern 4 - random noise */ -# define TV_TEST_MODE_PATTERN_4 (4 << 0) -/** Encoder test pattern 5 - linear color ramps */ -# define TV_TEST_MODE_PATTERN_5 (5 << 0) -/** - * This test mode forces the DACs to 50% of full output. - * - * This is used for load detection in combination with TVDAC_SENSE_MASK - */ -# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) -# define TV_TEST_MODE_MASK (7 << 0) - -#define TV_DAC 0x68004 -# define TV_DAC_SAVE 0x00ffff00 -/** - * Reports that DAC state change logic has reported change (RO). - * - * This gets cleared when TV_DAC_STATE_EN is cleared -*/ -# define TVDAC_STATE_CHG (1 << 31) -# define TVDAC_SENSE_MASK (7 << 28) -/** Reports that DAC A voltage is above the detect threshold */ -# define TVDAC_A_SENSE (1 << 30) -/** Reports that DAC B voltage is above the detect threshold */ -# define TVDAC_B_SENSE (1 << 29) -/** Reports that DAC C voltage is above the detect threshold */ -# define TVDAC_C_SENSE (1 << 28) -/** - * Enables DAC state detection logic, for load-based TV detection. - * - * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set - * to off, for load detection to work. - */ -# define TVDAC_STATE_CHG_EN (1 << 27) -/** Sets the DAC A sense value to high */ -# define TVDAC_A_SENSE_CTL (1 << 26) -/** Sets the DAC B sense value to high */ -# define TVDAC_B_SENSE_CTL (1 << 25) -/** Sets the DAC C sense value to high */ -# define TVDAC_C_SENSE_CTL (1 << 24) -/** Overrides the ENC_ENABLE and DAC voltage levels */ -# define DAC_CTL_OVERRIDE (1 << 7) -/** Sets the slew rate. Must be preserved in software */ -# define ENC_TVDAC_SLEW_FAST (1 << 6) -# define DAC_A_1_3_V (0 << 4) -# define DAC_A_1_1_V (1 << 4) -# define DAC_A_0_7_V (2 << 4) -# define DAC_A_MASK (3 << 4) -# define DAC_B_1_3_V (0 << 2) -# define DAC_B_1_1_V (1 << 2) -# define DAC_B_0_7_V (2 << 2) -# define DAC_B_MASK (3 << 2) -# define DAC_C_1_3_V (0 << 0) -# define DAC_C_1_1_V (1 << 0) -# define DAC_C_0_7_V (2 << 0) -# define DAC_C_MASK (3 << 0) - -/** - * CSC coefficients are stored in a floating point format with 9 bits of - * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, - * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with - * -1 (0x3) being the only legal negative value. - */ -#define TV_CSC_Y 0x68010 -# define TV_RY_MASK 0x07ff0000 -# define TV_RY_SHIFT 16 -# define TV_GY_MASK 0x00000fff -# define TV_GY_SHIFT 0 - -#define TV_CSC_Y2 0x68014 -# define TV_BY_MASK 0x07ff0000 -# define TV_BY_SHIFT 16 -/** - * Y attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AY_MASK 0x000003ff -# define TV_AY_SHIFT 0 - -#define TV_CSC_U 0x68018 -# define TV_RU_MASK 0x07ff0000 -# define TV_RU_SHIFT 16 -# define TV_GU_MASK 0x000007ff -# define TV_GU_SHIFT 0 - -#define TV_CSC_U2 0x6801c -# define TV_BU_MASK 0x07ff0000 -# define TV_BU_SHIFT 16 -/** - * U attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AU_MASK 0x000003ff -# define TV_AU_SHIFT 0 - -#define TV_CSC_V 0x68020 -# define TV_RV_MASK 0x0fff0000 -# define TV_RV_SHIFT 16 -# define TV_GV_MASK 0x000007ff -# define TV_GV_SHIFT 0 - -#define TV_CSC_V2 0x68024 -# define TV_BV_MASK 0x07ff0000 -# define TV_BV_SHIFT 16 -/** - * V attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AV_MASK 0x000007ff -# define TV_AV_SHIFT 0 - -#define TV_CLR_KNOBS 0x68028 -/** 2s-complement brightness adjustment */ -# define TV_BRIGHTNESS_MASK 0xff000000 -# define TV_BRIGHTNESS_SHIFT 24 -/** Contrast adjustment, as a 2.6 unsigned floating point number */ -# define TV_CONTRAST_MASK 0x00ff0000 -# define TV_CONTRAST_SHIFT 16 -/** Saturation adjustment, as a 2.6 unsigned floating point number */ -# define TV_SATURATION_MASK 0x0000ff00 -# define TV_SATURATION_SHIFT 8 -/** Hue adjustment, as an integer phase angle in degrees */ -# define TV_HUE_MASK 0x000000ff -# define TV_HUE_SHIFT 0 - -#define TV_CLR_LEVEL 0x6802c -/** Controls the DAC level for black */ -# define TV_BLACK_LEVEL_MASK 0x01ff0000 -# define TV_BLACK_LEVEL_SHIFT 16 -/** Controls the DAC level for blanking */ -# define TV_BLANK_LEVEL_MASK 0x000001ff -# define TV_BLANK_LEVEL_SHIFT 0 - -#define TV_H_CTL_1 0x68030 -/** Number of pixels in the hsync. */ -# define TV_HSYNC_END_MASK 0x1fff0000 -# define TV_HSYNC_END_SHIFT 16 -/** Total number of pixels minus one in the line (display and blanking). */ -# define TV_HTOTAL_MASK 0x00001fff -# define TV_HTOTAL_SHIFT 0 - -#define TV_H_CTL_2 0x68034 -/** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) -/** Offset of the colorburst from the start of hsync, in pixels minus one. */ -# define TV_HBURST_START_SHIFT 16 -# define TV_HBURST_START_MASK 0x1fff0000 -/** Length of the colorburst */ -# define TV_HBURST_LEN_SHIFT 0 -# define TV_HBURST_LEN_MASK 0x0001fff - -#define TV_H_CTL_3 0x68038 -/** End of hblank, measured in pixels minus one from start of hsync */ -# define TV_HBLANK_END_SHIFT 16 -# define TV_HBLANK_END_MASK 0x1fff0000 -/** Start of hblank, measured in pixels minus one from start of hsync */ -# define TV_HBLANK_START_SHIFT 0 -# define TV_HBLANK_START_MASK 0x0001fff - -#define TV_V_CTL_1 0x6803c -/** XXX */ -# define TV_NBR_END_SHIFT 16 -# define TV_NBR_END_MASK 0x07ff0000 -/** XXX */ -# define TV_VI_END_F1_SHIFT 8 -# define TV_VI_END_F1_MASK 0x00003f00 -/** XXX */ -# define TV_VI_END_F2_SHIFT 0 -# define TV_VI_END_F2_MASK 0x0000003f - -#define TV_V_CTL_2 0x68040 -/** Length of vsync, in half lines */ -# define TV_VSYNC_LEN_MASK 0x07ff0000 -# define TV_VSYNC_LEN_SHIFT 16 -/** Offset of the start of vsync in field 1, measured in one less than the - * number of half lines. - */ -# define TV_VSYNC_START_F1_MASK 0x00007f00 -# define TV_VSYNC_START_F1_SHIFT 8 -/** - * Offset of the start of vsync in field 2, measured in one less than the - * number of half lines. - */ -# define TV_VSYNC_START_F2_MASK 0x0000007f -# define TV_VSYNC_START_F2_SHIFT 0 - -#define TV_V_CTL_3 0x68044 -/** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) -/** Length of vsync, in half lines */ -# define TV_VEQ_LEN_MASK 0x007f0000 -# define TV_VEQ_LEN_SHIFT 16 -/** Offset of the start of equalization in field 1, measured in one less than - * the number of half lines. - */ -# define TV_VEQ_START_F1_MASK 0x0007f00 -# define TV_VEQ_START_F1_SHIFT 8 -/** - * Offset of the start of equalization in field 2, measured in one less than - * the number of half lines. - */ -# define TV_VEQ_START_F2_MASK 0x000007f -# define TV_VEQ_START_F2_SHIFT 0 - -#define TV_V_CTL_4 0x68048 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F1_MASK 0x003f0000 -# define TV_VBURST_START_F1_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F1_MASK 0x000000ff -# define TV_VBURST_END_F1_SHIFT 0 - -#define TV_V_CTL_5 0x6804c -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F2_MASK 0x003f0000 -# define TV_VBURST_START_F2_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F2_MASK 0x000000ff -# define TV_VBURST_END_F2_SHIFT 0 - -#define TV_V_CTL_6 0x68050 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F3_MASK 0x003f0000 -# define TV_VBURST_START_F3_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F3_MASK 0x000000ff -# define TV_VBURST_END_F3_SHIFT 0 - -#define TV_V_CTL_7 0x68054 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F4_MASK 0x003f0000 -# define TV_VBURST_START_F4_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F4_MASK 0x000000ff -# define TV_VBURST_END_F4_SHIFT 0 - -#define TV_SC_CTL_1 0x68060 -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA2_EN (1 << 30) -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA3_EN (1 << 29) -/** Sets the subcarrier DDA to reset frequency every other field */ -# define TV_SC_RESET_EVERY_2 (0 << 24) -/** Sets the subcarrier DDA to reset frequency every fourth field */ -# define TV_SC_RESET_EVERY_4 (1 << 24) -/** Sets the subcarrier DDA to reset frequency every eighth field */ -# define TV_SC_RESET_EVERY_8 (2 << 24) -/** Sets the subcarrier DDA to never reset the frequency */ -# define TV_SC_RESET_NEVER (3 << 24) -/** Sets the peak amplitude of the colorburst.*/ -# define TV_BURST_LEVEL_MASK 0x00ff0000 -# define TV_BURST_LEVEL_SHIFT 16 -/** Sets the increment of the first subcarrier phase generation DDA */ -# define TV_SCDDA1_INC_MASK 0x00000fff -# define TV_SCDDA1_INC_SHIFT 0 - -#define TV_SC_CTL_2 0x68064 -/** Sets the rollover for the second subcarrier phase generation DDA */ -# define TV_SCDDA2_SIZE_MASK 0x7fff0000 -# define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ -# define TV_SCDDA2_INC_MASK 0x00007fff -# define TV_SCDDA2_INC_SHIFT 0 - -#define TV_SC_CTL_3 0x68068 -/** Sets the rollover for the third subcarrier phase generation DDA */ -# define TV_SCDDA3_SIZE_MASK 0x7fff0000 -# define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ -# define TV_SCDDA3_INC_MASK 0x00007fff -# define TV_SCDDA3_INC_SHIFT 0 - -#define TV_WIN_POS 0x68070 -/** X coordinate of the display from the start of horizontal active */ -# define TV_XPOS_MASK 0x1fff0000 -# define TV_XPOS_SHIFT 16 -/** Y coordinate of the display from the start of vertical active (NBR) */ -# define TV_YPOS_MASK 0x00000fff -# define TV_YPOS_SHIFT 0 - -#define TV_WIN_SIZE 0x68074 -/** Horizontal size of the display window, measured in pixels*/ -# define TV_XSIZE_MASK 0x1fff0000 -# define TV_XSIZE_SHIFT 16 -/** - * Vertical size of the display window, measured in pixels. - * - * Must be even for interlaced modes. - */ -# define TV_YSIZE_MASK 0x00000fff -# define TV_YSIZE_SHIFT 0 - -#define TV_FILTER_CTL_1 0x68080 -/** - * Enables automatic scaling calculation. - * - * If set, the rest of the registers are ignored, and the calculated values can - * be read back from the register. - */ -# define TV_AUTO_SCALE (1 << 31) -/** - * Disables the vertical filter. - * - * This is required on modes more than 1024 pixels wide */ -# define TV_V_FILTER_BYPASS (1 << 29) -/** Enables adaptive vertical filtering */ -# define TV_VADAPT (1 << 28) -# define TV_VADAPT_MODE_MASK (3 << 26) -/** Selects the least adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_LEAST (0 << 26) -/** Selects the moderately adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_MODERATE (1 << 26) -/** Selects the most adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_MOST (3 << 26) -/** - * Sets the horizontal scaling factor. - * - * This should be the fractional part of the horizontal scaling factor divided - * by the oversampling rate. TV_HSCALE should be less than 1, and set to: - * - * (src width - 1) / ((oversample * dest width) - 1) - */ -# define TV_HSCALE_FRAC_MASK 0x00003fff -# define TV_HSCALE_FRAC_SHIFT 0 - -#define TV_FILTER_CTL_2 0x68084 -/** - * Sets the integer part of the 3.15 fixed-point vertical scaling factor. - * - * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) - */ -# define TV_VSCALE_INT_MASK 0x00038000 -# define TV_VSCALE_INT_SHIFT 15 -/** - * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. - * - * \sa TV_VSCALE_INT_MASK - */ -# define TV_VSCALE_FRAC_MASK 0x00007fff -# define TV_VSCALE_FRAC_SHIFT 0 - -#define TV_FILTER_CTL_3 0x68088 -/** - * Sets the integer part of the 3.15 fixed-point vertical scaling factor. - * - * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) - * - * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. - */ -# define TV_VSCALE_IP_INT_MASK 0x00038000 -# define TV_VSCALE_IP_INT_SHIFT 15 -/** - * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. - * - * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. - * - * \sa TV_VSCALE_IP_INT_MASK - */ -# define TV_VSCALE_IP_FRAC_MASK 0x00007fff -# define TV_VSCALE_IP_FRAC_SHIFT 0 - -#define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) -/** - * Specifies which field to send the CC data in. - * - * CC data is usually sent in field 0. - */ -# define TV_CC_FID_MASK (1 << 27) -# define TV_CC_FID_SHIFT 27 -/** Sets the horizontal position of the CC data. Usually 135. */ -# define TV_CC_HOFF_MASK 0x03ff0000 -# define TV_CC_HOFF_SHIFT 16 -/** Sets the vertical position of the CC data. Usually 21 */ -# define TV_CC_LINE_MASK 0x0000003f -# define TV_CC_LINE_SHIFT 0 - -#define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) -/** Second word of CC data to be transmitted. */ -# define TV_CC_DATA_2_MASK 0x007f0000 -# define TV_CC_DATA_2_SHIFT 16 -/** First word of CC data to be transmitted. */ -# define TV_CC_DATA_1_MASK 0x0000007f -# define TV_CC_DATA_1_SHIFT 0 - -#define TV_H_LUMA_0 0x68100 -#define TV_H_LUMA_59 0x681ec -#define TV_H_CHROMA_0 0x68200 -#define TV_H_CHROMA_59 0x682ec -#define TV_V_LUMA_0 0x68300 -#define TV_V_LUMA_42 0x683a8 -#define TV_V_CHROMA_0 0x68400 -#define TV_V_CHROMA_42 0x684a8 - -/* Display Port */ -#define DP_A 0x64000 /* eDP */ -#define DP_B 0x64100 -#define DP_C 0x64200 -#define DP_D 0x64300 - -#define DP_PORT_EN (1 << 31) -#define DP_PIPEB_SELECT (1 << 30) -#define DP_PIPE_MASK (1 << 30) - -/* Link training mode - select a suitable mode for each stage */ -#define DP_LINK_TRAIN_PAT_1 (0 << 28) -#define DP_LINK_TRAIN_PAT_2 (1 << 28) -#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) -#define DP_LINK_TRAIN_OFF (3 << 28) -#define DP_LINK_TRAIN_MASK (3 << 28) -#define DP_LINK_TRAIN_SHIFT 28 - -/* CPT Link training mode */ -#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) -#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) -#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) -#define DP_LINK_TRAIN_OFF_CPT (3 << 8) -#define DP_LINK_TRAIN_MASK_CPT (7 << 8) -#define DP_LINK_TRAIN_SHIFT_CPT 8 - -/* Signal voltages. These are mostly controlled by the other end */ -#define DP_VOLTAGE_0_4 (0 << 25) -#define DP_VOLTAGE_0_6 (1 << 25) -#define DP_VOLTAGE_0_8 (2 << 25) -#define DP_VOLTAGE_1_2 (3 << 25) -#define DP_VOLTAGE_MASK (7 << 25) -#define DP_VOLTAGE_SHIFT 25 - -/* Signal pre-emphasis levels, like voltages, the other end tells us what - * they want - */ -#define DP_PRE_EMPHASIS_0 (0 << 22) -#define DP_PRE_EMPHASIS_3_5 (1 << 22) -#define DP_PRE_EMPHASIS_6 (2 << 22) -#define DP_PRE_EMPHASIS_9_5 (3 << 22) -#define DP_PRE_EMPHASIS_MASK (7 << 22) -#define DP_PRE_EMPHASIS_SHIFT 22 - -/* How many wires to use. I guess 3 was too hard */ -#define DP_PORT_WIDTH_1 (0 << 19) -#define DP_PORT_WIDTH_2 (1 << 19) -#define DP_PORT_WIDTH_4 (3 << 19) -#define DP_PORT_WIDTH_MASK (7 << 19) - -/* Mystic DPCD version 1.1 special mode */ -#define DP_ENHANCED_FRAMING (1 << 18) - -/* eDP */ -#define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) -#define DP_PLL_FREQ_MASK (3 << 16) - -/** locked once port is enabled */ -#define DP_PORT_REVERSAL (1 << 15) - -/* eDP */ -#define DP_PLL_ENABLE (1 << 14) - -/** sends the clock on lane 15 of the PEG for debug */ -#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) - -#define DP_SCRAMBLING_DISABLE (1 << 12) -#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) - -/** limit RGB values to avoid confusing TVs */ -#define DP_COLOR_RANGE_16_235 (1 << 8) - -/** Turn on the audio link */ -#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) - -/** vs and hs sync polarity */ -#define DP_SYNC_VS_HIGH (1 << 4) -#define DP_SYNC_HS_HIGH (1 << 3) - -/** A fantasy */ -#define DP_DETECTED (1 << 2) - -/** The aux channel provides a way to talk to the - * signal sink for DDC etc. Max packet size supported - * is 20 bytes in each direction, hence the 5 fixed - * data registers - */ -#define DPA_AUX_CH_CTL 0x64010 -#define DPA_AUX_CH_DATA1 0x64014 -#define DPA_AUX_CH_DATA2 0x64018 -#define DPA_AUX_CH_DATA3 0x6401c -#define DPA_AUX_CH_DATA4 0x64020 -#define DPA_AUX_CH_DATA5 0x64024 - -#define DPB_AUX_CH_CTL 0x64110 -#define DPB_AUX_CH_DATA1 0x64114 -#define DPB_AUX_CH_DATA2 0x64118 -#define DPB_AUX_CH_DATA3 0x6411c -#define DPB_AUX_CH_DATA4 0x64120 -#define DPB_AUX_CH_DATA5 0x64124 - -#define DPC_AUX_CH_CTL 0x64210 -#define DPC_AUX_CH_DATA1 0x64214 -#define DPC_AUX_CH_DATA2 0x64218 -#define DPC_AUX_CH_DATA3 0x6421c -#define DPC_AUX_CH_DATA4 0x64220 -#define DPC_AUX_CH_DATA5 0x64224 - -#define DPD_AUX_CH_CTL 0x64310 -#define DPD_AUX_CH_DATA1 0x64314 -#define DPD_AUX_CH_DATA2 0x64318 -#define DPD_AUX_CH_DATA3 0x6431c -#define DPD_AUX_CH_DATA4 0x64320 -#define DPD_AUX_CH_DATA5 0x64324 - -#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 - -/* - * Computing GMCH M and N values for the Display Port link - * - * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes - * - * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) - * - * The GMCH value is used internally - * - * bytes_per_pixel is the number of bytes coming out of the plane, - * which is after the LUTs, so we want the bytes for our color format. - * For our current usage, this is always 3, one byte for R, G and B. - */ -#define _PIPEA_GMCH_DATA_M 0x70050 -#define _PIPEB_GMCH_DATA_M 0x71050 - -/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 - -#define PIPE_GMCH_DATA_M_MASK (0xffffff) - -#define _PIPEA_GMCH_DATA_N 0x70054 -#define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) - -/* - * Computing Link M and N values for the Display Port link - * - * Link M / N = pixel_clock / ls_clk - * - * (the DP spec calls pixel_clock the 'strm_clk') - * - * The Link value is transmitted in the Main Stream - * Attributes and VB-ID. - */ - -#define _PIPEA_DP_LINK_M 0x70060 -#define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) - -#define _PIPEA_DP_LINK_N 0x70064 -#define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) - -#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) -#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) -#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) -#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) - -/* Display & cursor control */ - -/* Pipe A */ -#define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff -#define _PIPEACONF 0x70008 -#define PIPECONF_ENABLE (1<<31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1<<25) -#define PIPECONF_PALETTE 0 -#define PIPECONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_INTERLACE_MASK (7 << 21) -/* Note that pre-gen3 does not support interlaced display directly. Panel - * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ -/* Ironlake and later have a complete new set of values for interlaced. PFIT - * means panel fitter required, PF means progressive fetch, DBL means power - * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_CXSR_DOWNCLOCK (1<<16) -#define PIPECONF_BPP_MASK (0x000000e0) -#define PIPECONF_BPP_8 (0<<5) -#define PIPECONF_BPP_10 (1<<5) -#define PIPECONF_BPP_6 (2<<5) -#define PIPECONF_BPP_12 (3<<5) -#define PIPECONF_DITHER_EN (1<<4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0<<2) -#define PIPECONF_DITHER_TYPE_ST1 (1<<2) -#define PIPECONF_DITHER_TYPE_ST2 (2<<2) -#define PIPECONF_DITHER_TYPE_TEMP (3<<2) -#define _PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ -#define PIPE_8BPC (0 << 5) -#define PIPE_10BPC (1 << 5) -#define PIPE_6BPC (2 << 5) -#define PIPE_12BPC (3 << 5) - -#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) -#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) -#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) -#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) -#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) -#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) - -#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -#define DSPARB_BEND_SHIFT 9 /* on 855 */ -#define DSPARB_AEND_SHIFT 0 - -#define DSPFW1 0x70034 -#define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) -#define DSPFW_CURSORB_SHIFT 16 -#define DSPFW_CURSORB_MASK (0x3f<<16) -#define DSPFW_PLANEB_SHIFT 8 -#define DSPFW_PLANEB_MASK (0x7f<<8) -#define DSPFW_PLANEA_MASK (0x7f) -#define DSPFW2 0x70038 -#define DSPFW_CURSORA_MASK 0x00003f00 -#define DSPFW_CURSORA_SHIFT 8 -#define DSPFW_PLANEC_MASK (0x7f) -#define DSPFW3 0x7003c -#define DSPFW_HPLL_SR_EN (1<<31) -#define DSPFW_CURSOR_SR_SHIFT 24 -#define PINEVIEW_SELF_REFRESH_EN (1<<30) -#define DSPFW_CURSOR_SR_MASK (0x3f<<24) -#define DSPFW_HPLL_CURSOR_SHIFT 16 -#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) -#define DSPFW_HPLL_SR_MASK (0x1ff) - -/* FIFO watermark sizes etc */ -#define G4X_FIFO_LINE_SIZE 64 -#define I915_FIFO_LINE_SIZE 64 -#define I830_FIFO_LINE_SIZE 32 - -#define G4X_FIFO_SIZE 127 -#define I965_FIFO_SIZE 512 -#define I945_FIFO_SIZE 127 -#define I915_FIFO_SIZE 95 -#define I855GM_FIFO_SIZE 127 /* In cachelines */ -#define I830_FIFO_SIZE 95 - -#define G4X_MAX_WM 0x3f -#define I915_MAX_WM 0x3f - -#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ -#define PINEVIEW_FIFO_LINE_SIZE 64 -#define PINEVIEW_MAX_WM 0x1ff -#define PINEVIEW_DFT_WM 0x3f -#define PINEVIEW_DFT_HPLLOFF_WM 0 -#define PINEVIEW_GUARD_WM 10 -#define PINEVIEW_CURSOR_FIFO 64 -#define PINEVIEW_CURSOR_MAX_WM 0x3f -#define PINEVIEW_CURSOR_DFT_WM 0 -#define PINEVIEW_CURSOR_GUARD_WM 5 - -#define I965_CURSOR_FIFO 64 -#define I965_CURSOR_MAX_WM 32 -#define I965_CURSOR_DFT_WM 8 - -/* define the Watermark register on Ironlake */ -#define WM0_PIPEA_ILK 0x45100 -#define WM0_PIPE_PLANE_MASK (0x7f<<16) -#define WM0_PIPE_PLANE_SHIFT 16 -#define WM0_PIPE_SPRITE_MASK (0x3f<<8) -#define WM0_PIPE_SPRITE_SHIFT 8 -#define WM0_PIPE_CURSOR_MASK (0x1f) - -#define WM0_PIPEB_ILK 0x45104 -#define WM0_PIPEC_IVB 0x45200 -#define WM1_LP_ILK 0x45108 -#define WM1_LP_SR_EN (1<<31) -#define WM1_LP_LATENCY_SHIFT 24 -#define WM1_LP_LATENCY_MASK (0x7f<<24) -#define WM1_LP_FBC_MASK (0xf<<20) -#define WM1_LP_FBC_SHIFT 20 -#define WM1_LP_SR_MASK (0x1ff<<8) -#define WM1_LP_SR_SHIFT 8 -#define WM1_LP_CURSOR_MASK (0x3f) -#define WM2_LP_ILK 0x4510c -#define WM2_LP_EN (1<<31) -#define WM3_LP_ILK 0x45110 -#define WM3_LP_EN (1<<31) -#define WM1S_LP_ILK 0x45120 -#define WM2S_LP_IVB 0x45124 -#define WM3S_LP_IVB 0x45128 -#define WM1S_LP_EN (1<<31) - -/* Memory latency timer register */ -#define MLTR_ILK 0x11222 -#define MLTR_WM1_SHIFT 0 -#define MLTR_WM2_SHIFT 8 -/* the unit of memory self-refresh latency time is 0.5us */ -#define ILK_SRLT_MASK 0x3f -#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) -#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) -#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) - -/* define the fifo size on Ironlake */ -#define ILK_DISPLAY_FIFO 128 -#define ILK_DISPLAY_MAXWM 64 -#define ILK_DISPLAY_DFTWM 8 -#define ILK_CURSOR_FIFO 32 -#define ILK_CURSOR_MAXWM 16 -#define ILK_CURSOR_DFTWM 8 - -#define ILK_DISPLAY_SR_FIFO 512 -#define ILK_DISPLAY_MAX_SRWM 0x1ff -#define ILK_DISPLAY_DFT_SRWM 0x3f -#define ILK_CURSOR_SR_FIFO 64 -#define ILK_CURSOR_MAX_SRWM 0x3f -#define ILK_CURSOR_DFT_SRWM 8 - -#define ILK_FIFO_LINE_SIZE 64 - -/* define the WM info on Sandybridge */ -#define SNB_DISPLAY_FIFO 128 -#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ -#define SNB_DISPLAY_DFTWM 8 -#define SNB_CURSOR_FIFO 32 -#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ -#define SNB_CURSOR_DFTWM 8 - -#define SNB_DISPLAY_SR_FIFO 512 -#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ -#define SNB_DISPLAY_DFT_SRWM 0x3f -#define SNB_CURSOR_SR_FIFO 64 -#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ -#define SNB_CURSOR_DFT_SRWM 8 - -#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ - -#define SNB_FIFO_LINE_SIZE 64 - - -/* the address where we get all kinds of latency value */ -#define SSKPD 0x5d10 -#define SSKPD_WM_MASK 0x3f -#define SSKPD_WM0_SHIFT 0 -#define SSKPD_WM1_SHIFT 8 -#define SSKPD_WM2_SHIFT 16 -#define SSKPD_WM3_SHIFT 24 - -#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) -#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) -#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) -#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) -#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) - -/* - * The two pipe frame counter registers are not synchronized, so - * reading a stable value is somewhat tricky. The following code - * should work: - * - * do { - * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; - * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); - * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); - * } while (high1 != high2); - * frame = (high1 << 8) | low1; - */ -#define _PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define _PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 -/* GM45+ just has to be different */ -#define _PIPEA_FRMCOUNT_GM45 0x70040 -#define _PIPEA_FLIPCOUNT_GM45 0x70044 -#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) - -/* Cursor A & B regs */ -#define _CURACNTR 0x70080 -/* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE 0x80000000 -#define CURSOR_GAMMA_ENABLE 0x40000000 -#define CURSOR_STRIDE_MASK 0x30000000 -#define CURSOR_FORMAT_SHIFT 24 -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) -/* New style CUR*CNTR flags */ -#define CURSOR_MODE 0x27 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_PIPE_SELECT (1 << 28) -#define MCURSOR_PIPE_A 0x00 -#define MCURSOR_PIPE_B (1 << 28) -#define MCURSOR_GAMMA_ENABLE (1 << 26) -#define _CURABASE 0x70084 -#define _CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 -#define CURSIZE 0x700a0 -#define _CURBCNTR 0x700c0 -#define _CURBBASE 0x700c4 -#define _CURBPOS 0x700c8 - -#define _CURBCNTR_IVB 0x71080 -#define _CURBBASE_IVB 0x71084 -#define _CURBPOS_IVB 0x71088 - -#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) -#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) -#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) - -#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) -#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) -#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) - -/* Display A control */ -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_SHIFT 24 -#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ -#define DISPPLANE_TILED (1<<10) -#define _DSPAADDR 0x70184 -#define _DSPASTRIDE 0x70188 -#define _DSPAPOS 0x7018C /* reserved */ -#define _DSPASIZE 0x70190 -#define _DSPASURF 0x7019C /* 965+ only */ -#define _DSPATILEOFF 0x701A4 /* 965+ only */ - -#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) -#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) -#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) -#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) -#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) -#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) -#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) - -/* VBIOS flags */ -#define SWF00 0x71410 -#define SWF01 0x71414 -#define SWF02 0x71418 -#define SWF03 0x7141c -#define SWF04 0x71420 -#define SWF05 0x71424 -#define SWF06 0x71428 -#define SWF10 0x70410 -#define SWF11 0x70414 -#define SWF14 0x71420 -#define SWF30 0x72414 -#define SWF31 0x72418 -#define SWF32 0x7241c - -/* Pipe B */ -#define _PIPEBDSL 0x71000 -#define _PIPEBCONF 0x71008 -#define _PIPEBSTAT 0x71024 -#define _PIPEBFRAMEHIGH 0x71040 -#define _PIPEBFRAMEPIXEL 0x71044 -#define _PIPEB_FRMCOUNT_GM45 0x71040 -#define _PIPEB_FLIPCOUNT_GM45 0x71044 - - -/* Display B control */ -#define _DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -#define _DSPBADDR 0x71184 -#define _DSPBSTRIDE 0x71188 -#define _DSPBPOS 0x7118C -#define _DSPBSIZE 0x71190 -#define _DSPBSURF 0x7119C -#define _DSPBTILEOFF 0x711A4 - -/* Sprite A control */ -#define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) -#define DVS_GAMMA_ENABLE (1<<30) -#define DVS_PIXFORMAT_MASK (3<<25) -#define DVS_FORMAT_YUV422 (0<<25) -#define DVS_FORMAT_RGBX101010 (1<<25) -#define DVS_FORMAT_RGBX888 (2<<25) -#define DVS_FORMAT_RGBX161616 (3<<25) -#define DVS_SOURCE_KEY (1<<22) -#define DVS_RGB_ORDER_XBGR (1<<20) -#define DVS_YUV_BYTE_ORDER_MASK (3<<16) -#define DVS_YUV_ORDER_YUYV (0<<16) -#define DVS_YUV_ORDER_UYVY (1<<16) -#define DVS_YUV_ORDER_YVYU (2<<16) -#define DVS_YUV_ORDER_VYUY (3<<16) -#define DVS_DEST_KEY (1<<2) -#define DVS_TRICKLE_FEED_DISABLE (1<<14) -#define DVS_TILED (1<<10) -#define _DVSALINOFF 0x72184 -#define _DVSASTRIDE 0x72188 -#define _DVSAPOS 0x7218c -#define _DVSASIZE 0x72190 -#define _DVSAKEYVAL 0x72194 -#define _DVSAKEYMSK 0x72198 -#define _DVSASURF 0x7219c -#define _DVSAKEYMAXVAL 0x721a0 -#define _DVSATILEOFF 0x721a4 -#define _DVSASURFLIVE 0x721ac -#define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE (1<<31) -#define DVS_FILTER_MASK (3<<29) -#define DVS_FILTER_MEDIUM (0<<29) -#define DVS_FILTER_ENHANCING (1<<29) -#define DVS_FILTER_SOFTENING (2<<29) -#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) -#define _DVSAGAMC 0x72300 - -#define _DVSBCNTR 0x73180 -#define _DVSBLINOFF 0x73184 -#define _DVSBSTRIDE 0x73188 -#define _DVSBPOS 0x7318c -#define _DVSBSIZE 0x73190 -#define _DVSBKEYVAL 0x73194 -#define _DVSBKEYMSK 0x73198 -#define _DVSBSURF 0x7319c -#define _DVSBKEYMAXVAL 0x731a0 -#define _DVSBTILEOFF 0x731a4 -#define _DVSBSURFLIVE 0x731ac -#define _DVSBSCALE 0x73204 -#define _DVSBGAMC 0x73300 - -#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) -#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) -#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) -#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) -#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) -#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) -#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) -#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) -#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) -#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) -#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) - -#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE (1<<31) -#define SPRITE_GAMMA_ENABLE (1<<30) -#define SPRITE_PIXFORMAT_MASK (7<<25) -#define SPRITE_FORMAT_YUV422 (0<<25) -#define SPRITE_FORMAT_RGBX101010 (1<<25) -#define SPRITE_FORMAT_RGBX888 (2<<25) -#define SPRITE_FORMAT_RGBX161616 (3<<25) -#define SPRITE_FORMAT_YUV444 (4<<25) -#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ -#define SPRITE_CSC_ENABLE (1<<24) -#define SPRITE_SOURCE_KEY (1<<22) -#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) -#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ -#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) -#define SPRITE_YUV_ORDER_YUYV (0<<16) -#define SPRITE_YUV_ORDER_UYVY (1<<16) -#define SPRITE_YUV_ORDER_YVYU (2<<16) -#define SPRITE_YUV_ORDER_VYUY (3<<16) -#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) -#define SPRITE_INT_GAMMA_ENABLE (1<<13) -#define SPRITE_TILED (1<<10) -#define SPRITE_DEST_KEY (1<<2) -#define _SPRA_LINOFF 0x70284 -#define _SPRA_STRIDE 0x70288 -#define _SPRA_POS 0x7028c -#define _SPRA_SIZE 0x70290 -#define _SPRA_KEYVAL 0x70294 -#define _SPRA_KEYMSK 0x70298 -#define _SPRA_SURF 0x7029c -#define _SPRA_KEYMAX 0x702a0 -#define _SPRA_TILEOFF 0x702a4 -#define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE (1<<31) -#define SPRITE_FILTER_MASK (3<<29) -#define SPRITE_FILTER_MEDIUM (0<<29) -#define SPRITE_FILTER_ENHANCING (1<<29) -#define SPRITE_FILTER_SOFTENING (2<<29) -#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) -#define _SPRA_GAMC 0x70400 - -#define _SPRB_CTL 0x71280 -#define _SPRB_LINOFF 0x71284 -#define _SPRB_STRIDE 0x71288 -#define _SPRB_POS 0x7128c -#define _SPRB_SIZE 0x71290 -#define _SPRB_KEYVAL 0x71294 -#define _SPRB_KEYMSK 0x71298 -#define _SPRB_SURF 0x7129c -#define _SPRB_KEYMAX 0x712a0 -#define _SPRB_TILEOFF 0x712a4 -#define _SPRB_SCALE 0x71304 -#define _SPRB_GAMC 0x71400 - -#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) -#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) -#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) -#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) -#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) -#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) -#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) -#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) -#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) -#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) -#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) -#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) - -/* VBIOS regs */ -#define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) -# define VGA_2X_MODE (1 << 30) -# define VGA_PIPE_B_SELECT (1 << 29) - -/* Ironlake */ - -#define CPU_VGACNTRL 0x41000 - -#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) -#define DIGITAL_PORTA_NO_DETECT (0 << 0) -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) -#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) - -/* refresh rate hardware control */ -#define RR_HW_CTL 0x45300 -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 - -#define FDI_PLL_BIOS_0 0x46000 -#define FDI_PLL_FB_CLOCK_MASK 0xff -#define FDI_PLL_BIOS_1 0x46004 -#define FDI_PLL_BIOS_2 0x46008 -#define DISPLAY_PORT_PLL_BIOS_0 0x4600c -#define DISPLAY_PORT_PLL_BIOS_1 0x46010 -#define DISPLAY_PORT_PLL_BIOS_2 0x46014 - -#define PCH_DSPCLK_GATE_D 0x42020 -# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) -# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) -# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) -# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) - -#define PCH_3DCGDIS0 0x46020 -# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) -# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) - -#define PCH_3DCGDIS1 0x46024 -# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) - -#define FDI_PLL_FREQ_CTL 0x46030 -#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) -#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 -#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff - - -#define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 -#define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 0x60034 -#define PIPE_DATA_N1_OFFSET 0 - -#define _PIPEA_DATA_M2 0x60038 -#define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 0x6003c -#define PIPE_DATA_N2_OFFSET 0 - -#define _PIPEA_LINK_M1 0x60040 -#define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 0x60044 -#define PIPE_LINK_N1_OFFSET 0 - -#define _PIPEA_LINK_M2 0x60048 -#define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 0x6004c -#define PIPE_LINK_N2_OFFSET 0 - -/* PIPEB timing regs are same start from 0x61000 */ - -#define _PIPEB_DATA_M1 0x61030 -#define _PIPEB_DATA_N1 0x61034 - -#define _PIPEB_DATA_M2 0x61038 -#define _PIPEB_DATA_N2 0x6103c - -#define _PIPEB_LINK_M1 0x61040 -#define _PIPEB_LINK_N1 0x61044 - -#define _PIPEB_LINK_M2 0x61048 -#define _PIPEB_LINK_N2 0x6104c - -#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) -#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) -#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2) -#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2) -#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1) -#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1) -#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2) -#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2) - -/* CPU panel fitter */ -/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_ENABLE (1<<31) -#define PF_FILTER_MASK (3<<23) -#define PF_FILTER_PROGRAMMED (0<<23) -#define PF_FILTER_MED_3x3 (1<<23) -#define PF_FILTER_EDGE_ENHANCE (2<<23) -#define PF_FILTER_EDGE_SOFTEN (3<<23) -#define _PFA_WIN_SZ 0x68074 -#define _PFB_WIN_SZ 0x68874 -#define _PFA_WIN_POS 0x68070 -#define _PFB_WIN_POS 0x68870 -#define _PFA_VSCALE 0x68084 -#define _PFB_VSCALE 0x68884 -#define _PFA_HSCALE 0x68090 -#define _PFB_HSCALE 0x68890 - -#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) -#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) -#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) -#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) -#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) - -/* legacy palette */ -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 -#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) - -/* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) -#define DE_SPRITEB_FLIP_DONE (1 << 29) -#define DE_SPRITEA_FLIP_DONE (1 << 28) -#define DE_PLANEB_FLIP_DONE (1 << 27) -#define DE_PLANEA_FLIP_DONE (1 << 26) -#define DE_PCU_EVENT (1 << 25) -#define DE_GTT_FAULT (1 << 24) -#define DE_POISON (1 << 23) -#define DE_PERFORM_COUNTER (1 << 22) -#define DE_PCH_EVENT (1 << 21) -#define DE_AUX_CHANNEL_A (1 << 20) -#define DE_DP_A_HOTPLUG (1 << 19) -#define DE_GSE (1 << 18) -#define DE_PIPEB_VBLANK (1 << 15) -#define DE_PIPEB_EVEN_FIELD (1 << 14) -#define DE_PIPEB_ODD_FIELD (1 << 13) -#define DE_PIPEB_LINE_COMPARE (1 << 12) -#define DE_PIPEB_VSYNC (1 << 11) -#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) -#define DE_PIPEA_VBLANK (1 << 7) -#define DE_PIPEA_EVEN_FIELD (1 << 6) -#define DE_PIPEA_ODD_FIELD (1 << 5) -#define DE_PIPEA_LINE_COMPARE (1 << 4) -#define DE_PIPEA_VSYNC (1 << 3) -#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) - -/* More Ivybridge lolz */ -#define DE_ERR_DEBUG_IVB (1<<30) -#define DE_GSE_IVB (1<<29) -#define DE_PCH_EVENT_IVB (1<<28) -#define DE_DP_A_HOTPLUG_IVB (1<<27) -#define DE_AUX_CHANNEL_A_IVB (1<<26) -#define DE_SPRITEB_FLIP_DONE_IVB (1<<9) -#define DE_SPRITEA_FLIP_DONE_IVB (1<<4) -#define DE_PLANEB_FLIP_DONE_IVB (1<<8) -#define DE_PLANEA_FLIP_DONE_IVB (1<<3) -#define DE_PIPEB_VBLANK_IVB (1<<5) -#define DE_PIPEA_VBLANK_IVB (1<<0) - -#define DEISR 0x44000 -#define DEIMR 0x44004 -#define DEIIR 0x44008 -#define DEIER 0x4400c - -/* GT interrupt */ -#define GT_PIPE_NOTIFY (1 << 4) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) -#define GT_BSD_USER_INTERRUPT (1 << 5) -#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) -#define GT_BLT_USER_INTERRUPT (1 << 22) - -#define GTISR 0x44010 -#define GTIMR 0x44014 -#define GTIIR 0x44018 -#define GTIER 0x4401c - -#define ILK_DISPLAY_CHICKEN2 0x42004 -/* Required on all Ironlake and Sandybridge according to the B-Spec. */ -#define ILK_ELPIN_409_SELECT (1 << 25) -#define ILK_DPARB_GATE (1<<22) -#define ILK_VSDPFD_FULL (1<<21) -#define ILK_DISPLAY_CHICKEN_FUSES 0x42014 -#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) -#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) -#define ILK_DISPLAY_DEBUG_DISABLE (1<<29) -#define ILK_HDCP_DISABLE (1<<25) -#define ILK_eDP_A_DISABLE (1<<24) -#define ILK_DESKTOP (1<<23) -#define ILK_DSPCLK_GATE 0x42020 -#define IVB_VRHUNIT_CLK_GATE (1<<28) -#define ILK_DPARB_CLK_GATE (1<<5) -#define ILK_DPFD_CLK_GATE (1<<7) - -/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ -#define ILK_CLK_FBC (1<<7) -#define ILK_DPFC_DIS1 (1<<8) -#define ILK_DPFC_DIS2 (1<<9) - -#define IVB_CHICKEN3 0x4200c -# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) -# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) - -#define DISP_ARB_CTL 0x45000 -#define DISP_TILE_SURFACE_SWIZZLING (1<<13) -#define DISP_FBC_WM_DIS (1<<15) - -/* GEN7 chicken */ -#define GEN7_COMMON_SLICE_CHICKEN1 0x7010 -# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) - -#define GEN7_L3CNTLREG1 0xB01C -#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C - -#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 -#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 - -/* WaCatErrorRejectionIssue */ -#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 -#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) - -/* PCH */ - -/* south display engine interrupt */ -#define SDE_AUDIO_POWER_D (1 << 27) -#define SDE_AUDIO_POWER_C (1 << 26) -#define SDE_AUDIO_POWER_B (1 << 25) -#define SDE_AUDIO_POWER_SHIFT (25) -#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) -#define SDE_GMBUS (1 << 24) -#define SDE_AUDIO_HDCP_TRANSB (1 << 23) -#define SDE_AUDIO_HDCP_TRANSA (1 << 22) -#define SDE_AUDIO_HDCP_MASK (3 << 22) -#define SDE_AUDIO_TRANSB (1 << 21) -#define SDE_AUDIO_TRANSA (1 << 20) -#define SDE_AUDIO_TRANS_MASK (3 << 20) -#define SDE_POISON (1 << 19) -/* 18 reserved */ -#define SDE_FDI_RXB (1 << 17) -#define SDE_FDI_RXA (1 << 16) -#define SDE_FDI_MASK (3 << 16) -#define SDE_AUXD (1 << 15) -#define SDE_AUXC (1 << 14) -#define SDE_AUXB (1 << 13) -#define SDE_AUX_MASK (7 << 13) -/* 12 reserved */ -#define SDE_CRT_HOTPLUG (1 << 11) -#define SDE_PORTD_HOTPLUG (1 << 10) -#define SDE_PORTC_HOTPLUG (1 << 9) -#define SDE_PORTB_HOTPLUG (1 << 8) -#define SDE_SDVOB_HOTPLUG (1 << 6) -#define SDE_HOTPLUG_MASK (0xf << 8) -#define SDE_TRANSB_CRC_DONE (1 << 5) -#define SDE_TRANSB_CRC_ERR (1 << 4) -#define SDE_TRANSB_FIFO_UNDER (1 << 3) -#define SDE_TRANSA_CRC_DONE (1 << 2) -#define SDE_TRANSA_CRC_ERR (1 << 1) -#define SDE_TRANSA_FIFO_UNDER (1 << 0) -#define SDE_TRANS_MASK (0x3f) -/* CPT */ -#define SDE_CRT_HOTPLUG_CPT (1 << 19) -#define SDE_PORTD_HOTPLUG_CPT (1 << 23) -#define SDE_PORTC_HOTPLUG_CPT (1 << 22) -#define SDE_PORTB_HOTPLUG_CPT (1 << 21) -#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ - SDE_PORTD_HOTPLUG_CPT | \ - SDE_PORTC_HOTPLUG_CPT | \ - SDE_PORTB_HOTPLUG_CPT) - -#define SDEISR 0xc4000 -#define SDEIMR 0xc4004 -#define SDEIIR 0xc4008 -#define SDEIER 0xc400c - -/* digital port hotplug */ -#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ -#define PORTD_HOTPLUG_ENABLE (1 << 20) -#define PORTD_PULSE_DURATION_2ms (0) -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) -#define PORTD_PULSE_DURATION_6ms (2 << 18) -#define PORTD_PULSE_DURATION_100ms (3 << 18) -#define PORTD_PULSE_DURATION_MASK (3 << 18) -#define PORTD_HOTPLUG_NO_DETECT (0) -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) -#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) -#define PORTC_HOTPLUG_ENABLE (1 << 12) -#define PORTC_PULSE_DURATION_2ms (0) -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) -#define PORTC_PULSE_DURATION_6ms (2 << 10) -#define PORTC_PULSE_DURATION_100ms (3 << 10) -#define PORTC_PULSE_DURATION_MASK (3 << 10) -#define PORTC_HOTPLUG_NO_DETECT (0) -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) -#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) -#define PORTB_HOTPLUG_ENABLE (1 << 4) -#define PORTB_PULSE_DURATION_2ms (0) -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) -#define PORTB_PULSE_DURATION_6ms (2 << 2) -#define PORTB_PULSE_DURATION_100ms (3 << 2) -#define PORTB_PULSE_DURATION_MASK (3 << 2) -#define PORTB_HOTPLUG_NO_DETECT (0) -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) -#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) - -#define PCH_GPIOA 0xc5010 -#define PCH_GPIOB 0xc5014 -#define PCH_GPIOC 0xc5018 -#define PCH_GPIOD 0xc501c -#define PCH_GPIOE 0xc5020 -#define PCH_GPIOF 0xc5024 - -#define PCH_GMBUS0 0xc5100 -#define PCH_GMBUS1 0xc5104 -#define PCH_GMBUS2 0xc5108 -#define PCH_GMBUS3 0xc510c -#define PCH_GMBUS4 0xc5110 -#define PCH_GMBUS5 0xc5120 - -#define _PCH_DPLL_A 0xc6014 -#define _PCH_DPLL_B 0xc6018 -#define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) - -#define _PCH_FPA0 0xc6040 -#define FP_CB_TUNE (0x3<<22) -#define _PCH_FPA1 0xc6044 -#define _PCH_FPB0 0xc6048 -#define _PCH_FPB1 0xc604c -#define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) -#define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1) - -#define PCH_DPLL_TEST 0xc606c - -#define PCH_DREF_CONTROL 0xC6200 -#define DREF_CONTROL_MASK 0x7fc3 -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) -#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) -#define DREF_SSC_SOURCE_DISABLE (0<<11) -#define DREF_SSC_SOURCE_ENABLE (2<<11) -#define DREF_SSC_SOURCE_MASK (3<<11) -#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) -#define DREF_NONSPREAD_CK505_ENABLE (1<<9) -#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) -#define DREF_NONSPREAD_SOURCE_MASK (3<<9) -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) -#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) -#define DREF_SSC4_DOWNSPREAD (0<<6) -#define DREF_SSC4_CENTERSPREAD (1<<6) -#define DREF_SSC1_DISABLE (0<<1) -#define DREF_SSC1_ENABLE (1<<1) -#define DREF_SSC4_DISABLE (0) -#define DREF_SSC4_ENABLE (1) - -#define PCH_RAWCLK_FREQ 0xc6204 -#define FDL_TP1_TIMER_SHIFT 12 -#define FDL_TP1_TIMER_MASK (3<<12) -#define FDL_TP2_TIMER_SHIFT 10 -#define FDL_TP2_TIMER_MASK (3<<10) -#define RAWCLK_FREQ_MASK 0x3ff - -#define PCH_DPLL_TMR_CFG 0xc6208 - -#define PCH_SSC4_PARMS 0xc6210 -#define PCH_SSC4_AUX_PARMS 0xc6214 - -#define PCH_DPLL_SEL 0xc7000 -#define TRANSA_DPLL_ENABLE (1<<3) -#define TRANSA_DPLLB_SEL (1<<0) -#define TRANSA_DPLLA_SEL 0 -#define TRANSB_DPLL_ENABLE (1<<7) -#define TRANSB_DPLLB_SEL (1<<4) -#define TRANSB_DPLLA_SEL (0) -#define TRANSC_DPLL_ENABLE (1<<11) -#define TRANSC_DPLLB_SEL (1<<8) -#define TRANSC_DPLLA_SEL (0) - -/* transcoder */ - -#define _TRANS_HTOTAL_A 0xe0000 -#define TRANS_HTOTAL_SHIFT 16 -#define TRANS_HACTIVE_SHIFT 0 -#define _TRANS_HBLANK_A 0xe0004 -#define TRANS_HBLANK_END_SHIFT 16 -#define TRANS_HBLANK_START_SHIFT 0 -#define _TRANS_HSYNC_A 0xe0008 -#define TRANS_HSYNC_END_SHIFT 16 -#define TRANS_HSYNC_START_SHIFT 0 -#define _TRANS_VTOTAL_A 0xe000c -#define TRANS_VTOTAL_SHIFT 16 -#define TRANS_VACTIVE_SHIFT 0 -#define _TRANS_VBLANK_A 0xe0010 -#define TRANS_VBLANK_END_SHIFT 16 -#define TRANS_VBLANK_START_SHIFT 0 -#define _TRANS_VSYNC_A 0xe0014 -#define TRANS_VSYNC_END_SHIFT 16 -#define TRANS_VSYNC_START_SHIFT 0 -#define _TRANS_VSYNCSHIFT_A 0xe0028 - -#define _TRANSA_DATA_M1 0xe0030 -#define _TRANSA_DATA_N1 0xe0034 -#define _TRANSA_DATA_M2 0xe0038 -#define _TRANSA_DATA_N2 0xe003c -#define _TRANSA_DP_LINK_M1 0xe0040 -#define _TRANSA_DP_LINK_N1 0xe0044 -#define _TRANSA_DP_LINK_M2 0xe0048 -#define _TRANSA_DP_LINK_N2 0xe004c - -/* Per-transcoder DIP controls */ - -#define _VIDEO_DIP_CTL_A 0xe0200 -#define _VIDEO_DIP_DATA_A 0xe0208 -#define _VIDEO_DIP_GCP_A 0xe0210 - -#define _VIDEO_DIP_CTL_B 0xe1200 -#define _VIDEO_DIP_DATA_B 0xe1208 -#define _VIDEO_DIP_GCP_B 0xe1210 - -#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) -#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) -#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) - -#define _TRANS_HTOTAL_B 0xe1000 -#define _TRANS_HBLANK_B 0xe1004 -#define _TRANS_HSYNC_B 0xe1008 -#define _TRANS_VTOTAL_B 0xe100c -#define _TRANS_VBLANK_B 0xe1010 -#define _TRANS_VSYNC_B 0xe1014 -#define _TRANS_VSYNCSHIFT_B 0xe1028 - -#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) -#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) -#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) -#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) -#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) -#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) -#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ - _TRANS_VSYNCSHIFT_B) - -#define _TRANSB_DATA_M1 0xe1030 -#define _TRANSB_DATA_N1 0xe1034 -#define _TRANSB_DATA_M2 0xe1038 -#define _TRANSB_DATA_N2 0xe103c -#define _TRANSB_DP_LINK_M1 0xe1040 -#define _TRANSB_DP_LINK_N1 0xe1044 -#define _TRANSB_DP_LINK_M2 0xe1048 -#define _TRANSB_DP_LINK_N2 0xe104c - -#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) -#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) -#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) -#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) -#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) -#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) -#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) -#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) - -#define _TRANSACONF 0xf0008 -#define _TRANSBCONF 0xf1008 -#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) -#define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) -#define TRANS_STATE_MASK (1<<30) -#define TRANS_STATE_DISABLE (0<<30) -#define TRANS_STATE_ENABLE (1<<30) -#define TRANS_FSYNC_DELAY_HB1 (0<<27) -#define TRANS_FSYNC_DELAY_HB2 (1<<27) -#define TRANS_FSYNC_DELAY_HB3 (2<<27) -#define TRANS_FSYNC_DELAY_HB4 (3<<27) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_VIDEO_AUDIO (0<<26) -#define TRANS_INTERLACE_MASK (7<<21) -#define TRANS_PROGRESSIVE (0<<21) -#define TRANS_INTERLACED (3<<21) -#define TRANS_LEGACY_INTERLACED_ILK (2<<21) -#define TRANS_8BPC (0<<5) -#define TRANS_10BPC (1<<5) -#define TRANS_6BPC (2<<5) -#define TRANS_12BPC (3<<5) - -#define _TRANSA_CHICKEN2 0xf0064 -#define _TRANSB_CHICKEN2 0xf1064 -#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) - -#define SOUTH_CHICKEN1 0xc2000 -#define FDIA_PHASE_SYNC_SHIFT_OVR 19 -#define FDIA_PHASE_SYNC_SHIFT_EN 18 -#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) -#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) -#define SOUTH_CHICKEN2 0xc2004 -#define DPLS_EDP_PPS_FIX_DIS (1<<0) - -#define _FDI_RXA_CHICKEN 0xc200c -#define _FDI_RXB_CHICKEN 0xc2010 -#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) -#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) -#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) - -#define SOUTH_DSPCLK_GATE_D 0xc2020 -#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) - -/* CPU: FDI_TX */ -#define _FDI_TXA_CTL 0x60100 -#define _FDI_TXB_CTL 0x61100 -#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) -#define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) -#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) -#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) -#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) -#define FDI_LINK_TRAIN_NONE (3<<28) -#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) -#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) -/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. - SNB has different settings. */ -/* SNB A-stepping */ -#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) -#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) -#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) -#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) -/* SNB B-stepping */ -#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) -#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) -#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) -#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) -#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) -#define FDI_DP_PORT_WIDTH_X1 (0<<19) -#define FDI_DP_PORT_WIDTH_X2 (1<<19) -#define FDI_DP_PORT_WIDTH_X3 (2<<19) -#define FDI_DP_PORT_WIDTH_X4 (3<<19) -#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) -/* Ironlake: hardwired to 1 */ -#define FDI_TX_PLL_ENABLE (1<<14) - -/* Ivybridge has different bits for lolz */ -#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) -#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) -#define FDI_LINK_TRAIN_NONE_IVB (3<<8) - -/* both Tx and Rx */ -#define FDI_COMPOSITE_SYNC (1<<11) -#define FDI_LINK_TRAIN_AUTO (1<<10) -#define FDI_SCRAMBLING_ENABLE (0<<7) -#define FDI_SCRAMBLING_DISABLE (1<<7) - -/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ -#define _FDI_RXA_CTL 0xf000c -#define _FDI_RXB_CTL 0xf100c -#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) -/* train, dp width same as FDI_TX */ -#define FDI_FS_ERRC_ENABLE (1<<27) -#define FDI_FE_ERRC_ENABLE (1<<26) -#define FDI_DP_PORT_WIDTH_X8 (7<<19) -#define FDI_8BPC (0<<16) -#define FDI_10BPC (1<<16) -#define FDI_6BPC (2<<16) -#define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) -#define FDI_DMI_LINK_REVERSE_MASK (1<<14) -#define FDI_RX_PLL_ENABLE (1<<13) -#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) -#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) -#define FDI_FS_ERR_REPORT_ENABLE (1<<9) -#define FDI_FE_ERR_REPORT_ENABLE (1<<8) -#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) -#define FDI_PCDCLK (1<<4) -/* CPT */ -#define FDI_AUTO_TRAINING (1<<10) -#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) -#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) -#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) -#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) - -#define _FDI_RXA_MISC 0xf0010 -#define _FDI_RXB_MISC 0xf1010 -#define _FDI_RXA_TUSIZE1 0xf0030 -#define _FDI_RXA_TUSIZE2 0xf0038 -#define _FDI_RXB_TUSIZE1 0xf1030 -#define _FDI_RXB_TUSIZE2 0xf1038 -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) -#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) -#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) - -/* FDI_RX interrupt register format */ -#define FDI_RX_INTER_LANE_ALIGN (1<<10) -#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ -#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ -#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) -#define FDI_RX_FS_CODE_ERR (1<<6) -#define FDI_RX_FE_CODE_ERR (1<<5) -#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) -#define FDI_RX_HDCP_LINK_FAIL (1<<3) -#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) -#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) -#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) - -#define _FDI_RXA_IIR 0xf0014 -#define _FDI_RXA_IMR 0xf0018 -#define _FDI_RXB_IIR 0xf1014 -#define _FDI_RXB_IMR 0xf1018 -#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) -#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) - -#define FDI_PLL_CTL_1 0xfe000 -#define FDI_PLL_CTL_2 0xfe004 - -/* CRT */ -#define PCH_ADPA 0xe1100 -#define ADPA_TRANS_SELECT_MASK (1<<30) -#define ADPA_TRANS_A_SELECT 0 -#define ADPA_TRANS_B_SELECT (1<<30) -#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ -#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) -#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) -#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) -#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) -#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) -#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) -#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) -#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) -#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) -#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) -#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) -#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) -#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) -#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) -#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) - -/* or SDVOB */ -#define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) -#define TRANSCODER(pipe) ((pipe) << 30) -#define TRANSCODER_CPT(pipe) ((pipe) << 29) -#define TRANSCODER_MASK (1 << 30) -#define TRANSCODER_MASK_CPT (3 << 29) -#define COLOR_FORMAT_8bpc (0) -#define COLOR_FORMAT_12bpc (3 << 26) -#define SDVOB_HOTPLUG_ENABLE (1 << 23) -#define SDVO_ENCODING (0) -#define TMDS_ENCODING (2 << 10) -#define NULL_PACKET_VSYNC_ENABLE (1 << 9) -/* CPT */ -#define HDMI_MODE_SELECT (1 << 9) -#define DVI_MODE_SELECT (0) -#define SDVOB_BORDER_ENABLE (1 << 7) -#define AUDIO_ENABLE (1 << 6) -#define VSYNC_ACTIVE_HIGH (1 << 4) -#define HSYNC_ACTIVE_HIGH (1 << 3) -#define PORT_DETECTED (1 << 2) - -/* PCH SDVOB multiplex with HDMIB */ -#define PCH_SDVOB HDMIB - -#define HDMIC 0xe1150 -#define HDMID 0xe1160 - -#define PCH_LVDS 0xe1180 -#define LVDS_DETECTED (1 << 1) - -#define BLC_PWM_CPU_CTL2 0x48250 -#define PWM_ENABLE (1 << 31) -#define PWM_PIPE_A (0 << 29) -#define PWM_PIPE_B (1 << 29) -#define BLC_PWM_CPU_CTL 0x48254 - -#define BLC_PWM_PCH_CTL1 0xc8250 -#define PWM_PCH_ENABLE (1 << 31) -#define PWM_POLARITY_ACTIVE_LOW (1 << 29) -#define PWM_POLARITY_ACTIVE_HIGH (0 << 29) -#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) -#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) - -#define BLC_PWM_PCH_CTL2 0xc8254 - -#define PCH_PP_STATUS 0xc7200 -#define PCH_PP_CONTROL 0xc7204 -#define PANEL_UNLOCK_REGS (0xabcd << 16) -#define PANEL_UNLOCK_MASK (0xffff << 16) -#define EDP_FORCE_VDD (1 << 3) -#define EDP_BLC_ENABLE (1 << 2) -#define PANEL_POWER_RESET (1 << 1) -#define PANEL_POWER_OFF (0 << 0) -#define PANEL_POWER_ON (1 << 0) -#define PCH_PP_ON_DELAYS 0xc7208 -#define PANEL_PORT_SELECT_MASK (3 << 30) -#define PANEL_PORT_SELECT_LVDS (0 << 30) -#define PANEL_PORT_SELECT_DPA (1 << 30) -#define EDP_PANEL (1 << 30) -#define PANEL_PORT_SELECT_DPC (2 << 30) -#define PANEL_PORT_SELECT_DPD (3 << 30) -#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) -#define PANEL_POWER_UP_DELAY_SHIFT 16 -#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) -#define PANEL_LIGHT_ON_DELAY_SHIFT 0 - -#define PCH_PP_OFF_DELAYS 0xc720c -#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) -#define PANEL_POWER_DOWN_DELAY_SHIFT 16 -#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) -#define PANEL_LIGHT_OFF_DELAY_SHIFT 0 - -#define PCH_PP_DIVISOR 0xc7210 -#define PP_REFERENCE_DIVIDER_MASK (0xffffff00) -#define PP_REFERENCE_DIVIDER_SHIFT 8 -#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) -#define PANEL_POWER_CYCLE_DELAY_SHIFT 0 - -#define PCH_DP_B 0xe4100 -#define PCH_DPB_AUX_CH_CTL 0xe4110 -#define PCH_DPB_AUX_CH_DATA1 0xe4114 -#define PCH_DPB_AUX_CH_DATA2 0xe4118 -#define PCH_DPB_AUX_CH_DATA3 0xe411c -#define PCH_DPB_AUX_CH_DATA4 0xe4120 -#define PCH_DPB_AUX_CH_DATA5 0xe4124 - -#define PCH_DP_C 0xe4200 -#define PCH_DPC_AUX_CH_CTL 0xe4210 -#define PCH_DPC_AUX_CH_DATA1 0xe4214 -#define PCH_DPC_AUX_CH_DATA2 0xe4218 -#define PCH_DPC_AUX_CH_DATA3 0xe421c -#define PCH_DPC_AUX_CH_DATA4 0xe4220 -#define PCH_DPC_AUX_CH_DATA5 0xe4224 - -#define PCH_DP_D 0xe4300 -#define PCH_DPD_AUX_CH_CTL 0xe4310 -#define PCH_DPD_AUX_CH_DATA1 0xe4314 -#define PCH_DPD_AUX_CH_DATA2 0xe4318 -#define PCH_DPD_AUX_CH_DATA3 0xe431c -#define PCH_DPD_AUX_CH_DATA4 0xe4320 -#define PCH_DPD_AUX_CH_DATA5 0xe4324 - -/* CPT */ -#define PORT_TRANS_A_SEL_CPT 0 -#define PORT_TRANS_B_SEL_CPT (1<<29) -#define PORT_TRANS_C_SEL_CPT (2<<29) -#define PORT_TRANS_SEL_MASK (3<<29) -#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) - -#define TRANS_DP_CTL_A 0xe0300 -#define TRANS_DP_CTL_B 0xe1300 -#define TRANS_DP_CTL_C 0xe2300 -#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) -#define TRANS_DP_OUTPUT_ENABLE (1<<31) -#define TRANS_DP_PORT_SEL_B (0<<29) -#define TRANS_DP_PORT_SEL_C (1<<29) -#define TRANS_DP_PORT_SEL_D (2<<29) -#define TRANS_DP_PORT_SEL_NONE (3<<29) -#define TRANS_DP_PORT_SEL_MASK (3<<29) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_ENH_FRAMING (1<<18) -#define TRANS_DP_8BPC (0<<9) -#define TRANS_DP_10BPC (1<<9) -#define TRANS_DP_6BPC (2<<9) -#define TRANS_DP_12BPC (3<<9) -#define TRANS_DP_BPC_MASK (3<<9) -#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) -#define TRANS_DP_VSYNC_ACTIVE_LOW 0 -#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) -#define TRANS_DP_HSYNC_ACTIVE_LOW 0 -#define TRANS_DP_SYNC_MASK (3<<3) - -/* SNB eDP training params */ -/* SNB A-stepping */ -#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) -#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) -#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) -#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) -/* SNB B-stepping */ -#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) -#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) -#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) -#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) -#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) -#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) - -/* IVB */ -#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) -#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) -#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) -#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) -#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) -#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) -#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 << 22) - -/* legacy values */ -#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) -#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) -#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) -#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) -#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) - -#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) - -#define FORCEWAKE 0xA18C -#define FORCEWAKE_ACK 0x130090 -#define FORCEWAKE_MT 0xa188 /* multi-threaded */ -#define FORCEWAKE_MT_ACK 0x130040 -#define ECOBUS 0xa180 -#define FORCEWAKE_MT_ENABLE (1<<5) - -#define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 -#define GT_FIFO_OVFERR (1<<2) -#define GT_FIFO_IAWRERR (1<<1) -#define GT_FIFO_IARDERR (1<<0) - -#define GT_FIFO_FREE_ENTRIES 0x120008 -#define GT_FIFO_NUM_RESERVED_ENTRIES 20 - -#define GEN6_UCGCTL1 0x9400 -# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) - -#define GEN6_UCGCTL2 0x9404 -# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) -# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) -# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) - -#define GEN6_RPNSWREQ 0xA008 -#define GEN6_TURBO_DISABLE (1<<31) -#define GEN6_FREQUENCY(x) ((x)<<25) -#define GEN6_OFFSET(x) ((x)<<19) -#define GEN6_AGGRESSIVE_TURBO (0<<15) -#define GEN6_RC_VIDEO_FREQ 0xA00C -#define GEN6_RC_CONTROL 0xA090 -#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) -#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) -#define GEN6_RC_CTL_RC6_ENABLE (1<<18) -#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) -#define GEN6_RC_CTL_RC7_ENABLE (1<<22) -#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) -#define GEN6_RC_CTL_HW_ENABLE (1<<31) -#define GEN6_RP_DOWN_TIMEOUT 0xA010 -#define GEN6_RP_INTERRUPT_LIMITS 0xA014 -#define GEN6_RPSTAT1 0xA01C -#define GEN6_CAGF_SHIFT 8 -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) -#define GEN6_RP_CONTROL 0xA024 -#define GEN6_RP_MEDIA_TURBO (1<<11) -#define GEN6_RP_MEDIA_MODE_MASK (3<<9) -#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) -#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) -#define GEN6_RP_MEDIA_HW_MODE (1<<9) -#define GEN6_RP_MEDIA_SW_MODE (0<<9) -#define GEN6_RP_MEDIA_IS_GFX (1<<8) -#define GEN6_RP_ENABLE (1<<7) -#define GEN6_RP_UP_IDLE_MIN (0x1<<3) -#define GEN6_RP_UP_BUSY_AVG (0x2<<3) -#define GEN6_RP_UP_BUSY_CONT (0x4<<3) -#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) -#define GEN6_RP_UP_THRESHOLD 0xA02C -#define GEN6_RP_DOWN_THRESHOLD 0xA030 -#define GEN6_RP_CUR_UP_EI 0xA050 -#define GEN6_CURICONT_MASK 0xffffff -#define GEN6_RP_CUR_UP 0xA054 -#define GEN6_CURBSYTAVG_MASK 0xffffff -#define GEN6_RP_PREV_UP 0xA058 -#define GEN6_RP_CUR_DOWN_EI 0xA05C -#define GEN6_CURIAVG_MASK 0xffffff -#define GEN6_RP_CUR_DOWN 0xA060 -#define GEN6_RP_PREV_DOWN 0xA064 -#define GEN6_RP_UP_EI 0xA068 -#define GEN6_RP_DOWN_EI 0xA06C -#define GEN6_RP_IDLE_HYSTERSIS 0xA070 -#define GEN6_RC_STATE 0xA094 -#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 -#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C -#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 -#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 -#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC -#define GEN6_RC_SLEEP 0xA0B0 -#define GEN6_RC1e_THRESHOLD 0xA0B4 -#define GEN6_RC6_THRESHOLD 0xA0B8 -#define GEN6_RC6p_THRESHOLD 0xA0BC -#define GEN6_RC6pp_THRESHOLD 0xA0C0 -#define GEN6_PMINTRMSK 0xA168 - -#define GEN6_PMISR 0x44020 -#define GEN6_PMIMR 0x44024 /* rps_lock */ -#define GEN6_PMIIR 0x44028 -#define GEN6_PMIER 0x4402C -#define GEN6_PM_MBOX_EVENT (1<<25) -#define GEN6_PM_THERMAL_EVENT (1<<24) -#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) -#define GEN6_PM_RP_UP_THRESHOLD (1<<5) -#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) -#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) -#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) -#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ - GEN6_PM_RP_DOWN_THRESHOLD | \ - GEN6_PM_RP_DOWN_TIMEOUT) - -#define GEN6_PCODE_MAILBOX 0x138124 -#define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 -#define GEN6_PCODE_DATA 0x138128 -#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 - -#define GEN6_GT_CORE_STATUS 0x138060 -#define GEN6_CORE_CPD_STATE_MASK (7<<4) -#define GEN6_RCn_MASK 7 -#define GEN6_RC0 0 -#define GEN6_RC3 2 -#define GEN6_RC6 3 -#define GEN6_RC7 4 - -#define G4X_AUD_VID_DID 0x62020 -#define INTEL_AUDIO_DEVCL 0x808629FB -#define INTEL_AUDIO_DEVBLC 0x80862801 -#define INTEL_AUDIO_DEVCTG 0x80862802 - -#define G4X_AUD_CNTL_ST 0x620B4 -#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) -#define G4X_ELDV_DEVCTG (1 << 14) -#define G4X_ELD_ADDR (0xf << 5) -#define G4X_ELD_ACK (1 << 4) -#define G4X_HDMIW_HDMIEDID 0x6210C - -#define IBX_HDMIW_HDMIEDID_A 0xE2050 -#define IBX_AUD_CNTL_ST_A 0xE20B4 -#define IBX_ELD_BUFFER_SIZE (0x1f << 10) -#define IBX_ELD_ADDRESS (0x1f << 5) -#define IBX_ELD_ACK (1 << 4) -#define IBX_AUD_CNTL_ST2 0xE20C0 -#define IBX_ELD_VALIDB (1 << 0) -#define IBX_CP_READYB (1 << 1) - -#define CPT_HDMIW_HDMIEDID_A 0xE5050 -#define CPT_AUD_CNTL_ST_A 0xE50B4 -#define CPT_AUD_CNTRL_ST2 0xE50C0 - -/* These are the 4 32-bit write offset registers for each stream - * output buffer. It determines the offset from the - * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. - */ -#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) - -#define IBX_AUD_CONFIG_A 0xe2000 -#define CPT_AUD_CONFIG_A 0xe5000 -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) -#define AUD_CONFIG_UPPER_N_SHIFT 20 -#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) -#define AUD_CONFIG_LOWER_N_SHIFT 4 -#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) - -#endif /* _I915_REG_H_ */ diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c deleted file mode 100644 index 3552867..0000000 --- a/src/mainboard/lenovo/x60/i915io.c +++ /dev/null @@ -1,2273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include "i915io.h" - -struct iodef iodefs[] = { -{V, 0,}, -{M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected 8192K stolen memory", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:AGP aperture is 256M @ 0xd0000000", 0x0, 0x0, 0}, -{M, 1, "[drm] Initialized drm 1.1.0 20060810", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon defaulting to kernel modesetting.", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon kernel modesetting enabled.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:setting latency timer to 64", 0x0, 0x0, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{R, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800, 0}, -{W, 1, "", RENDER_RING_BASE, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0xc, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x10, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x14, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x18, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x1c, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x4, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x8, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0xc, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x10, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0}, -{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 | 0x000f0202, 0}, -{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0}, -{M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0}, -{M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0}, -{M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0}, -{W, 1, "", VGACNTRL, VGA_DISP_DISABLE | 0x80000000, 0}, -{R, 1, "", PFIT_CONTROL, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 1, "", 0x5108, 0x00004a00, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x468000a1, 0}, -{R, 1, "", 0x5108, 0x00008a08, 0}, -{R, 1, "", 0x510c, 0xffffff00, 0}, -{R, 1, "", 0x5108, 0x00008a0c, 0}, -{R, 1, "", 0x510c, 0x00ffffff, 0}, -{R, 1, "", 0x5108, 0x00008a10, 0}, -{R, 1, "", 0x510c, 0x4000ae30, 0}, -{R, 1, "", 0x5108, 0x00008a14, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x00008a18, 0}, -{R, 1, "", 0x510c, 0x03010f00, 0}, -{R, 1, "", 0x5108, 0x00008a1c, 0}, -{R, 1, "", 0x510c, 0x78121980, 0}, -{R, 1, "", 0x5108, 0x00008a20, 0}, -{R, 1, "", 0x510c, 0x9175edea, 0}, -{R, 1, "", 0x5108, 0x00008a24, 0}, -{R, 1, "", 0x510c, 0x268b4f57, 0}, -{R, 1, "", 0x5108, 0x00008a28, 0}, -{R, 1, "", 0x510c, 0x21545021, 0}, -{R, 1, "", 0x5108, 0x00008a2c, 0}, -{R, 1, "", 0x510c, 0x01010008, 0}, -{R, 1, "", 0x5108, 0x00008a30, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a34, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a38, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a3c, 0}, -{R, 1, "", 0x510c, 0x15280101, 0}, -{R, 1, "", 0x5108, 0x00008a40, 0}, -{R, 1, "", 0x510c, 0x00414000, 0}, -{R, 1, "", 0x5108, 0x00008a44, 0}, -{R, 1, "", 0x510c, 0x88183026, 0}, -{R, 1, "", 0x5108, 0x00008a48, 0}, -{R, 1, "", 0x510c, 0xb9f60036, 0}, -{R, 1, "", 0x5108, 0x00008a4c, 0}, -{R, 1, "", 0x510c, 0x18000000, 0}, -{R, 1, "", 0x5108, 0x00008a50, 0}, -{R, 1, "", 0x510c, 0x400010ed, 0}, -{R, 1, "", 0x5108, 0x00008a54, 0}, -{R, 1, "", 0x510c, 0x30260041, 0}, -{R, 1, "", 0x5108, 0x00008a58, 0}, -{R, 1, "", 0x510c, 0x00368818, 0}, -{R, 1, "", 0x5108, 0x00008a5c, 0}, -{R, 1, "", 0x510c, 0x0000b9f6, 0}, -{R, 1, "", 0x5108, 0x00008a60, 0}, -{R, 1, "", 0x510c, 0x00001800, 0}, -{R, 1, "", 0x5108, 0x00008a64, 0}, -{R, 1, "", 0x510c, 0x61000f00, 0}, -{R, 1, "", 0x5108, 0x00008a68, 0}, -{R, 1, "", 0x510c, 0x43613243, 0}, -{R, 1, "", 0x5108, 0x00008a6c, 0}, -{R, 1, "", 0x510c, 0x00010f28, 0}, -{R, 1, "", 0x5108, 0x00008a70, 0}, -{R, 1, "", 0x510c, 0x4a58a34c, 0}, -{R, 1, "", 0x5108, 0x00008a74, 0}, -{R, 1, "", 0x510c, 0xfe000000, 0}, -{R, 1, "", 0x5108, 0x00008a78, 0}, -{R, 1, "", 0x510c, 0x4e544c00, 0}, -{R, 1, "", 0x5108, 0x00008a7c, 0}, -{R, 1, "", 0x510c, 0x58313231, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x304c2d4a, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x00000a37, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_CONTROL, 0x00000000, 0}, -{W, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{R, 2, "", BLC_PWM_CTL, 0x00000000, 0}, -{R, 2, "", DVOB, 0x00300000, 0}, -{R, 1, "", DVOC, 0x00300000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x08000000, 0}, -{R, 1, "", TV_DAC, 0x08000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{M, 1, "tsc:Refined TSC clocksource calibration:1662.499 MHz", 0x0, 0x0, 0}, -{W, 1, "", HWS_PGA, 0x352d2000, 0}, -{W, 1, "", PRB0_CTL, 0x00000000, 0}, -{M, 1, "Switching to clocksource tsc", 0x0, 0x0, 0}, -{W, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_START, 0x00000000, 0}, -{W, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_START, 0x00000000, 0}, -{R, 2, "", PRB0_HEAD, 0x00000000, 0}, -{R, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", 0x6104, 0x00000000, 0}, -{W, 1, "", 0x6104, 0x0000000b, 0}, -{W, 1, "", ECOSKPD, 0x00010000, 0}, -{M, 1, "[drm] initialized overlay support", 0x0, 0x0, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DSPACNTR, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", _DSPBCNTR, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", HWSTAM, 0x0000effe, 0}, -{W, 1, "", _PIPEASTAT, 0x00000000, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000000, 0}, -{W, 1, "", IMR, 0xffffffff, 0}, -{W, 1, "", IER, 0x00000000, 0}, -{W, 1, "", EMR, 0xffffffed, 0}, -{W, 1, "", IMR, 0xfffd73ae, 0}, -{W, 1, "", IER, 0x00028053, 0}, -{R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", 0x5100, 0x00000002, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 2, "", 0x5108, 0x00009c00, 0}, -{W, 1, "", 0x5104, 0x80000000, 0}, -{W, 1, "", 0x5104, 0x00000000, 0}, -{W, 2, "", 0x5100, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _FPA0, 0x00020e08, 0}, -{W, 1, "", _FPA1, 0x00020e08, 0}, -{W, 1, "", _DPLL_A, 0x14020003, 0}, -{W, 2, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{W, 1, "", _HBLANK_A, 0x06af04ff, 0}, -{W, 1, "", _HSYNC_A, 0x05d70557, 0}, -{W, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{W, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{W, 1, "", _VSYNC_A, 0x04090402, 0}, -{W, 1, "", _PIPEASRC, 0x04ff03ff, 0}, -{W, 1, "", _DSPBSIZE, 0x03ff04ff, 0}, -{W, 1, "", _DSPBPOS, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{R, 2, "", _PIPEASTAT, 0x00000000, 0}, -{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{R, 1, "", _PIPEASTAT, 0x00000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _DSPBCNTR, 0x40000000, 0}, -{R, 1, "", _DSPBCNTR, 0x40000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBSTRIDE, 0x00001400, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", FW_BLC, 0x011d011a, 0}, -{W, 1, "", FW_BLC2, 0x00000102, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{W, 1, "", TV_H_CTL_1, 0x00400359, 0}, -{W, 1, "", TV_H_CTL_2, 0x80480022, 0}, -{W, 1, "", TV_H_CTL_3, 0x007c0344, 0}, -{W, 1, "", TV_V_CTL_1, 0x00f01415, 0}, -{W, 1, "", TV_V_CTL_2, 0x00060607, 0}, -{W, 1, "", TV_V_CTL_3, 0x80120001, 0}, -{W, 1, "", TV_V_CTL_4, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_5, 0x000a00f0, 0}, -{W, 1, "", TV_V_CTL_6, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_7, 0x000a00f0, 0}, -{W, 1, "", TV_SC_CTL_1, 0xc1710087, 0}, -{W, 1, "", TV_SC_CTL_2, 0x6b405140, 0}, -{W, 1, "", TV_SC_CTL_3, 0x00000000, 0}, -{W, 1, "", TV_CSC_Y, 0x0332012d, 0}, -{W, 1, "", TV_CSC_Y2, 0x07d30104, 0}, -{W, 1, "", TV_CSC_U, 0x0733052d, 0}, -{W, 1, "", TV_CSC_U2, 0x05c70200, 0}, -{W, 1, "", TV_CSC_V, 0x0340030c, 0}, -{W, 1, "", TV_CSC_V2, 0x06d00200, 0}, -{W, 1, "", TV_CLR_KNOBS, 0x00606000, 0}, -{W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEADSL, 0x0000029e, 0}, -{R, 3, "", _PIPEADSL, 0x000003ff, 0}, -{W, 1, "", _PFA_CTL_1, 0x80000000, 0}, -{W, 1, "", _PFA_WIN_POS, 0x00360024, 0}, -{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", TV_H_LUMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_LUMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_LUMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_LUMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_LUMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_LUMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_LUMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_LUMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_LUMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_LUMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_LUMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_LUMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_LUMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_LUMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_LUMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_LUMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_LUMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_LUMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_LUMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_LUMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68180, 0x3ae0b160, 0}, -{W, 1, "", 0x68184, 0x2b001810, 0}, -{W, 1, "", 0x68188, 0xb0c03120, 0}, -{W, 1, "", 0x6818c, 0xb140b020, 0}, -{W, 1, "", 0x68190, 0x18283ba0, 0}, -{W, 1, "", 0x68194, 0x30c02a80, 0}, -{W, 1, "", 0x68198, 0xb020b0a0, 0}, -{W, 1, "", 0x6819c, 0x3c60b140, 0}, -{W, 1, "", 0x681a0, 0x2a201838, 0}, -{W, 1, "", 0x681a4, 0xb0a03080, 0}, -{W, 1, "", 0x681a8, 0xb120b020, 0}, -{W, 1, "", 0x681ac, 0x18383d20, 0}, -{W, 1, "", 0x681b0, 0x304029c0, 0}, -{W, 1, "", 0x681b4, 0xb040b080, 0}, -{W, 1, "", 0x681b8, 0x3de0b100, 0}, -{W, 1, "", 0x681bc, 0x29601848, 0}, -{W, 1, "", 0x681c0, 0xb0803000, 0}, -{W, 1, "", 0x681c4, 0xb100b040, 0}, -{W, 1, "", 0x681c8, 0x18483ec0, 0}, -{W, 1, "", 0x681cc, 0xb0402900, 0}, -{W, 1, "", 0x681d0, 0xb040b060, 0}, -{W, 1, "", 0x681d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x681d8, 0x28801858, 0}, -{W, 1, "", 0x681dc, 0xb060b080, 0}, -{W, 1, "", 0x681e0, 0xb0a0b060, 0}, -{W, 1, "", 0x681e4, 0x18602820, 0}, -{W, 1, "", 0x681e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_LUMA_59, 0x0000b060, 0}, -{W, 1, "", TV_H_CHROMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_CHROMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_CHROMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_CHROMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_CHROMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_CHROMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_CHROMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_CHROMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_CHROMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_CHROMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_CHROMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x54, 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0000:00:02.0 on minor 0", 0x0, 0x0, 0}, -{0,}, -}; - -int niodefs = sizeof(iodefs) / sizeof(iodefs[0]); diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h deleted file mode 100644 index 8f37d9b..0000000 --- a/src/mainboard/lenovo/x60/i915io.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i915_reg.h" -#include "drm_dp_helper.h" - -/* things that are, strangely, not defined anywhere? */ -#define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1<<31) - -/* Google Link-specific defines */ -/* how many 4096-byte pages do we need for the framebuffer? - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * HencetThere are 4250 GTTs on Link: - * 1024 (X) * 768 (Y) pixels / 1024 pixels per page. - */ -#define FRAME_BUFFER_PAGES ((1024*768)/1024) -#define FRAME_BUFFER_BYTES (0x300000) - -/* One-letter commands for code not meant to be ready for humans. - * The code was generated by a set of programs/scripts. - * M print out a kernel message - * R read a register. We do these mainly to ensure that if hardware wanted - * the register read, it was read; also, in debug, we can see what was expected - * and what was found. This has proven *very* useful to get this debugged. - * The udelay, if non-zero, will make sure there is a - * udelay() call with the value. - * The count is from the kernel and tells us how many times this read was done. - * Also useful for debugging and the state - * machine uses the info to drive a poll. - * W Write a register - * V set verbosity. It's a bit mask. - * 0 -> nothing - * 1 -> print kernel messages - * 2 -> print IO ops - * 4 -> print the number of times we spin on a register in a poll - * 8 -> restore whatever the previous verbosity level was - * (only one deep stack) - * - * Again, this is not really meant for human consumption. There is not a poll - * operator as such because, sometimes, there is a read/write/read where the - * second read is a poll, and this chipset is so touchy I'm reluctant to move - * things around and/or delete too many reads. - */ -#define M 1 -#define R 2 -#define W 4 -#define V 8 -#define I 16 -#define P 32 - -struct iodef { - unsigned char op; - unsigned int count; - const char *msg; - unsigned long addr; - unsigned long data; - unsigned long udelay; -}; - -/* i915.c */ -unsigned long io_i915_READ32(unsigned long addr); -void io_i915_WRITE32(unsigned long val, unsigned long addr); - -/* intel_dp.c */ -u32 pack_aux(u32 *src, int src_bytes); -void unpack_aux(u32 src, u32 *dst, int dst_bytes); -int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size); diff --git a/src/mainboard/lenovo/x60/intel_dp.c b/src/mainboard/lenovo/x60/intel_dp.c deleted file mode 100644 index e48f4f8..0000000 --- a/src/mainboard/lenovo/x60/intel_dp.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Keith Packard <keithp(a)keithp.com> - * - */ - -#include <console/console.h> -#include <stdint.h> -#include <delay.h> -#include "i915io.h" - -u32 -pack_aux(u32 *src32, int src_bytes) -{ - u8 *src = (u8 *)src32; - int i; - u32 v = 0; - - if (src_bytes > 4) - src_bytes = 4; - for (i = 0; i < src_bytes; i++) - v |= ((u32) src[i]) << ((3-i) * 8); - return v; -} - -void -unpack_aux(u32 src, u32 *dst32, int dst_bytes) -{ - u8 *dst = (u8 *)dst32; - - int i; - if (dst_bytes > 4) - dst_bytes = 4; - for (i = 0; i < dst_bytes; i++) - dst[i] = src >> ((3-i) * 8); -} - -int -intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size) -{ - int i; - int recv_bytes; - u32 status; - u32 aux_clock_divider; - int try, precharge = 5; - - /* The clock divider is based off the hrawclk, - * and would like to run at 2MHz. So, take the - * hrawclk value and divide by 2 and use that - * - * Note that PCH attached eDP panels should use a 125MHz input - * clock divider. - */ - /* 200 on link */ - aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ - - /* Try to wait for any previous AUX channel activity */ - for (try = 0; try < 3; try++) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(1000); - } - - if (try == 3) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n", - io_i915_READ32(ch_ctl)); - return -1; - } - - /* Must try at least 3 times according to DP spec */ - for (try = 0; try < 5; try++) { - /* Load the send data into the aux channel data registers */ - for (i = 0; i < send_bytes; i += 4) - io_i915_WRITE32(send[i], ch_data + i); - - /* Send the command and wait for it to complete */ - io_i915_WRITE32( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_TIME_OUT_400us | - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | - (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - for (;;) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(100); - } - - /* Clear done status and any errors */ - io_i915_WRITE32( - status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - - if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) - continue; - if (status & DP_AUX_CH_CTL_DONE) - break; - } - - if ((status & DP_AUX_CH_CTL_DONE) == 0) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status); - return -1; - } - - /* Check for timeout or receive error. - * Timeouts occur when the sink is not connected - */ - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, - "dp_aux_ch receive error status 0x%08x\n", status); - return -1; - } - - /* Timeouts occur when the device isn't connected, so they're - * "normal" -- don't fill the kernel log with these */ - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status); - return -1; - } - - /* Unload any bytes sent back from the other side */ - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); - if (recv_bytes > recv_size) - recv_bytes = recv_size; - - for (i = 0; i < recv_bytes; i += 4) - unpack_aux(io_i915_READ32(ch_data + i), - recv + i, recv_bytes - i); - - return recv_bytes; -} diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h new file mode 100644 index 0000000..9e25ecc --- /dev/null +++ b/src/northbridge/intel/i945/chip.h @@ -0,0 +1,6 @@ +struct northbridge_intel_i945_config { + u32 gpu_hotplug; + u32 gpu_backlight; + int gpu_lvds_use_spread_spectrum_clock; + int gpu_lvds_is_dual_channel; +}; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..847c8f7 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -24,9 +24,334 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include "i945.h" +#include "chip.h" +#include <edid.h> +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include <string.h> #define GDRST 0xc0 +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ + +#define PGETBL_CTL 0x2020 +#define PGETBL_ENABLED 0x00000001 + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +static int gtt_setup(unsigned int mmiobase) +{ + unsigned long PGETBL_save; + + PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + PGETBL_save |= PGETBL_ENABLED; + + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= 2; /* set GTT to 256kb */ + + write32(mmiobase + GFX_FLSH_CNTL, 0); + + write32(mmiobase + PGETBL_CTL, PGETBL_save); + + /* verify */ + if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + } else { + printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + return 1; + } + write32(mmiobase + GFX_FLSH_CNTL, 0); + + return 0; +} + +static int intel_gma_init(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + unsigned int pmmio, unsigned int pgfx) +{ + struct edid edid; + u8 edid_data[256]; + unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; + + pphysbase += 0x20000; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + vblank = edid.vbl; + hblank = edid.hbl; + vsync = edid.vspw; + hsync = edid.hspw; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + + write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(pmmio+MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio+PP_ON_DELAYS, 0); + write32(pmmio+PP_OFF_DELAYS, 0); + + /* Disable VGA. */ + write32(pmmio+VGACNTRL, VGA_DISP_DISABLE); + + /* Disable pipes. */ + write32(pmmio+PIPECONF(0), 0); + write32(pmmio+PIPECONF(1), 0); + + /* Init PRB0. */ + write32(pmmio+HWS_PGA,0x352d2000); + write32(pmmio+PRB0_CTL, 0); + write32(pmmio+PRB0_HEAD, 0); + write32(pmmio+PRB0_TAIL, 0); + write32(pmmio+PRB0_START, 0); + write32(pmmio+PRB0_CTL, 0x0001f001); + + write32(pmmio+D_STATE, DSTATE_PLL_D3_OFF + | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); + write32(pmmio+ECOSKPD,0x00010000); + write32(pmmio+HWSTAM,0x0000effe); + write32(pmmio+PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio+INSTPM,0x08000000 | INSTPM_AGPBUSY_DIS); + + target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } + + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(pmmio + HBLANK(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(pmmio + HSYNC(1), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(pmmio + VSYNC(1), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); + + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PF_CTL(0),0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PF_WIN_POS(0), 0); + write32(pmmio+PFIT_PGM_RATIOS, 0); + write32(pmmio+PFIT_CONTROL, 0); + + mdelay(1); + + write32(pmmio+DSPSIZE(0),(hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio+DSPPOS(0),0); + + /* Backlight init. */ + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio+FW_BLC_SELF,0x0001003f); + write32(pmmio+FW_BLC,0x011d0109); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio+BLC_PWM_CTL,conf->gpu_backlight); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), (1 << 31)); + write32(pmmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL | (1 << 30)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); + write32(pmmio + EIR, 0xffffffff); + + /* GTT is the Global Translation Table for the graphics pipeline. + * It is used to translate graphics addresses to physical + * memory addresses. As in the CPU, GTTs map 4K pages. + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * There are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + * The setgtt function adds a further bit of flexibility: + * it allows you to set a range (the first two parameters) to point + * to a physical address (third parameter);the physical address is + * incremented by a count (fourth parameter) for each GTT in the + * range. + * Why do it this way? For ultrafast startup, + * we can point all the GTT entries to point to one page, + * and set that page to 0s: + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * this takes about 2 ms, and is a win because zeroing + * the page takes a up to 200 ms. We will be exploiting this + * trick in a later rev of this code. + * This call sets the GTT to point to a linear range of pages + * starting at physbase. + */ + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + + set_vbe_mode_info_valid(&edid, pgfx); + + return 0; +} +#endif + static void gma_func0_init(struct device *dev) { u32 reg32; @@ -40,8 +365,8 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -53,17 +378,19 @@ static void gma_func0_init(struct device *dev) /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); u32 iobase, mmiobase, graphics_base; + struct northbridge_intel_i945_config *conf = dev->chip_info; + iobase = dev->resource_list[1].base; mmiobase = dev->resource_list[0].base; - graphics_base = dev->resource_list[2].base + 0x20000; + graphics_base = dev->resource_list[2].base; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", pci_read_config32(dev, 0x18), pci_read_config32(dev, 0x1c) ); - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); + intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); #endif } @@ -92,7 +419,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

1 0

Patch set updated for coreboot: 7911265 apple/macbook21: Fix audio.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5324 -gerrit commit 79112658645d5582f4c700e4279033db2a3a2d9e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Mar 3 00:44:38 2014 +0100 apple/macbook21: Fix audio. Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/devicetree.cb | 2 +- src/mainboard/apple/macbook21/hda_verb.h | 93 +++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/mainboard.c | 7 ++- 3 files changed, 99 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 2141819..a7fb654 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -68,7 +68,7 @@ chip northbridge/intel/i945 register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller - subsystemid 0x17aa 0x2010 + subsystemid 0x8384 0x7680 end device pci 1c.0 on end # Ethernet device pci 1c.1 on end # Atheros WLAN diff --git a/src/mainboard/apple/macbook21/hda_verb.h b/src/mainboard/apple/macbook21/hda_verb.h new file mode 100644 index 0000000..4e1687d --- /dev/null +++ b/src/mainboard/apple/macbook21/hda_verb.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ + 0x106b2200, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + 0x00172000, + 0x00172122, + 0x0017226B, + 0x00172310, + + /* NID 0x0A. */ + 0x00A71C1F, + 0x00A71DE2, + 0x00A71E21, + 0x00A71F03, + + /* NID 0x0B. */ + 0x00B71C2E, + 0x00B71DE0, + 0x00B71EA1, + 0x00B71F03, + + /* NID 0x0C. */ + 0x00C71C10, + 0x00C71DE1, + 0x00C71E17, + 0x00C71F90, + + /* NID 0x0D. */ + 0x00D71C1F, + 0x00D71DE1, + 0x00D71E17, + 0x00D71F90, + + /* NID 0x0E. */ + 0x00E71CFE, + 0x00E71D00, + 0x00E71E00, + 0x00E71F40, + + /* NID 0x0F */ + 0x00F71C20, + 0x00F71DE0, + 0x00F71E81, + 0x00F71F03, + + /* NID 0x10 */ + 0x01071C30, + 0x01071DE2, + 0x01071E45, + 0x01071F13, + + /* NID 0x11 */ + 0x01171C40, + 0x01171DE2, + 0x01171EC5, + 0x01171F13, + + /* NID 0x15 */ + 0x01571CFC, + 0x01571D00, + 0x01571E00, + 0x01571F40, + + /* NID 0x1B. */ + 0x01B71CFB, + 0x01B71D00, + 0x01B71E00, + 0x01B71F40, + +}; diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index a136a4c..9a025dd 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -34,10 +34,11 @@ #include <arch/x86/include/arch/acpigen.h> #include <smbios.h> #include <x86emu/x86emu.h> +#include "hda_verb.h" #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(void) @@ -86,6 +87,8 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); } struct chip_operations mainboard_ops = {

1 0

New patch to review for coreboot: 52d5137 apple/macbook21: Fix audio.
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5324 -gerrit commit 52d5137619fbee93d3d59c30b0e970795938384e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Mar 3 00:44:38 2014 +0100 apple/macbook21: Fix audio. Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/devicetree.cb | 2 +- src/mainboard/apple/macbook21/hda_verb.h | 93 +++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/mainboard.c | 7 ++- 3 files changed, 99 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f264f9e..7dececc 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -67,7 +67,7 @@ chip northbridge/intel/i945 register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller - subsystemid 0x17aa 0x2010 + subsystemid 0x8384 0x7680 end device pci 1c.0 on end # Ethernet device pci 1c.1 on end # Atheros WLAN diff --git a/src/mainboard/apple/macbook21/hda_verb.h b/src/mainboard/apple/macbook21/hda_verb.h new file mode 100644 index 0000000..4e1687d --- /dev/null +++ b/src/mainboard/apple/macbook21/hda_verb.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ + 0x106b2200, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + 0x00172000, + 0x00172122, + 0x0017226B, + 0x00172310, + + /* NID 0x0A. */ + 0x00A71C1F, + 0x00A71DE2, + 0x00A71E21, + 0x00A71F03, + + /* NID 0x0B. */ + 0x00B71C2E, + 0x00B71DE0, + 0x00B71EA1, + 0x00B71F03, + + /* NID 0x0C. */ + 0x00C71C10, + 0x00C71DE1, + 0x00C71E17, + 0x00C71F90, + + /* NID 0x0D. */ + 0x00D71C1F, + 0x00D71DE1, + 0x00D71E17, + 0x00D71F90, + + /* NID 0x0E. */ + 0x00E71CFE, + 0x00E71D00, + 0x00E71E00, + 0x00E71F40, + + /* NID 0x0F */ + 0x00F71C20, + 0x00F71DE0, + 0x00F71E81, + 0x00F71F03, + + /* NID 0x10 */ + 0x01071C30, + 0x01071DE2, + 0x01071E45, + 0x01071F13, + + /* NID 0x11 */ + 0x01171C40, + 0x01171DE2, + 0x01171EC5, + 0x01171F13, + + /* NID 0x15 */ + 0x01571CFC, + 0x01571D00, + 0x01571E00, + 0x01571F40, + + /* NID 0x1B. */ + 0x01B71CFB, + 0x01B71D00, + 0x01B71E00, + 0x01B71F40, + +}; diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index a136a4c..9a025dd 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -34,10 +34,11 @@ #include <arch/x86/include/arch/acpigen.h> #include <smbios.h> #include <x86emu/x86emu.h> +#include "hda_verb.h" #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(void) @@ -86,6 +87,8 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); } struct chip_operations mainboard_ops = {

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New patch to review for coreboot: 065cb3a EC
by Vladimir Serbinenko 03 Mar '14

03 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5323 -gerrit commit 065cb3a7d60ab3e14492502a83ff9f9f52be5475 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 20:24:21 2014 +0100 EC Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi/ec.asl | 218 ++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/apple/macbook21/dsdt.asl | 1 - 3 files changed, 220 insertions(+), 4 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index e69de29..01bfb0c 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -0,0 +1,218 @@ +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + HPAC, 1, + Offset(0x02), + WKLD, 1, /* Lid wake */ + + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, + } + Field(ERAM, ByteAcc, Lock, Preserve) + { + Offset(0x24), + SBDW, 16, + } + + Method(SBPC, 0, NotSerialized) + { + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } + } + + Method(SBRW, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) + } + + Method(SBRB, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) + } + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_INI, 0, NotSerialized) + { + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } + + Device(BAT0) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } + } +} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index b5963eb..f264f9e 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -56,9 +56,8 @@ chip northbridge/intel/i945 # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "1" - register "gpi8_routing" = "2" + register "gpi1_routing" = "2" + register "gpi7_routing" = "2" register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index e654d20..5ba7b09 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ -#define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0

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coreboot-gerrit March 2014