coreboot-gerrit March 2014

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New patch to review for coreboot: d633b33 regions support
by Aaron Durbin 18 Mar '14

18 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5394 -gerrit commit d633b331019e055e1db8fd5157d34d05172080cb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 13 08:50:00 2014 -0500 regions support Needs some cleanup work. Compile tested as of now. Change-Id: I2a78278090ae928468e197ac73d1fb18596bf8cb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 7 + src/arch/x86/boot/smbios.c | 8 +- src/arch/x86/lib/cbfs_and_run.c | 2 + src/arch/x86/lib/rom_media.c | 116 +++--- src/cpu/intel/microcode/microcode.c | 38 +- src/cpu/x86/mirror_payload.c | 38 +- src/device/pci_device.c | 7 +- src/device/pci_rom.c | 232 +++++++----- src/drivers/elog/elog.c | 142 +++----- src/include/cbfs.h | 120 ++++--- src/include/cbfs_core.h | 44 --- src/include/device/pci_rom.h | 4 +- src/include/payload_loader.h | 3 + src/include/region.h | 138 ++++++++ src/include/rmodule.h | 7 +- src/lib/Makefile.inc | 10 + src/lib/bootrw_spi_flash_region.c | 107 ++++++ src/lib/cbfs.c | 488 ++++++++++++++++++-------- src/lib/cbfs_boot_region.c | 130 +++++++ src/lib/cbfs_core.c | 224 ------------ src/lib/loaders/cbfs_payload_loader.c | 18 +- src/lib/loaders/cbfs_ramstage_loader.c | 12 +- src/lib/loaders/load_and_run_payload.c | 5 +- src/lib/region.c | 283 +++++++++++++++ src/lib/rmodule.c | 46 ++- src/lib/selfboot.c | 113 +++--- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/mrc_cache.c | 20 +- src/soc/intel/baytrail/nvm.c | 27 +- src/soc/intel/baytrail/romstage/raminit.c | 9 +- src/soc/intel/baytrail/romstage/romstage.c | 4 + src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/chromeos.c | 4 + src/vendorcode/google/chromeos/fmap.c | 174 +++++---- src/vendorcode/google/chromeos/fmap.h | 25 +- src/vendorcode/google/chromeos/vboot_loader.c | 47 ++- 36 files changed, 1714 insertions(+), 940 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 531a8c8..b0b8d26 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1094,3 +1094,10 @@ config REG_SCRIPT default n help Internal option that controls whether we compile in register scripts. + +config BOOT_REGION_SPI_FLASH + def_bool n + depends on ARCH_X86 + help + Use generic SPI flash boot region support. This will provide a + function to initialize the read-write boot region. diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 0e84acc..0434715 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -27,7 +27,6 @@ #include <device/device.h> #include <arch/cpu.h> #include <cpu/x86/name.h> -#include <cbfs_core.h> #include <arch/byteorder.h> #include <elog.h> #if CONFIG_CHROMEOS @@ -147,12 +146,7 @@ static int smbios_write_type0(unsigned long *current, int handle) #endif { - const struct cbfs_header *header; - u32 romsize = CONFIG_ROM_SIZE; - header = cbfs_get_header(CBFS_DEFAULT_MEDIA); - if (header != CBFS_HEADER_INVALID_ADDRESS) - romsize = ntohl(header->romsize); - t->bios_rom_size = (romsize / 65535) - 1; + t->bios_rom_size = (CONFIG_ROM_SIZE / 65535) - 1; } t->system_bios_major_release = 4; diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ca8d61b..1ad935c 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -19,8 +19,10 @@ #include <arch/stages.h> #include <ramstage_loader.h> +#include <region.h> void asmlinkage copy_and_run(void) { + boot_region_init(); run_ramstage(); } diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c index ed2122c..c565faf 100644 --- a/src/arch/x86/lib/rom_media.c +++ b/src/arch/x86/lib/rom_media.c @@ -18,84 +18,64 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA */ -#include <cbfs.h> +#include <stdint.h> #include <string.h> +#include <console/console.h> +#include <region.h> -#ifdef LIBPAYLOAD -# define printk(x...) -# define init_default_cbfs_media libpayload_init_default_cbfs_media - extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -#else -# include <console/console.h> -#endif - -// Implementation of memory-mapped ROM media source on X86. - -static int x86_rom_open(struct cbfs_media *media) { - return 0; +static inline void *get_pointer(offset_t off) +{ + const uintptr_t base_address = (uintptr_t)-CONFIG_ROM_SIZE; + return (void *)(base_address + off); } -static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) { - void *ptr; - // Some address (ex, pointer to master header) may be given in memory - // mapped location. To workaround that, we handle >0xf0000000 as real - // memory pointer. - - if ((uint32_t)offset > (uint32_t)0xf0000000) - ptr = (void*)offset; - else - ptr = (void*)(0 - (uint32_t)media->context + offset); - return ptr; +static void * +boot_mmap(const struct region_device *rdev, offset_t off, size_t size) +{ + return get_pointer(off); } -static void *x86_rom_unmap(struct cbfs_media *media, const void *address) { - return NULL; +static void boot_munmap(const struct region_device *rdev, void *addr) +{ } -static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr = x86_rom_map(media, offset, count); - memcpy(dest, ptr, count); - x86_rom_unmap(media, ptr); - return count; +static ssize_t +boot_readat(const struct region_device *rdev, void *buf, + offset_t off, size_t size) +{ + memcpy(buf, get_pointer(off), size); + return size; } -static int x86_rom_close(struct cbfs_media *media) { - return 0; -} +static const struct region_device_ops boot_dev_ops = { + .mmap = boot_mmap, + .munmap = boot_munmap, + .readat = boot_readat, +}; -int init_x86rom_cbfs_media(struct cbfs_media *media); -int init_x86rom_cbfs_media(struct cbfs_media *media) { - // On X86, we always keep a reference of pointer to CBFS header in - // 0xfffffffc, and the pointer is still a memory-mapped address. - // Since the CBFS core always use ROM offset, we need to figure out - // header->romsize even before media is initialized. - struct cbfs_header *header = (struct cbfs_header*) - *(uint32_t*)(0xfffffffc); - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { -#if defined(CONFIG_ROM_SIZE) - printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); - media->context = (void*)CONFIG_ROM_SIZE; -#else - return -1; -#endif - } else { - uint32_t romsize = ntohl(header->romsize); - media->context = (void*)romsize; -#if defined(CONFIG_ROM_SIZE) - if (CONFIG_ROM_SIZE != romsize) - printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_ROM_SIZE, romsize); -#endif - } - media->open = x86_rom_open; - media->close = x86_rom_close; - media->map = x86_rom_map; - media->unmap = x86_rom_unmap; - media->read = x86_rom_read; - return 0; -} +static const struct region_device boot_dev = { + .ops = &boot_dev_ops, + .region = { + .offset = 0, + .size = CONFIG_ROM_SIZE, + }, +}; -int init_default_cbfs_media(struct cbfs_media *media) { - return init_x86rom_cbfs_media(media); +void boot_media_initialize(void) +{ + rhandle_t rh; + const char *bootro_name = BOOTRO_REGION_NAME; + + rh = region_locate(bootro_name); + + /* Already registered. */ + if (rhandle_valid(rh)) + return; + + rh = region_register(bootro_name, &boot_dev); + + if (!rhandle_valid(rh)) { + printk(BIOS_ERR, "Couldn't register boot region.\n"); + return; + } } diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 947dfd7..d6753c1 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -107,28 +107,48 @@ void intel_microcode_load_unlocked(const void *microcode_patch) #endif } +#if !defined(__ROMCC__) +static void *microcode_locate(u32 *len) +{ + const struct cbfs_file_descriptor *fd; + void *buf; + + fd = cbfs_open_by_name(cbfs_default_descriptor(), MICROCODE_CBFS_FILE); + if (fd == NULL) + return NULL; + + /* + * The following sequence relies on x86 having a persistent + * memory-mapped view of the SPI rom. + */ + *len = cbfs_file_content_size(fd); + buf = cbfs_file_map_content(fd, 0, *len); + cbfs_file_close(fd); + + return buf; +} +#endif + const void *intel_microcode_find(void) { - struct cbfs_file *microcode_file; const struct microcode *ucode_updates; u32 eax, microcode_len; u32 pf, rev, sig, update_size; unsigned int x86_model, x86_family; msr_t msr; +#if defined(__ROMCC__) + struct cbfs_file *file; -#ifdef __PRE_RAM__ - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); + file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); + microcode_len = ntohl(file->len); + ucode_updates = CBFS_SUBHEADER(file); #else - microcode_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, - MICROCODE_CBFS_FILE); + ucode_updates = microcode_locate(&microcode_len); #endif - if (!microcode_file) + if (!ucode_updates) return NULL; - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); - /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index edd2641..a6975e1 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -30,26 +30,12 @@ void mirror_payload(struct payload *payload) size_t size; char *src; uintptr_t alignment_diff; - const unsigned long cacheline_size = 64; - const uintptr_t intra_cacheline_mask = cacheline_size - 1; - const uintptr_t cacheline_mask = ~intra_cacheline_mask; + const unsigned long dword_size = sizeof(uint32_t); + const uintptr_t dword_mask = dword_size - 1; src = payload->backing_store.data; size = payload->backing_store.size; - /* - * Adjust size so that the start and end points are aligned to a - * cacheline. The SPI hardware controllers on Intel machines should - * cache full length cachelines as well as prefetch data. Once the - * data is mirrored in memory all accesses should hit the CPU's cache. - */ - alignment_diff = (intra_cacheline_mask & (uintptr_t)src); - size += alignment_diff; - - size = ALIGN(size, cacheline_size); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size); - buffer = bootmem_allocate_buffer(size); if (buffer == NULL) { @@ -57,7 +43,18 @@ void mirror_payload(struct payload *payload) return; } - src = (void *)(cacheline_mask & (uintptr_t)src); + /* + * Do copies in 32-bit aligned reads from backing source. + * 1. Do a copy to align the source address. + * 2. Do remaining copy. + */ + alignment_diff = dword_mask & (uintptr_t)src; + if (alignment_diff != 0) { + mempcy(buffer, src, alignment_diff); + src += alignment_diff; + buffer += alignment_diff; + size -= alignment_diff; + } /* * Note that if mempcy is not using 32-bit moves the performance will @@ -66,6 +63,9 @@ void mirror_payload(struct payload *payload) */ memcpy(buffer, src, size); - /* Update the payload's backing store. */ - payload->backing_store.data = &buffer[alignment_diff]; + /* + * Update the payload's backing store. May leak resources depending + * cbfs stroage source. + */ + payload->backing_store.data = buffer; } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index aa0d954..bcdbbe4 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -667,7 +667,7 @@ int oprom_is_loaded = 0; void pci_dev_init(struct device *dev) { #if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; + struct rom_header *ram; /* Only execute VGA ROMs. */ if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) @@ -694,11 +694,8 @@ void pci_dev_init(struct device *dev) return; #endif - rom = pci_rom_probe(dev); - if (rom == NULL) - return; + ram = pci_load_vga_rom(dev); - ram = pci_rom_load(dev, rom); if (ram == NULL) return; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 1bdccf0..bb17931 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -6,6 +6,7 @@ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,62 +29,15 @@ #include <device/pci_ops.h> #include <string.h> #include <cbfs.h> +#include <cbfs_core.h> -struct rom_header *pci_rom_probe(struct device *dev) +static struct rom_header * +pci_rom_verify_and_load(struct device *dev, struct rom_header *rom_header, + void *load_addr, int check_didvid) { - struct rom_header *rom_header; struct pci_data *rom_data; - - /* If it's in FLASH, then don't check device for ROM. */ - rom_header = cbfs_load_optionrom(CBFS_DEFAULT_MEDIA, dev->vendor, - dev->device, NULL); - - u32 vendev = (dev->vendor << 16) | dev->device; - u32 mapped_vendev = vendev; - - if (map_oprom_vendev) - mapped_vendev = map_oprom_vendev(vendev); - - if (!rom_header) { - if (vendev != mapped_vendev) { - rom_header = cbfs_load_optionrom( - CBFS_DEFAULT_MEDIA, - mapped_vendev >> 16, - mapped_vendev & 0xffff, NULL); - } - } - - if (rom_header) { - printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", - dev_path(dev), rom_header); - } else { - u32 rom_address; - - rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - - if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG_BOARD_EMULATION_QEMU_X86 - if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) - rom_address = 0xc0000; - else -#endif - return NULL; - } else { - /* Enable expansion ROM address decoding. */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); - } - -#if CONFIG_ON_DEVICE_ROM_RUN - printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", - dev_path(dev), (unsigned long)rom_address); - rom_header = (struct rom_header *)rom_address; -#else - printk(BIOS_DEBUG, "Option ROM execution disabled " - "for %s\n", dev_path(dev)); - return NULL; -#endif - } + unsigned int rom_size; + unsigned int image_size; printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, " "INIT size 0x%04x, data ptr 0x%04x\n", @@ -100,10 +54,11 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n", rom_data->vendor, rom_data->device); + /* If the device id is mapped, a mismatch is expected */ - if ((dev->vendor != rom_data->vendor - || dev->device != rom_data->device) - && (vendev == mapped_vendev)) { + if (check_didvid != 0 && + (dev->vendor != rom_data->vendor || + dev->device != rom_data->device)) { printk(BIOS_ERR, "ID mismatch: vendor ID %04x, " "device ID %04x\n", rom_data->vendor, rom_data->device); return NULL; @@ -117,29 +72,16 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); - // return NULL; } - return rom_header; -} - -static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START; - -struct rom_header *pci_rom_load(struct device *dev, - struct rom_header *rom_header) -{ - struct pci_data * rom_data; - unsigned int rom_size; - unsigned int image_size=0; - + image_size = 0; do { /* Get next image. */ - rom_header = (struct rom_header *)((void *) rom_header - + image_size); - - rom_data = (struct pci_data *)((void *) rom_header - + le32_to_cpu(rom_header->data)); + int data_offset; + rom_header = (void *)((char *)rom_header + image_size); + data_offset = le32_to_cpu(rom_header->data); + rom_data = (void *)((char *)rom_header + data_offset); image_size = le32_to_cpu(rom_data->ilen) * 512; } while ((rom_data->type != 0) && (rom_data->indicator != 0)); // make sure we got x86 version @@ -148,30 +90,128 @@ struct rom_header *pci_rom_load(struct device *dev, rom_size = rom_header->size * 512; - /* - * We check to see if the device thinks it is a VGA device not - * whether the ROM image is for a VGA device because some - * devices have a mismatch between the hardware and the ROM. - */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if (load_addr != (void *)rom_header) { + printk(BIOS_DEBUG, "Copying ROM from %p to %p, 0x%x bytes.\n", + rom_header, load_addr, rom_size); + memcpy(load_addr, rom_header, rom_size); + } + + return load_addr; +} + +static inline int tohex4(unsigned int c) +{ + return (c <= 9) ? (c + '0') : (c - 10 + 'a'); +} + +static void tohex16(uint16_t val, char* dest) +{ + dest[0] = tohex4(val>>12); + dest[1] = tohex4((val>>8) & 0xf); + dest[2] = tohex4((val>>4) & 0xf); + dest[3] = tohex4(val & 0xf); +} + +static const struct cbfs_file_descriptor * +cbfs_open_optionrom(uint16_t vendor, uint16_t device) +{ + char name[17] = "pciXXXX,XXXX.rom"; + + tohex16(vendor, name+3); + tohex16(device, name+8); + + return cbfs_open_by_name_type(cbfs_default_descriptor(), name, + CBFS_TYPE_OPTIONROM); +} + +static void *cbfs_probe_and_load(struct device *dev, void *dest) +{ + const struct cbfs_file_descriptor *file; + uint32_t vendev; + int remapped; + struct rom_header *hdr; + void *load_addr; + ssize_t filesz; + + load_addr = NULL; + remapped = 0; + file = cbfs_open_optionrom(dev->vendor, dev->device); + + if (file == NULL && map_oprom_vendev != NULL) { + vendev = map_oprom_vendev((dev->vendor << 16) | dev->device); + file = cbfs_open_optionrom(vendev >> 16, vendev & 0xffff); + remapped = 1; + } + + if (file == NULL) + return NULL; + + filesz = cbfs_file_content_size(file); + hdr = cbfs_file_map_content(file, 0, filesz); + if (hdr == NULL) + goto out; + + printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", + dev_path(dev), hdr); + + load_addr = pci_rom_verify_and_load(dev, hdr, dest, !remapped); + cbfs_file_unmap(file, hdr); + +out: + cbfs_file_close(file); + return load_addr; +} + +#if CONFIG_ON_DEVICE_ROM_RUN +static void *dev_probe_and_load(struct device *dev, void *dest) +{ + uint32_t rom_address; + struct rom_header *rom_header; + + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + if (IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86)) + rom_address = 0xc0000; + else + return NULL; + } else { + /* Enable expansion ROM address decoding. */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); + } + printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", + dev_path(dev), (unsigned long)rom_address); + + rom_header = (struct rom_header *)rom_address; + + return pci_rom_verify_and_load(dev, rom_header, dest, 1); +} +#endif + +struct rom_header *pci_load_vga_rom(struct device *dev) +{ + void *vga_load_addr = (void *)PCI_VGA_RAM_IMAGE_START; + void *load_addr; + + if (PCI_CLASS_DISPLAY_VGA != (dev->class >> 8)) + return NULL; + #if !CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; /* Primary VGA device (device.c). */ - if (dev != vga_pri) return NULL; /* Only one VGA supported. */ + extern device_t vga_pri; /* Primary VGA device (device.c). */ + if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif - if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { - printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); - memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); - } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); - } - printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " - "bytes\n", rom_header, pci_ram_image_start, rom_size); + load_addr = cbfs_probe_and_load(dev, vga_load_addr); + + if (load_addr == NULL) { +#if CONFIG_ON_DEVICE_ROM_RUN + load_addr = dev_probe_and_load(dev, vga_load_addr); +#else + printk(BIOS_DEBUG, "Option ROM execution disabled for %s\n", + dev_path(dev)); +#endif + } - memcpy(pci_ram_image_start, rom_header, rom_size); - pci_ram_image_start += rom_size; - return (struct rom_header *) (pci_ram_image_start-rom_size); + return load_addr; } diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index de34928..597c32e 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -22,10 +22,9 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> #include <smbios.h> -#include <spi-generic.h> -#include <spi_flash.h> #include <stdint.h> #include <string.h> +#include <region.h> #include <elog.h> #include "elog_internal.h" @@ -54,13 +53,15 @@ #define elog_debug(STR...) #endif + +#define ELOG_REGION_NAME "elog" + /* * Static variables for ELOG state */ static struct elog_area *elog_area; static u16 total_size; static u16 log_size; -static u32 flash_base; static elog_area_state area_state; static elog_header_state header_state; @@ -70,51 +71,10 @@ static u16 next_event_offset; static u16 event_count; static int elog_initialized; -static struct spi_flash *elog_spi; - - -static inline u32 get_rom_size(void) -{ - u32 rom_size; - - /* Assume the used space of the ROM image starts from 0. The - * physical size of the device may not be completely used. */ - rom_size = elog_spi->size; - if (rom_size > CONFIG_ROM_SIZE) - rom_size = CONFIG_ROM_SIZE; - - return rom_size; -} - -/* - * Convert a memory mapped flash address into a flash offset - */ -static inline u32 elog_flash_address_to_offset(u8 *address) -{ - u32 rom_size; - - if (!elog_spi) - return 0; - rom_size = get_rom_size(); - - return (u32)address - ((u32)~0UL - rom_size + 1); -} - -/* - * Convert a flash offset into a memory mapped flash address - */ -static inline u8* elog_flash_offset_to_address(u32 offset) -{ - u32 rom_size; - - if (!elog_spi) - return NULL; - - rom_size = get_rom_size(); - - return (u8*)((u32)~0UL - rom_size + 1 + offset); -} +/* Region device for accessing the ELOG area. */ +static struct region_device elog_dev; +static rhandle_t elog_rh = INVALID_RHANDLE; /* * Pointer to an event log header in the event data area @@ -259,17 +219,16 @@ static void elog_flash_write(void *address, u32 size) { u32 offset; - if (!address || !size || !elog_spi) + if (!address || !size) return; - offset = flash_base; - offset += (u8 *)address - (u8 *)elog_area; + offset = (u8 *)address - (u8 *)elog_area; elog_debug("elog_flash_write(address=0x%p offset=0x%08x size=%u)\n", address, offset, size); /* Write the data to flash */ - elog_spi->write(elog_spi, offset, size, address); + region_writeat(elog_rh, address, offset, size); } /* @@ -280,17 +239,16 @@ static void elog_flash_erase(void *address, u32 size) { u32 offset; - if (!address || !size || !elog_spi) + if (!address || !size) return; - offset = flash_base; - offset += (u8 *)address - (u8*)elog_area; + offset = (u8 *)address - (u8*)elog_area; elog_debug("elog_flash_erase(address=0x%p offset=0x%08x size=%u)\n", address, offset, size); /* Erase the sectors in this region */ - elog_spi->erase(elog_spi, offset, size); + region_eraseat(elog_rh, offset, size); } /* @@ -348,7 +306,7 @@ static void elog_scan_flash(void) event_buffer_state = ELOG_EVENT_BUFFER_OK; /* Fill memory buffer by reading from SPI */ - elog_spi->read(elog_spi, flash_base, total_size, elog_area); + region_readat(elog_rh, elog_area, 0, total_size); next_event_offset = 0; event_count = 0; @@ -449,13 +407,17 @@ int elog_smbios_write_type15(unsigned long *current, int handle) { struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); + void *backing_store; #if CONFIG_ELOG_CBMEM /* Save event log buffer into CBMEM for the OS to read */ - void *cbmem = cbmem_add(CBMEM_ID_ELOG, total_size); - if (!cbmem) + backing_store = cbmem_add(CBMEM_ID_ELOG, total_size); + if (!backing_store) return 0; - memcpy(cbmem, elog_area, total_size); + memcpy(backing_store, elog_area, total_size); +#else + /* This assumes x86 memory-mapped capabilities of flash. */ + backing_store = region_mmap(elog_rh, 0, total_size); #endif memset(t, 0, len); @@ -468,11 +430,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) t->access_method = SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32; t->log_status = SMBIOS_EVENTLOG_STATUS_VALID; t->change_token = 0; -#if CONFIG_ELOG_CBMEM - t->address = (u32)cbmem; -#else - t->address = (u32)elog_flash_offset_to_address(flash_base); -#endif + t->address = (u32)backing_store; t->header_format = ELOG_HEADER_TYPE_OEM; t->log_type_descriptors = 0; t->log_type_descriptor_length = 2; @@ -506,33 +464,46 @@ int elog_clear(void) return 0; } -static void elog_find_flash(void) +static int elog_find_flash(void) { -#if CONFIG_CHROMEOS - u8 *flash_base_ptr; -#endif + rhandle_t rh; + + if (rhandle_valid(elog_rh)) + return 0; elog_debug("elog_find_flash()\n"); #if CONFIG_CHROMEOS /* Find the ELOG base and size in FMAP */ - total_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr); - if (total_size < 0) { + if (fmap_locate("RW_ELOG", &elog_dev.region.offset, + &elog_dev.region.size)) { printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP, " "using CONFIG_ELOG_FLASH_BASE instead\n"); - total_size = CONFIG_ELOG_AREA_SIZE; } else { - flash_base = elog_flash_address_to_offset(flash_base_ptr); - /* Use configured size if smaller than FMAP size */ - if (total_size > CONFIG_ELOG_AREA_SIZE) - total_size = CONFIG_ELOG_AREA_SIZE; + if (elog_dev.region.size > CONFIG_ELOG_AREA_SIZE) + elog_dev.region.size = CONFIG_ELOG_AREA_SIZE; } #else - flash_base = CONFIG_ELOG_FLASH_BASE; - total_size = CONFIG_ELOG_AREA_SIZE; + elog_dev.region.offset = CONFIG_ELOG_FLASH_BASE; + elog_dev.region.size = CONFIG_ELOG_AREA_SIZE; #endif + total_size = elog_dev.region.size; log_size = total_size - sizeof(struct elog_header); + + rh = region_locate(BOOTRW_REGION_NAME); + if (!rhandle_valid(rh)) { + printk(BIOS_WARNING, "Unable to find writable boot region.\n"); + return -1; + } + rh = region_register_subregion("elog", &elog_dev, rh); + if (!rhandle_valid(rh)) { + printk(BIOS_WARNING, "Unable to register ELOG region.\n"); + return -1; + } + + elog_rh = rh; + return 0; } /* @@ -545,18 +516,9 @@ int elog_init(void) elog_debug("elog_init()\n"); - /* Prepare SPI */ - spi_init(); - elog_spi = spi_flash_probe(0, 0, 0, 0); - if (!elog_spi) { - printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); - return -1; - } - /* Set up the backing store */ - elog_find_flash(); - if (flash_base == 0) { - printk(BIOS_ERR, "ELOG: Invalid flash base\n"); + if (elog_find_flash()) { + printk(BIOS_ERR, "ELOG: region not set up.\n"); return -1; } @@ -589,8 +551,8 @@ int elog_init(void) elog_initialized = 1; - printk(BIOS_INFO, "ELOG: FLASH @0x%p [SPI 0x%08x]\n", - elog_area, flash_base); + printk(BIOS_INFO, "ELOG: FLASH @0x%p [SPI 0x%08zx]\n", + elog_area, (size_t)elog_dev.region.offset); printk(BIOS_INFO, "ELOG: area is %d bytes, full threshold %d," " shrink size %d\n", total_size, diff --git a/src/include/cbfs.h b/src/include/cbfs.h index ebdbf43..bd000c9 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -1,14 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Google Inc. * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,62 +14,84 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _CBFS_H_ #define _CBFS_H_ -#include <cbfs_core.h> +#include <stdint.h> +#include <region.h> -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device, void * dest); -void *cbfs_load_stage(struct cbfs_media *media, const char *name); - -/* Simple buffer for streaming media. */ -struct cbfs_simple_buffer { - char *buffer; - size_t allocated; +/* Describe an instance of cbfs. */ +struct cbfs_descriptor { + rhandle_t rh; + size_t align; size_t size; - size_t last_allocate; }; -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count); +struct cbfs_file_descriptor; + +/* Obtain the default cbfs_descriptor. */ +const struct cbfs_descriptor *cbfs_default_descriptor(void); + +/* Open a file by name. Return NULL on error. */ +const struct cbfs_file_descriptor * +cbfs_open_by_name(const struct cbfs_descriptor *cbfs, const char *name); + +/* Open a file by name and type. */ +const struct cbfs_file_descriptor * +cbfs_open_by_name_type(const struct cbfs_descriptor *cbfs, + const char *name, uint32_t type); + +/* Close a previously opened file. */ +void cbfs_file_close(const struct cbfs_file_descriptor *fd); + +/* Return the size of the file's contents. < 0 on error. */ +ssize_t cbfs_file_content_size(const struct cbfs_file_descriptor *fd); + +/* Return the size of the file's metadata contents. < 0 on error. */ +ssize_t cbfs_file_metadata_size(const struct cbfs_file_descriptor *fd); + +/* + * Read size bytes file contents from offset of into buffer. Returns < 0 + * on error or bytes read. + */ +ssize_t cbfs_file_read_content(const struct cbfs_file_descriptor *fd, + void *buf, offset_t offset, size_t size); + +/* Attempt to map the file content. Returns NULL on error. */ +void *cbfs_file_map_content(const struct cbfs_file_descriptor *fd, + offset_t offset, size_t size); + +/* + * Read size bytes file metadata from offset of into buffer. Returns < 0 + * on error or bytes read. + */ +ssize_t cbfs_file_read_metadata(const struct cbfs_file_descriptor *fd, + void *buf, offset_t offset, size_t size); +/* + * Attempt to map all of the file's metadata. Depending on the file type there + * may be no metadata in which case NULL will be returned. File types of + * CBFS_TYPE_STAGE and CBFS_TYPE_PAYLOAD are currently the only files that + * contain metadata. + * + * Returns NULL on error. + */ +void *cbfs_file_map_metadata(const struct cbfs_file_descriptor *fd); + +/* Unmap the mapping associated with addr. No partial unmappings allowed. */ +void cbfs_file_unmap(const struct cbfs_file_descriptor *fd, void *addr); + -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address); +void *cbfs_load_optionrom(const struct cbfs_descriptor *cbfs, + uint16_t vendor, uint16_t device, void * dest); -// Utility functions -int run_address(void *f); +/* Return entry point to stage, or NULL on failure. */ +void *cbfs_load_stage(const struct cbfs_descriptor *cbfs, const char *name); -/* Defined in individual arch / board implementation. */ -int init_default_cbfs_media(struct cbfs_media *media); +/* Decompress range of file to destination. Returns bytes decompressed. */ +size_t cbfs_file_inflate(const struct cbfs_file_descriptor *fd, + offset_t offset, size_t src_sz, void *dest); #if defined(__PRE_RAM__) struct romstage_handoff; diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index a1d8127..6a91454 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -186,50 +186,6 @@ struct cbfs_optionrom { uint32_t len; } __attribute__((packed)); -#define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) -#define CBFS_DEFAULT_MEDIA ((void*)(0x0)) - -/* Media for CBFS to load files. */ -struct cbfs_media { - - /* implementation dependent context, to hold resource references */ - void *context; - - /* opens media and returns 0 on success, -1 on failure */ - int (*open)(struct cbfs_media *media); - - /* returns number of bytes read from media into dest, starting from - * offset for count of bytes */ - size_t (*read)(struct cbfs_media *media, void *dest, size_t offset, - size_t count); - - /* returns a pointer to memory with count of bytes from media source - * starting from offset, or CBFS_MEDIA_INVALID_MAP_ADDRESS on failure. - * Note: mapped data can't be free unless unmap is called, even if you - * do close first. */ - void * (*map)(struct cbfs_media *media, size_t offset, size_t count); - - /* returns NULL and releases the memory by address, which was allocated - * by map */ - void * (*unmap)(struct cbfs_media *media, const void *address); - - /* closes media and returns 0 on success, -1 on failure. */ - int (*close)(struct cbfs_media *media); -}; - -/* returns pointer to a file entry inside CBFS or NULL */ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); - -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); - -/* returns decompressed size on success, 0 on failure */ -int cbfs_decompress(int algo, void *src, void *dst, int len); - -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); #endif /* __ROMCC__ */ diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index fe77276..4bd0bfd 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -6,7 +6,6 @@ #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) -#define PCI_RAM_IMAGE_START 0xD0000 #define PCI_VGA_RAM_IMAGE_START 0xC0000 struct rom_header { @@ -33,8 +32,7 @@ struct pci_data { uint16_t reserved_2; }; -struct rom_header *pci_rom_probe(struct device *dev); -struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +struct rom_header *pci_load_vga_rom(struct device *dev); u32 __attribute__((weak)) map_oprom_vendev(u32 vendev); #endif diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..7b6fc1c 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -22,6 +22,8 @@ #include <stdint.h> #include <stddef.h> +struct cbfs_file_descriptor; + struct buffer_area { void *data; size_t size; @@ -29,6 +31,7 @@ struct buffer_area { struct payload { const char *name; + const struct cbfs_file_descriptor *fd; struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; diff --git a/src/include/region.h b/src/include/region.h new file mode 100644 index 0000000..937f7ba --- /dev/null +++ b/src/include/region.h @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef REGION_H +#define REGION_H + +#include <stdint.h> +#include <stddef.h> + +/* + * Region support. + * + * Regions are intended to abstract away the access mechanisms for blocks of + * data. This could be SPI, eMMC, or a memory region as the backing store. + * Subregions can be made by registering a region_device that is associated + * with another region. Regions can be addressed by name, but there is no + * hierarchy in the namespace. i.e. the operations through subregions are + * hierarchical but the namespace is not. + * + * There are two views to the boot media: read-only and read-write. On certain + * architectures the read-write availability is not available until late in + * ramstage. Therefore, users of each region need to be cognizant of the fact + * that different implementations may be backing a particular region. e.g. on + * x86 the read-only boot region doesn't have write and erase capabilities, but + * the read-write boot region would allow writes and erases but no mmap. + */ + +/* + * Initialize the boot region. Called directly in pre-ramstage or + * automatically in ramstage. + */ +void boot_region_init(void); +/* Initialize the boot media. Board/Arch specific code implements this. */ +void boot_media_initialize(void); +/* + * A potential call for chipsets that can't bring their RW area online til + * after the device init in ramstage. + */ +void bootrw_media_initialize(void); +/* Initialize the default CBFS region. */ +void cbfs_default_media_initialize(void); + +typedef uintptr_t offset_t; +typedef long rhandle_t; +#define INVALID_RHANDLE ((rhandle_t)~((uintptr_t)0)) + +#define BOOTRO_REGION_NAME "bootro" +#define BOOTRW_REGION_NAME "bootrw" +#define DEFAULT_CBFS_REGION_NAME "cbfs" + +struct region_device; + +struct region_device_ops { + void *(*mmap)(const struct region_device *, offset_t, size_t); + void (*munmap)(const struct region_device *, void *); + ssize_t (*readat)(const struct region_device *, void *, + offset_t, size_t); + ssize_t (*writeat)(const struct region_device *, const void *, + offset_t, size_t); + ssize_t (*eraseat)(const struct region_device *, offset_t, size_t); +}; + +struct region { + offset_t offset; + size_t size; +}; + +struct region_device { + const struct region_device_ops *ops; + struct region region; +}; + +/* Return 1 if child is contained within parent else 0. */ +int region_contained(const struct region *parent, const struct region *child); + +static inline int rhandle_valid(rhandle_t rh) +{ + return !!(rh < 0); +} + +/* Register a region_device by name. */ +rhandle_t region_register(const char *name, const struct region_device *rdev); + +/* Register a subregion by name under parent. rdev->ops must be NULL. */ +rhandle_t region_register_subregion(const char *name, + const struct region_device *rdev, + rhandle_t parent); + +/* Locate a region of provided name. */ +rhandle_t region_locate(const char *name); + +/* + * Read subregion within provided region. + * Returns bytes read, < 0 on error. + */ +ssize_t region_readat(rhandle_t rh, void *buf, offset_t offset, size_t count); + +/* + * Write to subregion within provided region. + * Returns bytes written, < 0 on error. + */ +ssize_t region_writeat(rhandle_t rh, void *buf, offset_t offset, size_t count); + +/* + * Erase subregion within provide region. + * Returns bytes erased, < 0 on error. + */ +ssize_t region_eraseat(rhandle_t rh, offset_t offset, size_t count); + +/* + * Map subregion described by offset and size within the region provided. + * Returns pointer to mapped subregion or NULL on error. + */ +void *region_mmap(rhandle_t rh, offset_t offset, size_t count); + +/* Unmap previously mapped region. */ +void region_munmap(rhandle_t rh, void *addr); + +/* Get size of region represented by rh. < 0 on error. */ +ssize_t region_size(rhandle_t rh); + +#endif /* REGION_H */ diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 2147ab0..19f32e4 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -61,6 +61,7 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, #if CONFIG_DYNAMIC_CBMEM struct cbfs_stage; struct cbmem_entry; +struct cbfs_descriptor; struct rmod_stage_load { /* Inputs */ @@ -72,8 +73,10 @@ struct rmod_stage_load { }; /* Both of the following functions return 0 on success, -1 on error. */ -int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); -int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); +int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage, + void *data); +int rmodule_stage_load_from_cbfs(const struct cbfs_descriptor *cbfs, + struct rmod_stage_load *rsl); #endif struct rmodule { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index acd334e..052dc9f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -18,7 +18,9 @@ # subdirs-y += loaders +ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += cbfs.c +endif ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) bootblock-y += memset.c endif @@ -109,6 +111,13 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c +ramstage-y += region.c +romstage-y += region.c +ramstage-y += cbfs_boot_region.c +romstage-y += cbfs_boot_region.c +smm-y += cbfs_boot_region.c +ramstage-$(CONFIG_BOOT_REGION_SPI_FLASH) += bootrw_spi_flash_region.c +smm-$(CONFIG_BOOT_REGION_SPI_FLASH) += bootrw_spi_flash_region.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c @@ -125,6 +134,7 @@ smm-y += memmove.c endif smm-y += cbfs.c memcmp.c smm-y += gcc.c +smm-y += region.c $(obj)/lib/version.ramstage.o : $(obj)/build.h diff --git a/src/lib/bootrw_spi_flash_region.c b/src/lib/bootrw_spi_flash_region.c new file mode 100644 index 0000000..80b1cd1 --- /dev/null +++ b/src/lib/bootrw_spi_flash_region.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <stddef.h> +#include <region.h> +#include <spi-generic.h> +#include <spi_flash.h> + +struct bootrw_flash_device { + struct spi_flash *spi; + struct region_device dev; +}; + + +static ssize_t +bootrw_readat(const struct region_device *rdev, void *buf, + offset_t offset, size_t size) +{ + struct bootrw_flash_device *dev; + + dev = container_of(rdev, struct bootrw_flash_device, dev); + if (dev->spi->read(dev->spi, offset, size, buf)) + return -1; + return size; +} + +static ssize_t +bootrw_writeat(const struct region_device *rdev, const void *buf, + offset_t offset, size_t size) +{ + struct bootrw_flash_device *dev; + + dev = container_of(rdev, struct bootrw_flash_device, dev); + if (dev->spi->write(dev->spi, offset, size, buf)) + return -1; + return size; +} + +static ssize_t +bootrw_eraseat(const struct region_device *rdev, offset_t offset, size_t size) +{ + struct bootrw_flash_device *dev; + + dev = container_of(rdev, struct bootrw_flash_device, dev); + if (dev->spi->erase(dev->spi, offset, size)) + return -1; + return size; +} + +static const struct region_device_ops bootrw_ops = { + .readat = bootrw_readat, + .writeat = bootrw_writeat, + .eraseat = bootrw_eraseat, +}; + +static struct bootrw_flash_device flashdev = { + .dev = { + .ops = &bootrw_ops, + .region = { + .offset = 0, + .size = CONFIG_ROM_SIZE, + }, + } +}; + +void bootrw_media_initialize(void) +{ + /* Reinitialize spi regs in case. */ + spi_init(); + + if (flashdev.spi != NULL) + return; + + flashdev.spi = spi_flash_probe(0, 0, 0, 0); + if (flashdev.spi == NULL) { + printk(BIOS_WARNING, "SPI probing failed for boot region.\n"); + return; + } + + if (flashdev.spi->size != CONFIG_ROM_SIZE) { + printk(BIOS_WARNING, + "SPI mismatch with CONFIG_ROM_SIZE: %zx vs %zx\n", + (size_t)CONFIG_ROM_SIZE, (size_t)flashdev.spi->size); + return; + } + + if (!rhandle_valid(region_register(BOOTRW_REGION_NAME, &flashdev.dev))) + printk(BIOS_WARNING, "Couldn't register '%s' region.\n", + BOOTRW_REGION_NAME); +} diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dc08937..c8b37fa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014-2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,192 +17,389 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -#ifdef LIBPAYLOAD -# include <libpayload-config.h> -# ifdef CONFIG_LZMA -# include <lzma.h> -# define CBFS_CORE_WITH_LZMA -# endif -# define CBFS_MINI_BUILD -#elif defined(__SMM__) -# define CBFS_MINI_BUILD -#elif defined(__BOOT_BLOCK__) - /* No LZMA in boot block. */ -#elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE - /* No LZMA in romstage if ramstage is not compressed. */ -#else -# define CBFS_CORE_WITH_LZMA -# include <lib.h> +#if !defined(__BOOT_BLOCK__) && !(defined(__PRE_RAM__) && !IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE)) +#define CBFS_WITH_LZMA #endif -#include <cbfs.h> #include <string.h> +#include <arch/early_variables.h> +#include <cbfs.h> +#include <cbfs_core.h> #include <cbmem.h> +#include <console/console.h> +#include <lib.h> -#ifdef LIBPAYLOAD -# include <stdio.h> -# define DEBUG(x...) -# define LOG(x...) printf(x) -# define ERROR(x...) printf(x) -#else -# include <console/console.h> -# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -# define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -# if CONFIG_DEBUG_CBFS -# define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -# else -# define DEBUG(x...) -# endif -#endif +struct cbfs_file_descriptor { + rhandle_t rh; + struct region metadata; + struct region content; +}; -#if defined(CONFIG_CBFS_HEADER_ROM_OFFSET) && (CONFIG_CBFS_HEADER_ROM_OFFSET) -# define CBFS_HEADER_ROM_ADDRESS (CONFIG_CBFS_HEADER_ROM_OFFSET) -#else -// Indirect address: only works on 32bit top-aligned systems. -# define CBFS_HEADER_ROM_ADDRESS (*(uint32_t *)0xfffffffc) -#endif +#define MAX_CBFS_OPEN_FILES 4 +struct cbfs_file_cache { + struct cbfs_file_descriptor files[MAX_CBFS_OPEN_FILES]; +}; -#include "cbfs_core.c" +static struct cbfs_file_cache g_cbfs_files CAR_GLOBAL; -#ifndef __SMM__ -static inline int tohex4(unsigned int c) +static struct cbfs_file_cache *get_cache(void) { - return (c <= 9) ? (c + '0') : (c - 10 + 'a'); + return car_get_var_ptr(&g_cbfs_files); } -static void tohex16(unsigned int val, char* dest) +static int cbfs_fd_available(const struct cbfs_file_descriptor *fd) { - dest[0] = tohex4(val>>12); - dest[1] = tohex4((val>>8) & 0xf); - dest[2] = tohex4((val>>4) & 0xf); - dest[3] = tohex4(val & 0xf); + return !!(fd->content.size == 0 && fd->metadata.size == 0); } -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device, void *dest) +static void cbfs_fd_mark_free(const struct cbfs_file_descriptor *cfd) { - char name[17] = "pciXXXX,XXXX.rom"; - struct cbfs_optionrom *orom; - uint8_t *src; + struct cbfs_file_descriptor *fd = (struct cbfs_file_descriptor *)cfd; + memset(fd, 0, sizeof(*fd)); + fd->rh = INVALID_RHANDLE; +} - tohex16(vendor, name+3); - tohex16(device, name+8); +static struct cbfs_file_descriptor *get_available_file(void) +{ + int i; + struct cbfs_file_cache *cache = get_cache(); - orom = (struct cbfs_optionrom *) - cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); + for (i = 0; i < MAX_CBFS_OPEN_FILES; i++) { + if (cbfs_fd_available(&cache->files[i])) + return &cache->files[i]; + } + + return NULL; +} - if (orom == NULL) +static void cbfs_fd_add_metadata(struct cbfs_file_descriptor *fd, size_t sz) +{ + fd->metadata.size += sz; + fd->content.offset += sz; + fd->content.size -= sz; +} + +static const struct cbfs_file_descriptor * +allocate_file(const struct cbfs_descriptor *cbfs, const struct cbfs_file *file, + offset_t offset) +{ + struct cbfs_file_descriptor *fd; + + fd = get_available_file(); + + if (fd == NULL) return NULL; - /* They might have specified a dest address. If so, we can decompress. - * If not, there's not much hope of decompressing or relocating the rom. - * in the common case, the expansion rom is uncompressed, we - * pass 0 in for the dest, and all we have to do is find the rom and - * return a pointer to it. - */ + fd->rh = cbfs->rh; + fd->metadata.offset = file->offset + offset; + fd->metadata.size = 0; + fd->content.offset = file->offset + offset; + fd->content.size = file->len; - /* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ - src = (uint8_t *)orom; // + sizeof(struct cbfs_optionrom); + if (file->type != CBFS_TYPE_STAGE || file->type != CBFS_TYPE_PAYLOAD) + return fd; - if (! dest) - return src; + if (file->type == CBFS_TYPE_STAGE) { + cbfs_fd_add_metadata(fd, sizeof(struct cbfs_stage)); + return fd; + } - if (!cbfs_decompress(ntohl(orom->compression), - src, - dest, - ntohl(orom->len))) + /* Parse payload segments. */ + while (offset + sizeof(struct cbfs_payload_segment) <= file->len) { + struct cbfs_payload_segment segment; + ssize_t read_sz; + + read_sz = region_readat(cbfs->rh, &segment, offset, + sizeof(segment)); + if (read_sz != sizeof(segment)) { + cbfs_fd_mark_free(fd); + return NULL; + } + + switch (segment.type) { + case PAYLOAD_SEGMENT_CODE: + case PAYLOAD_SEGMENT_DATA: + case PAYLOAD_SEGMENT_BSS: + case PAYLOAD_SEGMENT_PARAMS: + cbfs_fd_add_metadata(fd, sizeof(segment)); + break; + case PAYLOAD_SEGMENT_ENTRY: + cbfs_fd_add_metadata(fd, sizeof(segment)); + return fd; + default: + cbfs_fd_mark_free(fd); + return NULL; + } + } + + cbfs_fd_mark_free(fd); + return NULL; +} + +static offset_t +cbfs_next_offset(offset_t offset, size_t align, size_t increment) +{ + offset += increment; + if (offset % align) + offset += align - (offset % align); + return offset; +} + +static const struct cbfs_file_descriptor * +__cbfs_open(const struct cbfs_descriptor *cbfs,const char *name, + uint32_t *type) +{ + const struct cbfs_file_descriptor *fd; + struct cbfs_file file; + ssize_t read_sz; + offset_t offset; + size_t cbfs_sz; + size_t align; + rhandle_t rh; + + if (cbfs == NULL || name == NULL) return NULL; - return dest; + offset = 0; + rh = cbfs->rh; + align = cbfs->align; + cbfs_sz = cbfs->size; + fd = NULL; + + while (offset + sizeof(file) < cbfs_sz) { + char *file_name; + size_t name_sz; + size_t entry_sz; + int found; + + read_sz = region_readat(rh, &file, offset, sizeof(file)); + if (read_sz != sizeof(file)) + return NULL; + + if (memcmp(CBFS_FILE_MAGIC, file.magic, sizeof(file.magic))) { + offset = cbfs_next_offset(offset, align, align); + continue; + } + + file.len = ntohl(file.len); + file.type = ntohl(file.type); + file.offset = ntohl(file.offset); + entry_sz = file.len + file.offset; + + /* File type doesn't match. */ + if (type != NULL && *type != file.type) { + offset = cbfs_next_offset(offset, align, entry_sz); + continue; + } + name_sz = file.offset - sizeof(file); + file_name = region_mmap(rh, offset + sizeof(file), name_sz); + if (file_name == NULL) { + offset = cbfs_next_offset(offset, align, entry_sz); + continue; + } + + found = !strcmp(file_name, name); + region_munmap(rh, file_name); + + if (found) { + fd = allocate_file(cbfs, &file, offset); + break; + } + } + + return fd; } -void * cbfs_load_stage(struct cbfs_media *media, const char *name) +const struct cbfs_file_descriptor * +cbfs_open_by_name(const struct cbfs_descriptor *cbfs, const char *name) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); - /* this is a mess. There is no ntohll. */ - /* for now, assume compatible byte order until we solve this. */ - uint32_t entry; - uint32_t final_size; + return __cbfs_open(cbfs, name, NULL); +} - if (stage == NULL) - return (void *) -1; +const struct cbfs_file_descriptor * +cbfs_open_by_name_type(const struct cbfs_descriptor *cbfs, + const char *name, uint32_t type) +{ + return __cbfs_open(cbfs, name, &type); +} - LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", - name, - (uint32_t) stage->load, stage->memlen, - stage->entry); +void cbfs_file_close(const struct cbfs_file_descriptor *file) +{ + if (file != NULL) + cbfs_fd_mark_free(file); +} - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); - if (!final_size) - return (void *) -1; +ssize_t cbfs_file_content_size(const struct cbfs_file_descriptor *fd) +{ + if (fd == NULL) + return -1; - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); + return fd->content.size; +} + +ssize_t cbfs_file_metadata_size(const struct cbfs_file_descriptor *fd) +{ + if (fd == NULL) + return -1; + + return fd->metadata.size; +} + +ssize_t cbfs_file_read_content(const struct cbfs_file_descriptor *fd, + void *buf, offset_t offset, size_t size) +{ + struct region region = { + .offset = offset, + .size = size, + }; - DEBUG("stage loaded.\n"); + if (fd == NULL) + return -1; - entry = stage->entry; - // entry = ntohll(stage->entry); + if (!region_contained(&fd->content, &region)) + return -1; - return (void *) entry; + return region_readat(fd->rh, buf, fd->content.offset + offset, size); } -/* Simple buffer */ +void *cbfs_file_map_content(const struct cbfs_file_descriptor *fd, + offset_t offset, size_t size) +{ + struct region region = { + .offset = offset, + .size = size, + }; -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated; - DEBUG("simple_buffer_map(offset=%zd, count=%zd): " - "allocated=%zd, size=%zd, last_allocate=%zd\n", - offset, count, buffer->allocated, buffer->size, - buffer->last_allocate); - if (buffer->allocated + count >= buffer->size) - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - if (media->read(media, address, offset, count) != count) { - ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", - count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - buffer->allocated += count; - buffer->last_allocate = count; - return address; -} - -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { - // TODO Add simple buffer management so we can free more than last - // allocated one. - DEBUG("simple_buffer_unmap(address=0x%p): " - "allocated=%zd, size=%zd, last_allocate=%zd\n", - address, buffer->allocated, buffer->size, - buffer->last_allocate); - if ((buffer->buffer + buffer->allocated - buffer->last_allocate) == - address) { - buffer->allocated -= buffer->last_allocate; - buffer->last_allocate = 0; - } - return NULL; + if (fd == NULL) + return NULL; + + if (!region_contained(&fd->content, &region)) + return NULL; + + return region_mmap(fd->rh, fd->content.offset + offset, size); } -/** - * run_address is passed the address of a function taking no parameters and - * jumps to it, returning the result. - * @param f the address to call as a function. - * @return value returned by the function. - */ +ssize_t cbfs_file_read_metadata(const struct cbfs_file_descriptor *fd, + void *buf, offset_t offset, size_t size) +{ + struct region region = { + .offset = offset, + .size = size, + }; + + if (fd == NULL) + return -1; -int run_address(void *f) + if (!region_contained(&fd->metadata, &region)) + return -1; + + return region_readat(fd->rh, buf, fd->metadata.offset + offset, size); +} + +void *cbfs_file_map_metadata(const struct cbfs_file_descriptor *fd) { - int (*v) (void); - v = f; - return v(); + if (fd == NULL) + return NULL; + + return region_mmap(fd->rh, fd->metadata.offset, fd->metadata.size); } +void cbfs_file_unmap(const struct cbfs_file_descriptor *fd, void *addr) +{ + if (fd == NULL) + return; + + region_munmap(fd->rh, addr); +} + +#ifndef __SMM__ +size_t cbfs_file_inflate(const struct cbfs_file_descriptor *fd, + offset_t offset, size_t src_sz, void *dest) +{ +#if defined(CBFS_WITH_LZMA) + void *src; + size_t dest_sz; + + src = cbfs_file_map_content(fd, offset, src_sz); + + if (src == NULL) + return 0; + + dest_sz = ulzma(src, dest); + + cbfs_file_unmap(fd, src); + + return dest_sz; +#else + return 0; +#endif +} + +void *cbfs_load_stage(const struct cbfs_descriptor *cbfs, const char *name) +{ + struct cbfs_stage stage; + const struct cbfs_file_descriptor *file; + size_t inflated_sz; + ssize_t metadata_sz; + ssize_t file_sz; + uint8_t *dest; + void *entry; + + entry = NULL; + file = cbfs_open_by_name_type(cbfs, name, CBFS_TYPE_STAGE); + + if (file == NULL) + return NULL; + + metadata_sz = cbfs_file_read_metadata(file, &stage, 0, sizeof(stage)); + if (metadata_sz != sizeof(stage)) + goto out; + + file_sz = cbfs_file_content_size(file); + if (file_sz < 0) + goto out; + + printk(BIOS_INFO, + "Loading stage '%s' 0x%llx (%d bytes), entry point 0x%llx\n", + name, (long long) stage.load, stage.memlen, + (long long)stage.entry); + + dest = (void *)(uintptr_t)stage.load; + inflated_sz = stage.memlen; + + switch (stage.compression) { + case CBFS_COMPRESS_NONE: + if (cbfs_file_read_content(file, dest, 0, file_sz) != file_sz) + goto out; + break; +#if defined(CBFS_WITH_LZMA) + case CBFS_COMPRESS_LZMA: + inflated_sz = cbfs_file_inflate(file, 0, file_sz, dest); + if (inflated_sz == 0) + goto out; + break; +#endif + default: + printk(BIOS_ERR,"Invalid compression scheme: %d\n", + stage.compression); + goto out; + } + + if (inflated_sz > stage.memlen) { + printk(BIOS_ERR,"Inflated size %zu > memory size %zu.\n", + inflated_sz, stage.memlen); + goto out; + } + + /* Stages rely the below clearing so that the bss is initialized. */ + memset(dest + inflated_sz, 0, stage.memlen - inflated_sz); + + printk(BIOS_DEBUG,"stage loaded.\n"); + + entry = (void *)(uintptr_t)stage.entry; + +out: + cbfs_file_close(file); + return entry; +} #endif diff --git a/src/lib/cbfs_boot_region.c b/src/lib/cbfs_boot_region.c new file mode 100644 index 0000000..e689031 --- /dev/null +++ b/src/lib/cbfs_boot_region.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/early_variables.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <cbfs.h> +#include <cbfs_core.h> +#include <region.h> + +static struct cbfs_descriptor g_cbfs_descriptor CAR_GLOBAL; + +const struct cbfs_descriptor *cbfs_default_descriptor(void) +{ + return car_get_var_ptr(&g_cbfs_descriptor); +} + +static const struct region_device cbfs_dev = { + .region = { + .offset = CONFIG_ROM_SIZE - CONFIG_CBFS_SIZE, + .size = CONFIG_CBFS_SIZE, + }, +}; + +#if IS_ENABLED(CONFIG_ARCH_X86) +static offset_t get_header_offset(rhandle_t rh) +{ + int32_t header_offset; + offset_t off; + ssize_t rsize; + + rsize = region_size(rh); + off = rsize - sizeof(header_offset); + region_readat(rh, &header_offset, off, sizeof(header_offset)); + return rsize + header_offset; +} +#else +static inline offset_t get_header_offset(rhandle_t rh) +{ + return CONFIG_CBFS_HEADER_ROM_OFFSET; +} +#endif + +void cbfs_default_media_initialize(void) +{ + rhandle_t rh; + offset_t header_offset; + struct cbfs_header *hdr; + size_t cbfs_size; + struct cbfs_descriptor *cbfs_desc; + + /* Already initialized. */ + rh = region_locate(DEFAULT_CBFS_REGION_NAME); + if (rhandle_valid(rh)) + return; + + /* Mark region as invalid. */ + cbfs_desc = (struct cbfs_descriptor *)cbfs_default_descriptor(); + cbfs_desc->rh = INVALID_RHANDLE; + + /* CBFS provides a readonly view of the rom. */ + rh = region_locate(BOOTRO_REGION_NAME); + + if (!rhandle_valid(rh)) { + printk(BIOS_ERR, "Couldn't find boot region to register .\n"); + return; + } + + header_offset = get_header_offset(rh); + hdr = region_mmap(rh, header_offset, sizeof(*hdr)); + + if (hdr == NULL) { + printk(BIOS_ERR, "Couldn't mmap() cbfs header.\n"); + return; + } + + if (CBFS_HEADER_MAGIC != ntohl(hdr->magic)) { + printk(BIOS_ERR, "Invalid CBFS magic @ 0x%zx: %x vs %x\n", + (size_t)header_offset, CBFS_HEADER_MAGIC, + ntohl(hdr->magic)); + goto out; + } + + if (cbfs_dev.region.offset != ntohl(hdr->offset)) { + printk(BIOS_ERR, "CBFS offset doesn't match: 0x%zx vs 0x%zx\n", + (size_t)cbfs_dev.region.offset, + (size_t)ntohl(hdr->offset)); + goto out; + } + + cbfs_size = ntohl(hdr->romsize) - ntohl(hdr->offset); + + if (cbfs_dev.region.size != cbfs_size) { + printk(BIOS_ERR, "CBFS size doesn't match: 0x%zx vs 0x%zx\n", + cbfs_dev.region.size, cbfs_size); + goto out; + } + +#if IS_ENABLED(CONFIG_ARCH_X86) + cbfs_size -= htonl(hdr->bootblocksize); +#endif + + cbfs_desc->align = ntohl(hdr->align); + cbfs_desc->size = cbfs_size; + + cbfs_desc->rh = region_register_subregion(DEFAULT_CBFS_REGION_NAME, + &cbfs_dev, rh); + if (!rhandle_valid(cbfs_desc->rh)) + printk(BIOS_ERR, "Unable to register default CBFS region.\n"); + +out: + region_munmap(rh, hdr); +} diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c deleted file mode 100644 index 50c037e..0000000 --- a/src/lib/cbfs_core.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 secunet Security Networks AG - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* The CBFS core requires a couple of #defines or functions to adapt it to the - * target environment: - * - * CBFS_CORE_WITH_LZMA (must be #define) - * if defined, ulzma() must exist for decompression of data streams - * - * CBFS_HEADER_ROM_ADDRESS - * ROM address (offset) of CBFS header. Underlying CBFS media may interpret - * it in other way so we call this "address". - * - * ERROR(x...) - * print an error message x (in printf format) - * - * LOG(x...) - * print a message x (in printf format) - * - * DEBUG(x...) - * print a debug message x (in printf format) - * - */ - -#include <cbfs.h> -#include <string.h> - -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) -{ - const struct cbfs_header *header; - struct cbfs_media default_media; - - if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } - } - - media->open(media); - DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, - CONFIG_ROM_SIZE); - header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); - media->close(media); - - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("Failed to load CBFS header from 0x%x\n", - CBFS_HEADER_ROM_ADDRESS); - return CBFS_HEADER_INVALID_ADDRESS; - } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { - ERROR("Could not find valid CBFS master header at %x: " - "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, - ntohl(header->magic)); - if (header->magic == 0xffffffff) { - ERROR("Maybe ROM is not mapped properly?\n"); - } - return CBFS_HEADER_INVALID_ADDRESS; - } - return header; -} - -/* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) -{ - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; - struct cbfs_media default_media; - - if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return NULL; - } - } - - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; - - // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); - - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. -#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - romsize -= htonl(header->bootblocksize); -#endif - DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); - media->open(media); - while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { - uint32_t new_align = align; - if (offset % align) - new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); - offset += new_align; - continue; - } - name_len = ntohl(file.offset) - sizeof(file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); - media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - return file_ptr; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } - - // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); - if (offset % align) - offset += align - (offset % align); - } - media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return NULL; -} - -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) -{ - struct cbfs_file *file = cbfs_get_file(media, name); - - if (sz) - *sz = 0; - - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); - return NULL; - } - - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); - return NULL; - } - - if (sz) - *sz = ntohl(file->len); - - return (void *)CBFS_SUBHEADER(file); -} - -int cbfs_decompress(int algo, void *src, void *dst, int len) -{ - switch (algo) { - case CBFS_COMPRESS_NONE: - /* Reads need to be aligned at 4 bytes to avoid - poor flash performance. */ - while (len && ((u32)src & 3)) { - *(u8*)dst++ = *(u8*)src++; - len--; - } - memmove(dst, src, len); - return len; -#ifdef CBFS_CORE_WITH_LZMA - case CBFS_COMPRESS_LZMA: - return ulzma(src, dst); -#endif - default: - ERROR("tried to decompress %d bytes with algorithm #%x," - "but that algorithm id is unsupported.\n", len, - algo); - return 0; - } -} - diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..31ad7e6 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -18,20 +18,30 @@ */ #include <cbfs.h> +#include <cbfs_core.h> #include <payload_loader.h> static int cbfs_locate_payload(struct payload *payload) { void *buffer; size_t size; - const int type = CBFS_TYPE_PAYLOAD; + const struct cbfs_file_descriptor *fd; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + fd = cbfs_open_by_name_type(cbfs_default_descriptor(), payload->name, + CBFS_TYPE_PAYLOAD); - if (buffer == NULL) + if (fd == NULL) return -1; + size = cbfs_file_content_size(fd); + buffer = cbfs_file_map_content(fd, 0, size); + + if (buffer == NULL) { + cbfs_file_close(fd); + return -1; + } + + payload->fd = fd; payload->backing_store.data = buffer; payload->backing_store.size = size; diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c index 5d5cc0b..5d5edd8 100644 --- a/src/lib/loaders/cbfs_ramstage_loader.c +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -34,7 +34,8 @@ static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, .name = name, }; - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + if (rmodule_stage_load_from_cbfs(cbfs_default_descriptor(), + &rmod_ram)) { printk(BIOS_DEBUG, "Could not load ramstage.\n"); return NULL; } @@ -49,14 +50,7 @@ static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, const struct cbmem_entry **cbmem_entry) { - void *entry; - - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); - - if ((void *)entry == (void *) -1) - entry = NULL; - - return entry; + return cbfs_load_stage(cbfs_default_descriptor(), name); } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..ac4e7bf 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,8 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); + printk(BIOS_DEBUG, "%s: located payload, %zu bytes.\n", + ops->name, payload->backing_store.size); break; } diff --git a/src/lib/region.c b/src/lib/region.c new file mode 100644 index 0000000..bf952f3 --- /dev/null +++ b/src/lib/region.c @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/early_variables.h> +#include <region.h> +#include <vendorcode/google/chromeos/fmap.h> + +/* MAX_REGIONS could be configurable. */ +#define MAX_REGIONS 6 + +struct region_registry_entry { + rhandle_t parent_slot; + const char *name; + const struct region_device *rdev; +}; + +struct region_registry { + struct region_registry_entry entries[MAX_REGIONS]; +}; + +static struct region_registry g_regions CAR_GLOBAL; + +static inline struct region_registry *get_registry(void) +{ + return car_get_var_ptr(&g_regions); +} + +static const struct region_registry_entry * +registry_entry_lookup(const struct region_registry *rr, rhandle_t rh) +{ + if (rh < 0 || rh >= MAX_REGIONS) + return NULL; + + return &rr->entries[rh]; +} + +int region_contained(const struct region *parent, const struct region *child) +{ + if (child->size > parent->size) + return 0; + + if (child->offset >= parent->size) + return 0; + + if ((child->offset + child->size) > parent->size) + return 0; + + return 1; +} + +static rhandle_t __region_register(struct region_registry *rr, const char *name, + const struct region_device *rdev, + rhandle_t parent) +{ + rhandle_t slot; + + for (slot = 0; slot < MAX_REGIONS; slot++) { + struct region_registry_entry *entry = &rr->entries[slot]; + + /* Find an empty slot. */ + if (entry->rdev != NULL) + continue; + + entry->parent_slot = parent; + entry->name = name; + entry->rdev = rdev; + return slot; + } + + return INVALID_RHANDLE; +} + +rhandle_t region_register(const char *name, const struct region_device *rdev) +{ + if (name == NULL || rdev == NULL || rdev->ops == NULL) + return INVALID_RHANDLE; + + return __region_register(get_registry(), name, rdev, INVALID_RHANDLE); +} + +rhandle_t region_register_subregion(const char *name, + const struct region_device *rdev, + rhandle_t parent) +{ + struct region_registry *rr; + + /* Subregions require NULL ops. */ + if (name == NULL || rdev == NULL || rdev->ops != NULL) + return INVALID_RHANDLE; + + rr = get_registry(); + + /* Parent is invalid. */ + if (registry_entry_lookup(rr, parent) == NULL) + return INVALID_RHANDLE; + + return __region_register(rr, name, rdev, parent); +} + +/* Locate a region of provided name. */ +rhandle_t region_locate(const char *name) +{ + rhandle_t slot; + struct region_registry *rr; + + if (name == NULL) + return INVALID_RHANDLE; + + rr = get_registry(); + + for (slot = 0; slot < MAX_REGIONS; slot++) { + const struct region_registry_entry *entry = &rr->entries[slot]; + + /* No more valid entries. */ + if (entry->rdev == NULL) + break; + + if (!strcmp(entry->name, name)) + return slot; + } + return INVALID_RHANDLE; +} + +/* + * Obtain the appropriate region_device while optionally translating the + * region into the parent's domain. + */ +static const struct region_device * +find_parent(rhandle_t rh, struct region *region) +{ + const struct region_registry_entry *entry; + struct region_registry *rr; + + rr = get_registry(); + entry = registry_entry_lookup(rr, rh); + + if (entry == NULL) + return NULL; + + if (region != NULL && !region_contained(&entry->rdev->region, region)) + return NULL; + + while (entry->rdev->ops == NULL) { + /* Translate the region into the parent's view. */ + if (region != NULL) + region->offset += entry->rdev->region.offset; + entry = &rr->entries[entry->parent_slot]; + } + + return entry->rdev; +} + +ssize_t region_readat(rhandle_t rh, void *buf, offset_t offset, size_t count) +{ + const struct region_device *rdev; + struct region region = { + .offset = offset, + .size = count, + }; + + rdev = find_parent(rh, &region); + + if (rdev == NULL || rdev->ops->readat == NULL) + return -1; + + return rdev->ops->readat(rdev, buf, offset, count); +} + +ssize_t region_writeat(rhandle_t rh, void *buf, offset_t offset, size_t count) +{ + const struct region_device *rdev; + struct region region = { + .offset = offset, + .size = count, + }; + + rdev = find_parent(rh, &region); + + if (rdev == NULL || rdev->ops->writeat == NULL) + return -1; + + return rdev->ops->writeat(rdev, buf, offset, count); +} + +ssize_t region_eraseat(rhandle_t rh, offset_t offset, size_t count) +{ + const struct region_device *rdev; + struct region region = { + .offset = offset, + .size = count, + }; + + rdev = find_parent(rh, &region); + + if (rdev == NULL || rdev->ops->eraseat == NULL) + return -1; + + return rdev->ops->eraseat(rdev, offset, count); +} + +void *region_mmap(rhandle_t rh, offset_t offset, size_t count) +{ + const struct region_device *rdev; + struct region region = { + .offset = offset, + .size = count, + }; + + if (count == 0) + return NULL; + + rdev = find_parent(rh, &region); + + if (rdev == NULL || rdev->ops->mmap == NULL) + return NULL; + + return rdev->ops->mmap(rdev, offset, count); +} + +void region_munmap(rhandle_t rh, void *addr) +{ + const struct region_device *rdev; + + rdev = find_parent(rh, NULL); + + if (rdev == NULL || rdev->ops->munmap == NULL) + return; + + return rdev->ops->munmap(rdev, addr); +} + +ssize_t region_size(rhandle_t rh) +{ + const struct region_registry_entry *entry; + + entry = registry_entry_lookup(get_registry(), rh); + + if (entry == NULL) + return -1; + + return entry->rdev->region.size; +} + +void boot_region_init(void) +{ + boot_media_initialize(); + cbfs_default_media_initialize(); + fmap_initialize(); +} + +/* Provide weak default. */ +void __attribute__((weak)) bootrw_media_initialize(void) {} + +#if !defined(__PRE_RAM__) +#include <bootstate.h> +static void regions_bscb(void *unused) +{ + boot_region_init(); +} + +BOOT_STATE_INIT_ENTRIES(regions_init) = { + BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, + regions_bscb, NULL), +}; +#endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 2cb70b8..33481b2 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -21,6 +21,9 @@ #include <stdlib.h> #include <string.h> #include <console/console.h> +#include <cbfs.h> +#include <cbfs_core.h> +#include <lib.h> #include <rmodule.h> /* Change this define to get more verbose debugging for module loading. */ @@ -305,11 +308,12 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, #include <cbmem.h> #include <cbfs_core.h> -int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) +int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage, + void *data) { struct rmodule rmod_stage; size_t region_size; - char *stage_region; + unsigned char *stage_region; int rmodule_offset; int load_offset; const struct cbmem_entry *cbmem_entry; @@ -331,8 +335,12 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", rsl->name, &stage_region[rmodule_offset], stage->memlen); - if (!cbfs_decompress(stage->compression, &stage[1], - &stage_region[rmodule_offset], stage->len)) + if (stage->compression == CBFS_COMPRESS_NONE) { + memcpy(data, &stage_region[rmodule_offset], stage->len); + } else if (stage->compression == CBFS_COMPRESS_LZMA) { + if (!ulzma(data, &stage_region[rmodule_offset])) + return -1; + } else return -1; if (rmodule_parse(&stage_region[rmodule_offset], &rmod_stage)) @@ -347,17 +355,35 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) return 0; } -int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) +int rmodule_stage_load_from_cbfs(const struct cbfs_descriptor *cbfs, + struct rmod_stage_load *rsl) { - struct cbfs_stage *stage; + const struct cbfs_file_descriptor *fd; + struct cbfs_stage stage; + size_t rdsz = sizeof(stage); + int ret; + void *buf; - stage = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - rsl->name, CBFS_TYPE_STAGE, NULL); + fd = cbfs_open_by_name_type(cbfs, rsl->name, CBFS_TYPE_STAGE); - if (stage == NULL) + if (fd == NULL) return -1; - return rmodule_stage_load(rsl, stage); + ret = -1; + if (cbfs_file_read_metadata(fd, &stage, 0, rdsz) != rdsz) + goto out; + + buf = cbfs_file_map_content(fd, 0, cbfs_file_content_size(fd)); + if (buf == NULL) + goto out; + + ret = rmodule_stage_load(rsl, &stage, buf); + + cbfs_file_unmap(fd, buf); + +out: + cbfs_file_close(fd); + return ret; } #endif /* DYNAMIC_CBMEM */ diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index feff03e..b6c8797 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <string.h> #include <cbfs.h> +#include <cbfs_core.h> #include <lib.h> #include <bootmem.h> #include <payload_loader.h> @@ -40,7 +41,7 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; + unsigned long s_srcoffset; unsigned long s_memsz; unsigned long s_filesz; int compression; @@ -140,7 +141,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_srcoffset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +177,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_srcoffset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -213,17 +214,12 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( - struct segment *head, + struct segment *head, struct cbfs_payload_segment *segment, struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; while(1) { printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); @@ -237,43 +233,39 @@ static int build_self_segment_list( case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment->compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment->load_addr; + new->s_memsz = segment->mem_len; + new->compression = segment->compression; + + new->s_srcoffset = segment->offset; + new->s_filesz = segment->len; + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcoffset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_srcoffset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr, new->s_memsz, new->s_srcoffset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment->load_addr, + segment->mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_srcoffset = segment->offset; + new->s_dstaddr = segment->load_addr; + new->s_memsz = segment->mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment->load_addr); + *entry = segment->load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -292,17 +284,11 @@ static int build_self_segment_list( /* We have found another CODE, DATA or BSS segment */ segment++; - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Add to end of list. */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } return 1; @@ -315,6 +301,7 @@ static int load_self_segments( struct segment *ptr; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + unsigned char *srcaddr = payload->backing_store.data; for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -378,7 +365,7 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + src = srcaddr + ptr->s_srcoffset; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -441,13 +428,51 @@ static int load_self_segments( return 1; } +static void +parse_cbfs_segments(struct cbfs_payload_segment *segments, size_t size) +{ + int i; + int num; + + num = size / sizeof(struct cbfs_payload_segment); + + for (i = 0; i < num; i++) { + /* Note: the type field is in host order. */ + segments[i].compression = ntohl(segments[i].compression); + segments[i].offset = ntohl(segments[i].offset); + /* Fix up the offsets to be relative to the data stream. */ + segments[i].offset -= size; + segments[i].load_addr = ntohll(segments[i].load_addr); + segments[i].len = ntohl(segments[i].len); + segments[i].mem_len = ntohl(segments[i].mem_len); + } +} + void *selfload(struct payload *payload) { uintptr_t entry = 0; struct segment head; + ssize_t metadata_sz; + struct cbfs_payload_segment *segments; + + metadata_sz = cbfs_file_metadata_size(payload->fd); + + if (metadata_sz <= 0) + return NULL; + + segments = malloc(sizeof(struct cbfs_payload_segment)); + + if (segments == NULL) + return NULL; + + if (cbfs_file_read_metadata(payload->fd, segments, 0, metadata_sz) != + metadata_sz) + return NULL; + + parse_cbfs_segments(segments, metadata_sz); /* Preprocess the self segments */ - if (!build_self_segment_list(&head, payload, &entry)) + if (!build_self_segment_list(&head, segments, payload, &entry)) goto out; /* Load the segments */ diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 2360b36..63b5c89 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y + select BOOT_REGION_SPI_FLASH select CACHE_MRC_SETTINGS select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/baytrail/mrc_cache.c index 5613761..784952d 100644 --- a/src/soc/intel/baytrail/mrc_cache.c +++ b/src/soc/intel/baytrail/mrc_cache.c @@ -20,6 +20,7 @@ #include <string.h> #include <console/console.h> #include <cbmem.h> +#include <region.h> #include <ip_checksum.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> @@ -40,11 +41,20 @@ struct mrc_data_region { static int mrc_cache_get_region(struct mrc_data_region *region) { #if CONFIG_CHROMEOS - int ret; - ret = find_fmap_entry("RW_MRC_CACHE", &region->base); - if (ret >= 0) { - region->size = ret; - return 0; + offset_t offset; + size_t size; + if (!fmap_locate("RW_MRC_CACHE", &offset, &size)) { + void *mapping; + rhandle_t rh; + + rh = region_locate(BOOTRO_REGION_NAME); + mapping = region_mmap(rh, offset, size); + + if (mapping != NULL) { + region->base = mapping; + region->size = size; + return 0; + } } #endif region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE; diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index dccc801..44d67ae 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -24,26 +24,25 @@ #include <spi-generic.h> #include <spi_flash.h> #include <baytrail/nvm.h> +#include <region.h> /* This module assumes the flash is memory mapped just below 4GiB in the * address space for reading. Also this module assumes an area it erased * when all bytes read as all 0xff's. */ -static struct spi_flash *flash; +static rhandle_t rwrh = INVALID_RHANDLE; static int nvm_init(void) { - if (flash != NULL) + if (rhandle_valid(rwrh)) return 0; - spi_init(); - flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return -1; - } + rwrh = region_locate(BOOTRW_REGION_NAME); - return 0; + if (rhandle_valid(rwrh)) + return 0; + + return -1; } /* Convert memory mapped pointer to flash offset. */ @@ -69,7 +68,10 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + + if (region_eraseat(rwrh, to_flash_offset(start), size) != size) + return -1; + return 0; } @@ -78,6 +80,9 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + + if (region_eraseat(rwrh, to_flash_offset(start), size) != size) + return -1; + return 0; } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 7bcd54f..496e755 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -105,6 +105,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) int ret; mrc_wrapper_entry_t mrc_entry; const struct mrc_saved_data *cache; + const struct cbfs_file_descriptor *fd; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; @@ -118,10 +119,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) printk(BIOS_DEBUG, "No MRC cache found.\n"); } - mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, - NULL); + fd = cbfs_open_by_name_type(cbfs_default_descriptor(), "mrc.bin", 0xab); + mrc_entry = cbfs_file_map_content(fd, 0, cbfs_file_content_size(fd)); if (mrc_entry == NULL) { + cbfs_file_close(fd); printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } @@ -130,6 +132,9 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) ret = mrc_entry(mp); + cbfs_file_unmap(fd, mrc_entry); + cbfs_file_close(fd); + print_dram_info(); cbmem_initialize_empty(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5af9bf4..0e3bf7d 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -29,6 +29,7 @@ #include <ec/google/chromeec/ec.h> #endif #include <elog.h> +#include <region.h> #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> @@ -133,6 +134,9 @@ void * asmlinkage romstage_main(unsigned long bist, google_chromeec_early_init(); #endif + /* Initialize the boot media. */ + boot_media_initialize(); + /* Call into mainboard. */ mainboard_romstage_entry(&rp); diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 007bd57..24afb2c 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += fmap.c ramstage-y += fmap.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c smm-y += fmap.c +smm-y += ../../../lib/region.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/chromeos.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index e917ba1..6f20109 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -121,10 +121,14 @@ static int vboot_locate_payload(struct payload *payload) if (buffer == NULL) return -1; +#if 0 payload->backing_store.data = buffer; payload->backing_store.size = size; return 0; +#endif + /* TODO: fake a cbfs. Also need this in rmodule loading. */ + return -1; } const struct payload_loader_ops vboot_payload_loader = { diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c index 538b8c3..e0ad7c0 100644 --- a/src/vendorcode/google/chromeos/fmap.c +++ b/src/vendorcode/google/chromeos/fmap.c @@ -20,97 +20,131 @@ #include <stdint.h> #include <stddef.h> #include <string.h> +#include <arch/early_variables.h> #include <console/console.h> +#include <region.h> #include "fmap.h" -/* Find FMAP data structure in ROM. +/* * See http://code.google.com/p/flashmap/ for more information on FMAP. */ -const struct fmap *fmap_find(void) -{ - /* FIXME: Get rid of the hard codes. The "easy" way would be to - * do a binary search, but since ROM accesses are slow, we don't - * want to spend a lot of time looking for the FMAP. An elegant - * solution would be to store a pointer to the FMAP in the CBFS - * master header; that would require some more changes to cbfstool - * and possibly cros_bundle_firmware. - */ - - /* wrapping around 0x100000000 */ - const struct fmap *fmap = (void *) - (CONFIG_FLASHMAP_OFFSET - CONFIG_ROM_SIZE); - if (memcmp(fmap, FMAP_SIGNATURE, sizeof(FMAP_SIGNATURE)-1)) { - printk(BIOS_DEBUG, "No FMAP found at %p.\n", fmap); - return NULL; - } +/* + * The reason for the global state is that FMAP needs to be available in + * romstage on x86 machines. This necessitates keeping some global variables + * around because there is no malloc or global modifiable data without being + * placed in BSS. This code relies on CAR globals being migrated in romstage. + */ - printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %p.\n", - fmap->name, fmap->ver_major, fmap->ver_minor, fmap); - printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n", - (unsigned long long)fmap->base, fmap->size, fmap->nareas); +#define FMAP_REGION_NAME "fmap" + +struct fmap_state { + int registered; + int num_entries; +}; + +static struct fmap_state g_fmap_state CAR_GLOBAL; +static const offset_t fmap_offset = CONFIG_FLASHMAP_OFFSET; - return fmap; +static inline struct fmap_state *get_state(void) +{ + return car_get_var_ptr(&g_fmap_state); } -const struct fmap_area *find_fmap_area(const struct fmap *fmap, - const char name[]) +static const struct region_device fmap_rdev = { + .region = { + .offset = 0, + .size = CONFIG_ROM_SIZE, + }, +}; + +/* Return < 0 on failure, 0 on success */ +static int fmap_init(void) { - const struct fmap_area *area = NULL; - - if (fmap) { - int i; - for (i = 0; i < fmap->nareas; i++) { - if (!strcmp((const char *)fmap->areas[i].name, name)) { - area = &fmap->areas[i]; - break; - } - } - } + struct fmap_state *gs; + rhandle_t rh; + struct fmap *fmap; - if (area) { - printk(BIOS_DEBUG, "FMAP: area %s found\n", name); - printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset); - printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size); - } else { - printk(BIOS_DEBUG, "FMAP: area %s not found\n", name); + gs = get_state(); + + if (gs->registered) + return 1; + + /* Execute this function only once. Default to invalid. */ + gs->registered = 1; + rh = region_locate(BOOTRO_REGION_NAME); + + if (!rhandle_valid(rh)) + return -1; + + fmap = region_mmap(rh, fmap_offset, sizeof(*fmap)); + + if (fmap == NULL) + return -1; + + if (memcmp(fmap, FMAP_SIGNATURE, sizeof(FMAP_SIGNATURE)-1)) { + printk(BIOS_DEBUG, "No FMAP found at %zx.\n", fmap_offset); + region_munmap(rh, fmap); + return -1; } + printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n", + fmap->name, fmap->ver_major, fmap->ver_minor, fmap_offset); + printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n", + (unsigned long long)fmap->base, fmap->size, fmap->nareas); + + gs->num_entries = fmap->nareas; + region_munmap(rh, fmap); + + /* Register fmap device under the boot region. */ + if (!rhandle_valid(region_register_subregion(FMAP_REGION_NAME, + &fmap_rdev, rh))) + return -1; - return area; + return 0; } -int find_fmap_entry(const char name[], void **pointer) +int fmap_locate(const char *name, offset_t *offset, size_t *size) { -#ifndef __PRE_RAM__ - static -#endif - const struct fmap *fmap = NULL; - const struct fmap_area *area; - void *base = NULL; + rhandle_t rh; + struct fmap_area *areas; + struct fmap_state * gs; + int i; + int ret = -1; - if (!fmap) - fmap = fmap_find(); + rh = region_locate(FMAP_REGION_NAME); + gs = get_state(); - area = find_fmap_area(fmap, name); + if (!rhandle_valid(rh) || gs == NULL) + return ret; - if (!area) - return -1; + areas = region_mmap(rh, sizeof(struct fmap) + fmap_offset, + gs->num_entries * sizeof(*areas)); + + if (areas == NULL) { + printk(BIOS_DEBUG, "FMAP: could not map areas.\n"); + return ret; + } + + for (i = 0; i < gs->num_entries; i++) { + if (strncmp((char *)&areas[i].name[0], name, FMAP_STRLEN)) + continue; + printk(BIOS_DEBUG, "FMAP: area %s found\n", name); + printk(BIOS_DEBUG, "FMAP: offset: %x\n", areas[i].offset); + printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", areas[i].size); - /* Right now cros_bundle_firmware does not write a valid - * base address into the FMAP. Hence, if base is 0, assume - * 4GB-8MB as base address. - */ - if (fmap->base) { - base = (void *)(unsigned long)fmap->base; - printk(BIOS_DEBUG, "FMAP: %s base at %p\n", name, base); - } else { - base = (void *)(0 - CONFIG_ROM_SIZE); - printk(BIOS_WARNING, "FMAP: No valid base address, using" - " 0x%p\n", base); + *offset = areas[i].offset; + *size = areas[i].size; + ret = 0; + break; } - *pointer = (void*) ((u32)base + area->offset); - printk(BIOS_DEBUG, "FMAP: %s at %p (offset %x)\n", - name, *pointer, area->offset); - return area->size; + region_munmap(rh, areas); + + return ret; +} + +void fmap_initialize(void) +{ + if (fmap_init() < 0) + printk(BIOS_DEBUG, "FMAP region wasn't registered.\n"); } diff --git a/src/vendorcode/google/chromeos/fmap.h b/src/vendorcode/google/chromeos/fmap.h index a3d2abd..de935e7 100644 --- a/src/vendorcode/google/chromeos/fmap.h +++ b/src/vendorcode/google/chromeos/fmap.h @@ -37,6 +37,7 @@ #define FLASHMAP_LIB_FMAP_H__ #include <stdint.h> +#include <region.h> #define FMAP_SIGNATURE "__FMAP__" #define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ @@ -70,10 +71,24 @@ struct fmap { struct fmap_area areas[]; } __attribute__((packed)); +#if IS_ENABLED(CONFIG_CHROMEOS) +/* + * Initialize the fmap state within coreboot. + */ +void fmap_initialize(void); + +/* + * Locate a region by name within the fmap. offset and size are filled in + * relative to the boot media the global fmap is located. Returns 0 on + * success, < 0 when unable to find the region. + */ +int fmap_locate(const char *name, offset_t *offset, size_t *size); +#else /* IS_ENABLED(CONFIG_CHROMEOS) */ +static inline void fmap_initialize(void) {} +static inline int fmap_locate(const char *name, offset_t *offset, size_t *size) +{ + return -1; +} +#endif /* IS_ENABLED(CONFIG_CHROMEOS) */ -/* coreboot specific function prototypes */ -const struct fmap *fmap_find(void); -const struct fmap_area *find_fmap_area(const struct fmap *fmap, - const char name[]); -int find_fmap_entry(const char name[], void **pointer); #endif /* FLASHMAP_LIB_FMAP_H__*/ diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 0c5220a..98bc1a5 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <stddef.h> #include <cbfs.h> +#include <cbfs_core.h> #include <cbmem.h> #include <console/console.h> #include <console/vtxprintf.h> @@ -45,7 +46,8 @@ static void vboot_run_stub(struct vboot_context *context) }; void (*entry)(struct vboot_context *context); - if (rmodule_stage_load_from_cbfs(&rmod_stage)) { + if (rmodule_stage_load_from_cbfs(cbfs_default_descriptor(), + &rmod_stage)) { printk(BIOS_DEBUG, "Could not load vboot stub.\n"); goto out; } @@ -74,6 +76,30 @@ static void fatal_error(void) hard_reset(); } +static void locate_region(const char *name, void **parea, uint32_t *psize) +{ + offset_t offset; + size_t size; + rhandle_t rh; + + *psize = 0; + *parea = NULL; + + if (fmap_locate(name, &offset, &size)) + return; + + rh = region_locate(BOOTRO_REGION_NAME); + if (!rhandle_valid(rh)) + return; + + /* + * This leaks the mappings on anything but x86 systems which have + * CBFS memory-mapped. + */ + *psize = size; + *parea = region_mmap(rh, offset, size); +} + static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) { VbCommonParams cparams; @@ -105,20 +131,17 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) context.cparams = &cparams; context.fparams = &fparams; - cparams.gbb_size = find_fmap_entry("GBB", &cparams.gbb_data); + locate_region("GBB", &cparams.gbb_data, &cparams.gbb_size); cparams.shared_data_blob = &vboot_handoff->shared_data[0]; cparams.shared_data_size = VB_SHARED_DATA_MIN_SIZE; cparams.caller_context = &context; - fparams.verification_size_A = - find_fmap_entry("VBLOCK_A", &fparams.verification_block_A); - fparams.verification_size_B = - find_fmap_entry("VBLOCK_B", &fparams.verification_block_B); - - context.fw_a_size = - find_fmap_entry("FW_MAIN_A", (void **)&context.fw_a); - context.fw_b_size = - find_fmap_entry("FW_MAIN_B", (void **)&context.fw_b); + locate_region("VBLOCK_A", &fparams.verification_block_A, + &fparams.verification_size_A); + locate_region("VBLOCK_B", &fparams.verification_block_B, + &fparams.verification_size_B); + locate_region("FW_MAIN_A", (void **)&context.fw_a, &context.fw_a_size); + locate_region("FW_MAIN_B", (void **)&context.fw_b, &context.fw_b_size); /* Check all fmap entries. */ if (context.fw_a == NULL || context.fw_b == NULL || @@ -195,7 +218,7 @@ static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, stage = (void *)fwc->address; - if (rmodule_stage_load(&rmod_load, stage)) { + if (rmodule_stage_load(&rmod_load, stage, &stage[1])) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); return NULL;

1 0

Patch set updated for coreboot: b51f6b9 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments
by Alexandru Gagniuc 17 Mar '14

17 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5388 -gerrit commit b51f6b9a111ab4b06b912e9a1bcde054db948e03 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 16 00:15:57 2014 +0100 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments cbfstool fails to built under 32-bit platforms since commit * aa2f739a cbfs: fix issues with word size and endianness. due to the use of '%ld' format specifier on size_t, which on these platforms is only 32-bit. No error is seen when building a coreboot image which indirectly builds cbfstool at `build/cbfstool` too. Use the length modifier `z` for size_t arguments, and cast to size_t where apropriate. Change-Id: Id84a20fbf237376a31f7e4816bd139463800c977 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/cbfs-mkstage.c | 4 ++-- util/cbfstool/elfheaders.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6aa3746..2a92c9f 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -132,8 +132,8 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, continue; if (input->size < (phdr[i].p_offset + phdr[i].p_filesz)){ ERROR("Underflow copying out the segment." - "File has %ld bytes left, segment end is %ld\n", - input->size, phdr[i].p_offset + phdr[i].p_filesz); + "File has %zu bytes left, segment end is %zu\n", + input->size, (size_t)(phdr[i].p_offset + phdr[i].p_filesz)); return -1; } memcpy(buffer + (l_start - data_start), diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index f3ed05c..816278f 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -147,7 +147,7 @@ check_size(const struct buffer *b, size_t offset, size_t size, const char *desc) if (offset >= buffer_size(b) || (offset + size) > buffer_size(b)) { ERROR("The file is not large enough for the '%s'. " - "%ld bytes @ offset %zu, input %zu bytes.\n", + "%zu bytes @ offset %zu, input %zu bytes.\n", desc, size, offset, buffer_size(b)); return -1; }

1 0

Patch merged into coreboot/master: a00ce09 mainboard/lenovo/x230 Fix usage of GNU field designator extension
by gerrit＠coreboot.org 17 Mar '14

17 Mar '14

the following patch was just integrated into master: commit a00ce09cd2890b191ecfbd7b0b0b2001e47b0d17 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 20:42:40 2014 +1100 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5392 for details. -gerrit

1 0

Patch merged into coreboot/master: 774c897 romcc.c: Fixes warning about unused function from unused macros.
by gerrit＠coreboot.org 17 Mar '14

17 Mar '14

the following patch was just integrated into master: commit 774c89762a1a3f48d1d9c2e07b6a2740e725b1b0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Feb 20 19:37:42 2014 +1100 romcc.c: Fixes warning about unused function from unused macros. GCC suppresses warnings about unused static functions if they are inline, however Clang only does this for header files. None of these MASK_ declarations are used, so just remove them. Change-Id: Ia230beba3f6367237838d9b3d90536459e1d52cb Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5273 for details. -gerrit

1 0

Patch set updated for coreboot: a00ce09 mainboard/lenovo/x230 Fix usage of GNU field designator extension
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5392 -gerrit commit a00ce09cd2890b191ecfbd7b0b0b2001e47b0d17 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 20:42:40 2014 +1100 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/x230/romstage.c | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 377c34a..6e4e685 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -121,34 +121,34 @@ void main(unsigned long bist) } struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xA0, 0x00,0xA2,0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 1, - gbe_enable: 1, - ddr3lv_support: 0, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + .ddr3lv_support = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { /* enabled usb oc pin length */ { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ @@ -165,7 +165,7 @@ void main(unsigned long bist) { 1, 0, 0x0040 }, /* P12: wlan, no OC */ { 1, 0, 0x0080 }, /* P13: webcam, no OC */ }, - ddr_refresh_rate_config: 2, /* Force double refresh rate */ + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ }; timestamp_init(get_initial_timestamp());

1 0

Patch set updated for coreboot: c2e731d Lenovo T530 [1/2]: create board by forking Lenovo X230.
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5390 -gerrit commit c2e731d111f35d0bedd0892ff2d13490672425be Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 17:09:58 2014 +1100 Lenovo T530 [1/2]: create board by forking Lenovo X230. Step 1: copy all files unmodified from Lenovo X230. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 83 ++++++ src/mainboard/lenovo/t530/Makefile.inc | 20 ++ src/mainboard/lenovo/t530/acpi/ec.asl | 26 ++ src/mainboard/lenovo/t530/acpi/gpe.asl | 13 + src/mainboard/lenovo/t530/acpi/mainboard.asl | 0 src/mainboard/lenovo/t530/acpi/platform.asl | 74 +++++ .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 65 +++++ src/mainboard/lenovo/t530/acpi/superio.asl | 1 + src/mainboard/lenovo/t530/acpi/video.asl | 115 ++++++++ src/mainboard/lenovo/t530/acpi_tables.c | 256 +++++++++++++++++ src/mainboard/lenovo/t530/board_info.txt | 6 + src/mainboard/lenovo/t530/cmos.default | 18 ++ src/mainboard/lenovo/t530/cmos.layout | 158 ++++++++++ src/mainboard/lenovo/t530/devicetree.cb | 147 ++++++++++ src/mainboard/lenovo/t530/dsdt.asl | 61 ++++ src/mainboard/lenovo/t530/fadt.c | 160 +++++++++++ src/mainboard/lenovo/t530/gpio.h | 306 ++++++++++++++++++++ src/mainboard/lenovo/t530/hda_verb.h | 317 +++++++++++++++++++++ src/mainboard/lenovo/t530/mainboard.c | 196 +++++++++++++ src/mainboard/lenovo/t530/romstage.c | 286 +++++++++++++++++++ src/mainboard/lenovo/t530/smi.h | 0 src/mainboard/lenovo/t530/smihandler.c | 175 ++++++++++++ src/mainboard/lenovo/t530/thermal.h | 30 ++ 23 files changed, 2513 insertions(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig new file mode 100644 index 0000000..cd1f761 --- /dev/null +++ b/src/mainboard/lenovo/t530/Kconfig @@ -0,0 +1,83 @@ +if BOARD_LENOVO_X230 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select GFXUMA + select EARLY_CBMEM_INIT + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config HAVE_MRC_CACHE + bool + default n + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/x230 + +config MAINBOARD_PART_NUMBER + string + default "2325TLU" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0106.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21fa + +config MAINBOARD_VENDOR + string + default "LENOVO" + +endif # BOARD_LENOVO_X230 diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc new file mode 100644 index 0000000..d514d4b --- /dev/null +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t530/acpi/gpe.asl b/src/mainboard/lenovo/t530/acpi/gpe.asl new file mode 100644 index 0000000..eb489d5 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/gpe.asl @@ -0,0 +1,13 @@ + Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP03.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP03.HPCS) + If (\_SB.PCI0.RP03.PDC) + { + Store (0x01, \_SB.PCI0.RP03.PDC) + Notify (\_SB.PCI0.RP03, 0x00) + } + } + } diff --git a/src/mainboard/lenovo/t530/acpi/mainboard.asl b/src/mainboard/lenovo/t530/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl new file mode 100644 index 0000000..73478ea --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Not implemented. */ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ba725ac --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl new file mode 100644 index 0000000..a2657f1 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -0,0 +1 @@ +#include "../../../../drivers/pc80/ps2_controller.asl" diff --git a/src/mainboard/lenovo/t530/acpi/video.asl b/src/mainboard/lenovo/t530/acpi/video.asl new file mode 100644 index 0000000..12a268b --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/video.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (c) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Scope (\_SB.PCI0.GFX0) +{ + Device (LCD0) + { + Name (_ADR, 0x0400) + Name (BRCT, 0) + + Name (BRIG, Package (0x12) + { + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (_BCL, 0, NotSerialized) + { + Store (1, BRCT) + Return (BRIG) + } + + Method (_BCM, 1, NotSerialized) + { + Store (ShiftLeft (Arg0, 4), ^^BCLV) + Store (0x80000000, ^^CR1) + Store (0x061a061a, ^^CR2) + } + Method (_BQC, 0, NotSerialized) + { + Store (^^BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) + } + + Method(BRID, 1, NotSerialized) + { + Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) + If (LEqual (Local0, Ones)) + { + Return (0x11) + } + Return (Local0) + } + + /* Using Notify is the right way. But Windows doesn't handle + it well. So use both method in a way to avoid double action. + */ + Method (DECB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x87) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 2)) + { + Decrement (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + Method (INCB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x86) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 0x11)) + { + Increment (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + } +} diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c new file mode 100644 index 0000000..6ee2df8 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -0,0 +1,256 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt new file mode 100644 index 0000000..da3ef07 --- /dev/null +++ b/src/mainboard/lenovo/t530/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +Board name: X230 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default new file mode 100644 index 0000000..137f482 --- /dev/null +++ b/src/mainboard/lenovo/t530/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both \ No newline at end of file diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout new file mode 100644 index 0000000..6f8822f --- /dev/null +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -0,0 +1,158 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading + +#425 559 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb new file mode 100644 index 0000000..a76de5f --- /dev/null +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -0,0 +1,147 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi8_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (expresscard) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl new file mode 100644 index 0000000..12f40f8 --- /dev/null +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define RP03_IS_EXPRESSCARD 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + #include "acpi/video.asl" + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/t530/fadt.c b/src/mainboard/lenovo/t530/fadt.c new file mode 100644 index 0000000..27e6303 --- /dev/null +++ b/src/mainboard/lenovo/t530/fadt.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 101; /* c2 not supported */ + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h new file mode 100644 index 0000000..f0a32a8 --- /dev/null +++ b/src/mainboard/lenovo/t530/gpio.h @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_GPIO_H +#define X230_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map x230_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/lenovo/t530/hda_verb.h b/src/mainboard/lenovo/t530/hda_verb.h new file mode 100644 index 0000000..a319c28 --- /dev/null +++ b/src/mainboard/lenovo/t530/hda_verb.h @@ -0,0 +1,317 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : IDT + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fa + * Revision ID : 0x100303 + */ + + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fa, // Subsystem ID + 0x0000007d, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + 0x001720FA, + 0x00172121, + 0x001722AA, + 0x00172317, + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + 0x00A71C20, + 0x00A71D10, + 0x00A71EA1, + 0x00A71F04, + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + 0x00B71C1F, + 0x00B71D10, + 0x00B71E21, + 0x00B71F04, + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + 0x00C71CF0, + 0x00C71D00, + 0x00C71EF0, + 0x00C71F40, + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + 0x00D71C10, + 0x00D71D01, + 0x00D71E17, + 0x00D71F90, + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + 0x00F71CF0, + 0x00F71D00, + 0x00F71EF0, + 0x00F71F40, + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + 0x01171C40, + 0x01171D01, + 0x01171EA3, + 0x01171FD5, + + 0x01271C40, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + + 0x01471C10, + 0x01471D01, + 0x01471E17, + 0x01471F90, + + 0x01571C20, + 0x01571D10, + 0x01571E21, + 0x01571F03, + + 0x01871C30, + 0x01871D18, + 0x01871EA1, + 0x01871F03, + + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + 0x00370600, + 0x00270600, + 0x00270600, + 0x00270600, + + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + + 0x01D71C05, + 0x01D71D82, + 0x01D71E13, + 0x01D71F40, + + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x30172001, + 0x30172101, + 0x30172286, + 0x30172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); + + diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c new file mode 100644 index 0000000..2e4bc4a --- /dev/null +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, X86_AX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0001; /* Int-LVDS */ + res = 1; + break; + case 0x5f70: + switch (X86_CH) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + X86_CH); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +const char *smbios_mainboard_version(void) +{ + return "ThinkPad X230"; +} + +/* Audio Setup */ + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; +extern const u32 *pc_beep_verbs; +extern u32 pc_beep_verbs_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + /* This sneaked in here, because X201 SuperIO chip isn't really + connected to anything and hence we don't init it. + */ + pc_keyboard_init(0); + + /* Enable expresscard hotplug events. */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0xd8, + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) + | (1 << 30)); + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0x42, 0x142); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +void h8_mainboard_init_dock (void); + +void h8_mainboard_init_dock (void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c new file mode 100644 index 0000000..6e4e685 --- /dev/null +++ b/src/mainboard/lenovo/t530/romstage.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include "gpio.h" +#include <cbfs.h> + +static void pch_enable_lpc(void) +{ + /* X230 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, + 0x80010000); +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17f81fe3; + RCBA32(BUC) = 0; +} + +void main(unsigned long bist) +{ + int boot_mode = 0; + int cbmem_was_initted; + u32 pm1_cnt; + u16 pm1_sts; + + if (MCHBAR16(SSKPD) == 0xCAFE) { + outb(0x6, 0xcf9); + hlt (); + } + + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + .ddr3lv_support = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* enabled usb oc pin length */ + { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ + { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ + { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ + { 1, 0, 0x0040 }, /* P3: wwan, no OC */ + { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 1, 0, 0x0080 }, /* P7: dock, no OC */ + { 0, 0, 0x0000 }, /* P8: Empty */ + { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ + { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ + { 1, 0, 0x0040 }, /* P12: wlan, no OC */ + { 1, 0, 0x0080 }, /* P13: webcam, no OC */ + }, + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&x230_gpio_map); + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x39); + + post_code(0x3a); + pei_data.boot_mode = boot_mode; + timestamp_add_now(TS_BEFORE_INITRAM); + + /* MRC.bin has a bug and sometimes halts (instead of reboot?). + */ + if (boot_mode != 2) + { + RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ + outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ + } + + sdram_initialize(&pei_data); + + if (boot_mode != 2) + { + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + } + + timestamp_add_now(TS_AFTER_INITRAM); + post_code(0x3c); + + rcba_config(); + post_code(0x3d); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); + if (boot_mode!=2) + save_mrc_data(&pei_data); + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + hlt(); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/t530/smi.h b/src/mainboard/lenovo/t530/smi.h new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c new file mode 100644 index 0000000..bbe08e2 --- /dev/null +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include "smi.h" +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h new file mode 100644 index 0000000..ab24bb1 --- /dev/null +++ b/src/mainboard/lenovo/t530/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_THERMAL_H +#define X230_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

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Patch set updated for coreboot: 9a1b5e4 Lenovo T530 [2/2]: actually implement mainboard support.
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5391 -gerrit commit 9a1b5e4eb867747637468ed9580ee1b965accd9b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 17:24:18 2014 +1100 Lenovo T530 [2/2]: actually implement mainboard support. Step 2: change the Lenovo X230 code to adapt it to the new board's hardware with the great guidance from Vladimir (phcoder) to find the correct GPIO's. The machine has: - Chipset: Intel QM77 - GPU's: Intel Integrated HD Graphics : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology and pci configuration of: -[0000:00]-+-00.0 8086:0154 +-02.0 8086:0166 +-16.0 8086:1e3a +-19.0 8086:1502 +-1a.0 8086:1e2d +-1b.0 8086:1e20 +-1c.0-[02]----00.0 1180:e823 +-1c.1-[03]----00.0 8086:4238 +-1c.2-[04-0b]-- +-1d.0 8086:1e26 +-1f.0 8086:1e55 +-1f.2 8086:1e03 \-1f.3 8086:1e22 Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/t530/Kconfig | 8 ++++---- src/mainboard/lenovo/t530/board_info.txt | 2 +- src/mainboard/lenovo/t530/devicetree.cb | 4 ++-- src/mainboard/lenovo/t530/gpio.h | 8 ++++---- src/mainboard/lenovo/t530/mainboard.c | 2 +- src/mainboard/lenovo/t530/romstage.c | 12 +++++++++++- src/mainboard/lenovo/t530/thermal.h | 6 +++--- 8 files changed, 32 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..9410e90 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X230 help Lenovo X230 laptop. Consult wiki for details. +config BOARD_LENOVO_T530 + bool "ThinkPad T530" + help + Lenovo T530 laptop. Consult wiki for details. + config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" help @@ -35,6 +40,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" +source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index cd1f761..701b2ed 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X230 +if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -34,11 +34,11 @@ config HAVE_ME_BIN config MAINBOARD_DIR string - default lenovo/x230 + default lenovo/t530 config MAINBOARD_PART_NUMBER string - default "2325TLU" + default "2359CTO" config MMCONF_BASE_ADDRESS hex @@ -80,4 +80,4 @@ config MAINBOARD_VENDOR string default "LENOVO" -endif # BOARD_LENOVO_X230 +endif # BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt index da3ef07..94829c1 100644 --- a/src/mainboard/lenovo/t530/board_info.txt +++ b/src/mainboard/lenovo/t530/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -Board name: X230 +Board name: T530 ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index a76de5f..6a09004 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -101,10 +101,10 @@ chip northbridge/intel/sandybridge io 0x66 = 0x1604 end - register "config0" = "0xa6" + register "config0" = "0xa7" register "config1" = "0x09" register "config2" = "0xa0" - register "config3" = "0xe0" + register "config3" = "0xc2" register "has_keyboard_backlight" = "1" diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index f0a32a8..70e4c09 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef X230_GPIO_H -#define X230_GPIO_H +#ifndef T530_GPIO_H +#define T530_GPIO_H #include "southbridge/intel/bd82x6x/gpio.h" @@ -284,7 +284,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_map x230_gpio_map = { +const struct pch_gpio_map t530_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, @@ -303,4 +303,4 @@ const struct pch_gpio_map x230_gpio_map = { .level = &pch_gpio_set3_level, }, }; -#endif +#endif /* T530_GPIO_H */ diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 2e4bc4a..5931d00 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -133,7 +133,7 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "ThinkPad X230"; + return "ThinkPad T530"; } /* Audio Setup */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 6e4e685..96b5205 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -180,7 +180,17 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&x230_gpio_map); +// setup_pch_gpios(&t530_gpio_map); + outl(0x3962a5ff, DEFAULT_GPIOBASE); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); + outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); + outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); + outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); + outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); + outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); + outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); + outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); /* Initialize console device(s) */ console_init(); diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index ab24bb1..2fafcde 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef T530_THERMAL_H +#define T530_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -27,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif +#endif /* T530_THERMAL_H */

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Patch set updated for coreboot: d503273 mainboard/lenovo/x230: Fix usage of GNU field designator extension.
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5392 -gerrit commit d5032736c5a09b5173f44c7b5196ee826002da04 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 20:42:40 2014 +1100 mainboard/lenovo/x230: Fix usage of GNU field designator extension. In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/x230/romstage.c | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 377c34a..6e4e685 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -121,34 +121,34 @@ void main(unsigned long bist) } struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xA0, 0x00,0xA2,0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 1, - gbe_enable: 1, - ddr3lv_support: 0, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + .ddr3lv_support = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { /* enabled usb oc pin length */ { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ @@ -165,7 +165,7 @@ void main(unsigned long bist) { 1, 0, 0x0040 }, /* P12: wlan, no OC */ { 1, 0, 0x0080 }, /* P13: webcam, no OC */ }, - ddr_refresh_rate_config: 2, /* Force double refresh rate */ + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ }; timestamp_init(get_initial_timestamp());

1 0

Patch set updated for coreboot: b20e50f Lenovo T530 [1/2]: create board by forking Lenovo X230.
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5390 -gerrit commit b20e50f37621f42c9c767a59b7fedd811d8460d6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 17:09:58 2014 +1100 Lenovo T530 [1/2]: create board by forking Lenovo X230. Step 1: copy all files unmodified from Lenovo X230. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 83 ++++++ src/mainboard/lenovo/t530/Makefile.inc | 20 ++ src/mainboard/lenovo/t530/acpi/ec.asl | 26 ++ src/mainboard/lenovo/t530/acpi/gpe.asl | 13 + src/mainboard/lenovo/t530/acpi/mainboard.asl | 0 src/mainboard/lenovo/t530/acpi/platform.asl | 74 +++++ .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 65 +++++ src/mainboard/lenovo/t530/acpi/superio.asl | 1 + src/mainboard/lenovo/t530/acpi/video.asl | 115 ++++++++ src/mainboard/lenovo/t530/acpi_tables.c | 256 +++++++++++++++++ src/mainboard/lenovo/t530/board_info.txt | 6 + src/mainboard/lenovo/t530/cmos.default | 18 ++ src/mainboard/lenovo/t530/cmos.layout | 158 ++++++++++ src/mainboard/lenovo/t530/devicetree.cb | 147 ++++++++++ src/mainboard/lenovo/t530/dsdt.asl | 61 ++++ src/mainboard/lenovo/t530/fadt.c | 160 +++++++++++ src/mainboard/lenovo/t530/gpio.h | 306 ++++++++++++++++++++ src/mainboard/lenovo/t530/hda_verb.h | 317 +++++++++++++++++++++ src/mainboard/lenovo/t530/mainboard.c | 196 +++++++++++++ src/mainboard/lenovo/t530/romstage.c | 286 +++++++++++++++++++ src/mainboard/lenovo/t530/smi.h | 0 src/mainboard/lenovo/t530/smihandler.c | 175 ++++++++++++ src/mainboard/lenovo/t530/thermal.h | 30 ++ 23 files changed, 2513 insertions(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig new file mode 100644 index 0000000..cd1f761 --- /dev/null +++ b/src/mainboard/lenovo/t530/Kconfig @@ -0,0 +1,83 @@ +if BOARD_LENOVO_X230 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select GFXUMA + select EARLY_CBMEM_INIT + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config HAVE_MRC_CACHE + bool + default n + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/x230 + +config MAINBOARD_PART_NUMBER + string + default "2325TLU" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0106.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21fa + +config MAINBOARD_VENDOR + string + default "LENOVO" + +endif # BOARD_LENOVO_X230 diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc new file mode 100644 index 0000000..d514d4b --- /dev/null +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t530/acpi/gpe.asl b/src/mainboard/lenovo/t530/acpi/gpe.asl new file mode 100644 index 0000000..eb489d5 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/gpe.asl @@ -0,0 +1,13 @@ + Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP03.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP03.HPCS) + If (\_SB.PCI0.RP03.PDC) + { + Store (0x01, \_SB.PCI0.RP03.PDC) + Notify (\_SB.PCI0.RP03, 0x00) + } + } + } diff --git a/src/mainboard/lenovo/t530/acpi/mainboard.asl b/src/mainboard/lenovo/t530/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl new file mode 100644 index 0000000..73478ea --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Not implemented. */ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ba725ac --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl new file mode 100644 index 0000000..a2657f1 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -0,0 +1 @@ +#include "../../../../drivers/pc80/ps2_controller.asl" diff --git a/src/mainboard/lenovo/t530/acpi/video.asl b/src/mainboard/lenovo/t530/acpi/video.asl new file mode 100644 index 0000000..12a268b --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/video.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (c) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Scope (\_SB.PCI0.GFX0) +{ + Device (LCD0) + { + Name (_ADR, 0x0400) + Name (BRCT, 0) + + Name (BRIG, Package (0x12) + { + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (_BCL, 0, NotSerialized) + { + Store (1, BRCT) + Return (BRIG) + } + + Method (_BCM, 1, NotSerialized) + { + Store (ShiftLeft (Arg0, 4), ^^BCLV) + Store (0x80000000, ^^CR1) + Store (0x061a061a, ^^CR2) + } + Method (_BQC, 0, NotSerialized) + { + Store (^^BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) + } + + Method(BRID, 1, NotSerialized) + { + Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) + If (LEqual (Local0, Ones)) + { + Return (0x11) + } + Return (Local0) + } + + /* Using Notify is the right way. But Windows doesn't handle + it well. So use both method in a way to avoid double action. + */ + Method (DECB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x87) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 2)) + { + Decrement (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + Method (INCB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x86) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 0x11)) + { + Increment (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + } +} diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c new file mode 100644 index 0000000..6ee2df8 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -0,0 +1,256 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt new file mode 100644 index 0000000..da3ef07 --- /dev/null +++ b/src/mainboard/lenovo/t530/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +Board name: X230 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default new file mode 100644 index 0000000..137f482 --- /dev/null +++ b/src/mainboard/lenovo/t530/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both \ No newline at end of file diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout new file mode 100644 index 0000000..6f8822f --- /dev/null +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -0,0 +1,158 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading + +#425 559 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb new file mode 100644 index 0000000..a76de5f --- /dev/null +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -0,0 +1,147 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi8_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (expresscard) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl new file mode 100644 index 0000000..12f40f8 --- /dev/null +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define RP03_IS_EXPRESSCARD 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + #include "acpi/video.asl" + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/t530/fadt.c b/src/mainboard/lenovo/t530/fadt.c new file mode 100644 index 0000000..27e6303 --- /dev/null +++ b/src/mainboard/lenovo/t530/fadt.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 101; /* c2 not supported */ + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h new file mode 100644 index 0000000..f0a32a8 --- /dev/null +++ b/src/mainboard/lenovo/t530/gpio.h @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_GPIO_H +#define X230_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map x230_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/lenovo/t530/hda_verb.h b/src/mainboard/lenovo/t530/hda_verb.h new file mode 100644 index 0000000..a319c28 --- /dev/null +++ b/src/mainboard/lenovo/t530/hda_verb.h @@ -0,0 +1,317 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : IDT + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fa + * Revision ID : 0x100303 + */ + + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fa, // Subsystem ID + 0x0000007d, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + 0x001720FA, + 0x00172121, + 0x001722AA, + 0x00172317, + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + 0x00A71C20, + 0x00A71D10, + 0x00A71EA1, + 0x00A71F04, + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + 0x00B71C1F, + 0x00B71D10, + 0x00B71E21, + 0x00B71F04, + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + 0x00C71CF0, + 0x00C71D00, + 0x00C71EF0, + 0x00C71F40, + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + 0x00D71C10, + 0x00D71D01, + 0x00D71E17, + 0x00D71F90, + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + 0x00F71CF0, + 0x00F71D00, + 0x00F71EF0, + 0x00F71F40, + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + 0x01171C40, + 0x01171D01, + 0x01171EA3, + 0x01171FD5, + + 0x01271C40, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + + 0x01471C10, + 0x01471D01, + 0x01471E17, + 0x01471F90, + + 0x01571C20, + 0x01571D10, + 0x01571E21, + 0x01571F03, + + 0x01871C30, + 0x01871D18, + 0x01871EA1, + 0x01871F03, + + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + 0x00370600, + 0x00270600, + 0x00270600, + 0x00270600, + + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + + 0x01D71C05, + 0x01D71D82, + 0x01D71E13, + 0x01D71F40, + + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x30172001, + 0x30172101, + 0x30172286, + 0x30172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); + + diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c new file mode 100644 index 0000000..2e4bc4a --- /dev/null +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, X86_AX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0001; /* Int-LVDS */ + res = 1; + break; + case 0x5f70: + switch (X86_CH) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + X86_CH); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +const char *smbios_mainboard_version(void) +{ + return "ThinkPad X230"; +} + +/* Audio Setup */ + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; +extern const u32 *pc_beep_verbs; +extern u32 pc_beep_verbs_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + /* This sneaked in here, because X201 SuperIO chip isn't really + connected to anything and hence we don't init it. + */ + pc_keyboard_init(0); + + /* Enable expresscard hotplug events. */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0xd8, + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) + | (1 << 30)); + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0x42, 0x142); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +void h8_mainboard_init_dock (void); + +void h8_mainboard_init_dock (void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c new file mode 100644 index 0000000..6e4e685 --- /dev/null +++ b/src/mainboard/lenovo/t530/romstage.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include "gpio.h" +#include <cbfs.h> + +static void pch_enable_lpc(void) +{ + /* X230 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, + 0x80010000); +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17f81fe3; + RCBA32(BUC) = 0; +} + +void main(unsigned long bist) +{ + int boot_mode = 0; + int cbmem_was_initted; + u32 pm1_cnt; + u16 pm1_sts; + + if (MCHBAR16(SSKPD) == 0xCAFE) { + outb(0x6, 0xcf9); + hlt (); + } + + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + .ddr3lv_support = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* enabled usb oc pin length */ + { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ + { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ + { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ + { 1, 0, 0x0040 }, /* P3: wwan, no OC */ + { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 1, 0, 0x0080 }, /* P7: dock, no OC */ + { 0, 0, 0x0000 }, /* P8: Empty */ + { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ + { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ + { 1, 0, 0x0040 }, /* P12: wlan, no OC */ + { 1, 0, 0x0080 }, /* P13: webcam, no OC */ + }, + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&x230_gpio_map); + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x39); + + post_code(0x3a); + pei_data.boot_mode = boot_mode; + timestamp_add_now(TS_BEFORE_INITRAM); + + /* MRC.bin has a bug and sometimes halts (instead of reboot?). + */ + if (boot_mode != 2) + { + RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ + outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ + } + + sdram_initialize(&pei_data); + + if (boot_mode != 2) + { + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + } + + timestamp_add_now(TS_AFTER_INITRAM); + post_code(0x3c); + + rcba_config(); + post_code(0x3d); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); + if (boot_mode!=2) + save_mrc_data(&pei_data); + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + hlt(); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/t530/smi.h b/src/mainboard/lenovo/t530/smi.h new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c new file mode 100644 index 0000000..bbe08e2 --- /dev/null +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include "smi.h" +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h new file mode 100644 index 0000000..ab24bb1 --- /dev/null +++ b/src/mainboard/lenovo/t530/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_THERMAL_H +#define X230_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

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Patch set updated for coreboot: d7505e9 Lenovo T530 [2/2]: actually implement mainboard support.
by Edward O'Callaghan 17 Mar '14

17 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5391 -gerrit commit d7505e9fac906af1703356e7c9e5a244a98d00bb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 16 17:24:18 2014 +1100 Lenovo T530 [2/2]: actually implement mainboard support. Step 2: change the Lenovo X230 code to adapt it to the new board's hardware with the great guidance from Vladimir (phcoder) to find the correct GPIO's. The machine has: - Chipset: Intel QM77 - GPU's: Intel Integrated HD Graphics : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology and pci configuration of: -[0000:00]-+-00.0 8086:0154 +-02.0 8086:0166 +-16.0 8086:1e3a +-19.0 8086:1502 +-1a.0 8086:1e2d +-1b.0 8086:1e20 +-1c.0-[02]----00.0 1180:e823 +-1c.1-[03]----00.0 8086:4238 +-1c.2-[04-0b]-- +-1d.0 8086:1e26 +-1f.0 8086:1e55 +-1f.2 8086:1e03 \-1f.3 8086:1e22 Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/t530/Kconfig | 8 ++++---- src/mainboard/lenovo/t530/board_info.txt | 2 +- src/mainboard/lenovo/t530/devicetree.cb | 4 ++-- src/mainboard/lenovo/t530/gpio.h | 8 ++++---- src/mainboard/lenovo/t530/mainboard.c | 2 +- src/mainboard/lenovo/t530/romstage.c | 12 +++++++++++- src/mainboard/lenovo/t530/thermal.h | 6 +++--- 8 files changed, 32 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..9410e90 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X230 help Lenovo X230 laptop. Consult wiki for details. +config BOARD_LENOVO_T530 + bool "ThinkPad T530" + help + Lenovo T530 laptop. Consult wiki for details. + config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" help @@ -35,6 +40,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" +source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index cd1f761..701b2ed 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X230 +if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -34,11 +34,11 @@ config HAVE_ME_BIN config MAINBOARD_DIR string - default lenovo/x230 + default lenovo/t530 config MAINBOARD_PART_NUMBER string - default "2325TLU" + default "2359CTO" config MMCONF_BASE_ADDRESS hex @@ -80,4 +80,4 @@ config MAINBOARD_VENDOR string default "LENOVO" -endif # BOARD_LENOVO_X230 +endif # BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt index da3ef07..94829c1 100644 --- a/src/mainboard/lenovo/t530/board_info.txt +++ b/src/mainboard/lenovo/t530/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -Board name: X230 +Board name: T530 ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index a76de5f..6a09004 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -101,10 +101,10 @@ chip northbridge/intel/sandybridge io 0x66 = 0x1604 end - register "config0" = "0xa6" + register "config0" = "0xa7" register "config1" = "0x09" register "config2" = "0xa0" - register "config3" = "0xe0" + register "config3" = "0xc2" register "has_keyboard_backlight" = "1" diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index f0a32a8..70e4c09 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef X230_GPIO_H -#define X230_GPIO_H +#ifndef T530_GPIO_H +#define T530_GPIO_H #include "southbridge/intel/bd82x6x/gpio.h" @@ -284,7 +284,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_map x230_gpio_map = { +const struct pch_gpio_map t530_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, @@ -303,4 +303,4 @@ const struct pch_gpio_map x230_gpio_map = { .level = &pch_gpio_set3_level, }, }; -#endif +#endif /* T530_GPIO_H */ diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 2e4bc4a..5931d00 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -133,7 +133,7 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "ThinkPad X230"; + return "ThinkPad T530"; } /* Audio Setup */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 6e4e685..96b5205 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -180,7 +180,17 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&x230_gpio_map); +// setup_pch_gpios(&t530_gpio_map); + outl(0x3962a5ff, DEFAULT_GPIOBASE); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); + outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); + outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); + outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); + outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); + outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); + outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); + outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); /* Initialize console device(s) */ console_init(); diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index ab24bb1..2fafcde 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef T530_THERMAL_H +#define T530_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -27,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif +#endif /* T530_THERMAL_H */

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coreboot-gerrit March 2014