coreboot-gerrit November 2014

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New patch to review for coreboot: 1d4ca80 Unify remaining binutils invocations
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7610 -gerrit commit 1d4ca8071b71c34c4336603dde3dd7e61b6ff28a Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 29 11:41:35 2014 +0100 Unify remaining binutils invocations No need to pass calls through gcc in one case and directly to binutils in another. Just always call binutils. Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/arm/Makefile.inc | 24 ++++-------------------- src/arch/arm64/Makefile.inc | 18 +++--------------- src/arch/x86/Makefile.inc | 10 +--------- src/cpu/x86/smm/Makefile.inc | 4 ---- 4 files changed, 8 insertions(+), 48 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 95e16b5..5698f38 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,11 +63,7 @@ bootblock-y += div0.c $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_bootblock) -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld -else - $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group -endif + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm/bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -88,11 +84,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld -else - $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group -endif + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(romstage-objs) --end-group -T $(src)/arch/arm/romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -115,18 +107,10 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld -else - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld -endif + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm/ramstage.ld $(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -else - $(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -Wl,--gc-sections -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) -Wl,--end-group -endif + $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 64370d4..5bf72b2 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -60,11 +60,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_bootblock) -nostdlib -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm64/bootblock.ld -else - $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm64/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group -endif + $(LD_bootblock) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -87,11 +83,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm64/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm64/romstage.ld -else - $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm64/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group -endif + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(romstage-objs) --end-group -T $(src)/arch/arm64/romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -128,10 +120,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm64/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld -else - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm64/ramstage.ld -endif + $(LD_ramstage) -nostdlib --gc-sections -o $@ --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e66752e..cc4ce8d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -130,11 +130,7 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld -else - $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< -endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 @@ -313,11 +309,7 @@ else $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld -else - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< -endif + $(LD_ramstage) -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld endif diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 7ed4e86..fc6f8f3 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -27,11 +27,7 @@ $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --start-group $(smm-objs) $(COMPILER_RT_smm) --end-group $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o -else - $(CC_smm) $(CFLAGS_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o -endif $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm

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New patch to review for coreboot: 5220082 gcc.c: Test for gcc, not for non-clang
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7609 -gerrit commit 5220082dd3371c42e7883bb76d4cac0ee182a359 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 29 11:32:12 2014 +0100 gcc.c: Test for gcc, not for non-clang This is gcc specific, not necessary-everywhere-but-on-clang. Change-Id: Ie02587bd41c856cbf730ea2f72f594a20b5fefbe Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/lib/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 55e0d6d..a31c22d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -38,7 +38,7 @@ romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c endif romstage-y += compute_ip_checksum.c -ifneq ($(CONFIG_COMPILER_LLVM_CLANG),y) +ifeq ($(CONFIG_COMPILER_GCC),y) romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif

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New patch to review for coreboot: f93151d Replace hlt with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7608 -gerrit commit f93151d1829fa1f6a9ae8de41a75dc29c984cda8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 29 10:38:17 2014 +0100 Replace hlt with halt() There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/arm/armv4/bootblock_simple.c | 4 ++-- src/arch/arm/armv7/bootblock_simple.c | 4 ++-- src/arch/arm64/armv8/bootblock_simple.c | 4 ++-- src/arch/x86/init/bootblock_normal.c | 3 ++- src/arch/x86/init/bootblock_simple.c | 3 ++- src/cpu/intel/haswell/bootblock.c | 9 +++------ src/cpu/intel/model_2065x/bootblock.c | 3 ++- src/cpu/intel/model_206ax/bootblock.c | 3 ++- src/ec/google/chromeec/ec.c | 6 +++--- src/mainboard/a-trend/atc-6220/romstage.c | 1 - src/mainboard/a-trend/atc-6240/romstage.c | 1 - src/mainboard/aaeon/pfm-540i_revb/romstage.c | 1 - src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/advantech/pcm-5820/romstage.c | 1 - src/mainboard/amd/db800/romstage.c | 1 - src/mainboard/amd/norwich/romstage.c | 1 - src/mainboard/amd/rumba/romstage.c | 1 - src/mainboard/apple/macbook21/romstage.c | 4 ++-- src/mainboard/artecgroup/dbe61/romstage.c | 1 - src/mainboard/asi/mb_5blgp/romstage.c | 1 - src/mainboard/asi/mb_5blmp/romstage.c | 1 - src/mainboard/asus/mew-am/romstage.c | 1 - src/mainboard/asus/mew-vm/romstage.c | 1 - src/mainboard/asus/p2b-d/romstage.c | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/axus/tc320/romstage.c | 1 - src/mainboard/azza/pt-6ibd/romstage.c | 1 - src/mainboard/bachmann/ot200/romstage.c | 1 - src/mainboard/bcom/winnet100/romstage.c | 1 - src/mainboard/bcom/winnetp680/romstage.c | 1 - src/mainboard/bifferos/bifferboard/romstage.c | 1 - src/mainboard/biostar/m6tba/romstage.c | 1 - src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 1 - src/mainboard/digitallogic/adl855pc/romstage.c | 1 - src/mainboard/digitallogic/msm586seg/romstage.c | 1 - src/mainboard/digitallogic/msm800sev/romstage.c | 1 - src/mainboard/eaglelion/5bcm/romstage.c | 1 - src/mainboard/ecs/p6iwp-fe/romstage.c | 1 - src/mainboard/emulation/qemu-i440fx/romstage.c | 1 - src/mainboard/emulation/qemu-q35/romstage.c | 1 - src/mainboard/getac/p470/romstage.c | 3 ++- src/mainboard/gigabyte/ga-6bxc/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxe/romstage.c | 1 - src/mainboard/hp/e_vectra_p2706t/romstage.c | 1 - src/mainboard/ibase/mb899/romstage.c | 3 ++- src/mainboard/iei/juki-511p/romstage.c | 1 - src/mainboard/iei/nova4899r/romstage.c | 1 - src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 1 - src/mainboard/iei/pm-lx-800-r11/romstage.c | 1 - src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 - src/mainboard/intel/d810e2cb/romstage.c | 1 - src/mainboard/jetway/j7f2/romstage.c | 1 - src/mainboard/kontron/986lcd-m/romstage.c | 3 ++- src/mainboard/lanner/em8510/romstage.c | 1 - src/mainboard/lenovo/t60/romstage.c | 3 ++- src/mainboard/lenovo/x60/romstage.c | 4 ++-- src/mainboard/lippert/frontrunner/romstage.c | 1 - src/mainboard/lippert/hurricane-lx/romstage.c | 1 - src/mainboard/lippert/literunner-lx/romstage.c | 1 - src/mainboard/lippert/roadrunner-lx/romstage.c | 1 - src/mainboard/lippert/spacerunner-lx/romstage.c | 1 - src/mainboard/mitac/6513wu/romstage.c | 1 - src/mainboard/msi/ms6119/romstage.c | 1 - src/mainboard/msi/ms6147/romstage.c | 1 - src/mainboard/msi/ms6156/romstage.c | 1 - src/mainboard/msi/ms6178/romstage.c | 1 - src/mainboard/nec/powermate2000/romstage.c | 1 - src/mainboard/nokia/ip530/romstage.c | 1 - src/mainboard/pcengines/alix1c/romstage.c | 1 - src/mainboard/pcengines/alix2d/romstage.c | 1 - src/mainboard/rca/rm4100/romstage.c | 1 - src/mainboard/roda/rk886ex/romstage.c | 3 ++- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 - src/mainboard/technologic/ts5300/romstage.c | 1 - src/mainboard/televideo/tc7020/romstage.c | 1 - src/mainboard/thomson/ip1000/romstage.c | 1 - src/mainboard/traverse/geos/romstage.c | 1 - src/mainboard/tyan/s1846/romstage.c | 1 - src/mainboard/via/epia-cn/romstage.c | 1 - src/mainboard/via/epia-m/romstage.c | 1 - src/mainboard/via/epia-m700/romstage.c | 1 - src/mainboard/via/epia-m850/romstage.c | 1 - src/mainboard/via/epia-n/romstage.c | 1 - src/mainboard/via/epia/romstage.c | 1 - src/mainboard/via/pc2500e/romstage.c | 1 - src/mainboard/via/vt8454c/romstage.c | 1 - src/mainboard/winent/pl6064/romstage.c | 1 - src/mainboard/wyse/s50/romstage.c | 1 - src/northbridge/intel/gm45/early_reset.c | 3 ++- src/northbridge/intel/i5000/raminit.c | 5 +++-- src/northbridge/intel/i945/early_init.c | 3 ++- src/northbridge/intel/i945/raminit.c | 5 +++-- src/northbridge/intel/nehalem/raminit.c | 20 ++++++-------------- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- src/northbridge/via/vx800/examples/romstage.c | 1 - src/soc/intel/baytrail/smihandler.c | 4 ++-- src/soc/intel/broadwell/bootblock/cpu.c | 9 +++------ src/soc/intel/broadwell/me.c | 1 - src/soc/intel/broadwell/romstage/raminit.c | 1 - src/soc/intel/broadwell/smihandler.c | 4 ++-- src/soc/intel/fsp_baytrail/smihandler.c | 4 ++-- src/soc/nvidia/tegra124/bootblock.c | 1 - src/soc/samsung/exynos5250/power.c | 4 ++-- src/soc/samsung/exynos5420/power.c | 4 ++-- src/southbridge/intel/bd82x6x/early_me.c | 4 ++-- src/southbridge/intel/bd82x6x/early_me_native.c | 6 +++--- src/southbridge/intel/bd82x6x/early_pch_native.c | 1 - src/southbridge/intel/bd82x6x/me.c | 4 ++-- src/southbridge/intel/bd82x6x/me_8.x.c | 4 ++-- src/southbridge/intel/bd82x6x/smihandler.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/early_me.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/me.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/reset.c | 1 - src/southbridge/intel/fsp_bd82x6x/smihandler.c | 4 ++-- src/southbridge/intel/fsp_rangeley/reset.c | 1 - src/southbridge/intel/i82801gx/smihandler.c | 4 ++-- src/southbridge/intel/ibexpeak/me.c | 1 - src/southbridge/intel/ibexpeak/smihandler.c | 4 ++-- src/southbridge/intel/lynxpoint/me_9.x.c | 4 ++-- src/southbridge/intel/lynxpoint/smihandler.c | 4 ++-- 125 files changed, 92 insertions(+), 177 deletions(-) diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c index 80401b3..207279b 100644 --- a/src/arch/arm/armv4/bootblock_simple.c +++ b/src/arch/arm/armv4/bootblock_simple.c @@ -20,11 +20,11 @@ */ #include <arch/exception.h> -#include <arch/hlt.h> #include <arch/stages.h> #include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> +#include <halt.h> void main(void) { @@ -42,5 +42,5 @@ void main(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); if (entry) stage_exit(entry); - hlt(); + halt(); } diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c index 248ea4e..aad63b6 100644 --- a/src/arch/arm/armv7/bootblock_simple.c +++ b/src/arch/arm/armv7/bootblock_simple.c @@ -21,11 +21,11 @@ #include <arch/cache.h> #include <arch/exception.h> -#include <arch/hlt.h> #include <arch/stages.h> #include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> +#include <halt.h> #include <smp/node.h> void main(void) @@ -44,5 +44,5 @@ void main(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); if (entry) stage_exit(entry); - hlt(); + halt(); } diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c index d8339d1..7948f2f 100644 --- a/src/arch/arm64/armv8/bootblock_simple.c +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -21,11 +21,11 @@ #include <bootblock_common.h> #include <arch/cache.h> -#include <arch/hlt.h> #include <arch/stages.h> #include <arch/exception.h> #include <cbfs.h> #include <console/console.h> +#include <halt.h> static int boot_cpu(void) { @@ -69,5 +69,5 @@ void main(void) printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry); if (entry) stage_exit(entry); - hlt(); + halt(); } diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index 218d456..bde2535 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -1,6 +1,7 @@ #include <smp/node.h> #include <bootblock_common.h> #include <pc80/mc146818rtc.h> +#include <halt.h> static const char *get_fallback(const char *stagelist) { while (*stagelist) stagelist++; @@ -47,5 +48,5 @@ static void main(unsigned long bist) if (entry) call(entry, bist); /* duh. we're stuck */ - asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); + halt(); } diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 179595a..adeecf7 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -1,5 +1,6 @@ #include <smp/node.h> #include <bootblock_common.h> +#include <halt.h> static void main(unsigned long bist) { @@ -18,5 +19,5 @@ static void main(unsigned long bist) unsigned long entry; entry = findstage(target1); if (entry) call(entry, bist); - asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); + halt(); } diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 4857f23..366c56b 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,6 +23,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <halt.h> #include <cpu/intel/microcode/microcode.c> #include "haswell.h" @@ -106,9 +107,7 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); - while (1) { - asm("hlt"); - } + halt(); } static void check_for_clean_reset(void) @@ -122,9 +121,7 @@ static void check_for_clean_reset(void) if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); - while (1) { - asm("hlt"); - } + halt(); } } diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index fa8e137..23fb02a 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -23,6 +23,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <halt.h> #include <cpu/intel/microcode/microcode.c> @@ -109,7 +110,7 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); - asm("hlt"); + halt(); } static void bootblock_cpu_init(void) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 49c4012..d6fa2e7 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -23,6 +23,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <halt.h> #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" @@ -110,7 +111,7 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); - asm("hlt"); + halt(); } static void bootblock_cpu_init(void) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 24f9693..e5a9e9a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -23,7 +23,7 @@ #include <bootmode.h> #include <arch/io.h> #include <delay.h> -#include <arch/hlt.h> +#include <halt.h> #include <reset.h> #include <elog.h> #include <stdlib.h> @@ -125,7 +125,7 @@ void google_chromeec_check_ec_image(int expected_type) google_chromeec_command(&cec_cmd); udelay(1000); hard_reset(); - hlt(); + halt(); } } @@ -447,7 +447,7 @@ void google_chromeec_init(void) google_chromeec_command(&cec_cmd); udelay(1000); hard_reset(); - hlt(); + halt(); } } diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 70bc5d8..16c9286 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 392f40f..8485285 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index c4bf462..a664e9e 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -26,7 +26,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 41a09da..63dfec6 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index a6b856e..77cb154 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3df26c6..63e9275 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 1b8a303..2c82937 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 2d43fff..248baa0 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 8d3fc67..39a8e46 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -35,6 +35,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -313,8 +314,7 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); - while (1) - asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 343351f..63f89f1 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 43c5cf7..ac76f34 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index 1fb3378..96e884d 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/early_serial.c" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 7a79e85..15d7791 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 04bbd86..d2d4186 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/smsc/lpc47b272/early_serial.c" diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index d41afc8..8307311 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 494a3f0..56992c5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 1b905e4..7cf0099 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 09b9a4e..fb90a68 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 70bc5d8..16c9286 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 78c7629..2655fc7 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 15362e3..158a45f 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/early_serial.c" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index b31be70..804e34c 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 849479c..7951a57 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -25,7 +25,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 15362e3..158a45f 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/early_serial.c" diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 898ad1a..170a909 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c index dd2553e..574e9a6 100644 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/cache.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 921aa52..a91318d 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 70f820a..feccfb7 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 093c60b..ce8ef13 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <lib.h> #include "drivers/pc80/udelay_io.c" diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index ab944a4..2cc0ab5 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 8bfe8e5..4df217f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 28ddcc5..f247610 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/nsc/pc97317/early_serial.c" diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 9d5f2cd..0ffcfa5 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 6c17645..c617a0a 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index dd86701..658051c 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index ccfb076..7b60ae5 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -292,7 +293,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index e0a248b..9e465dd 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 5d69510..369a23f 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index c34801e..baa1995 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> /* TODO: It's a PC87364 actually! */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 2a81921..38e8620 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -243,7 +244,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 1b8e952..a58407a 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977f/early_serial.c" #include "southbridge/amd/cs5530/enable_rom.c" diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 2b6caf3..a146d8e 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977tf/early_serial.c" #include "southbridge/amd/cs5530/enable_rom.c" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 9f42232..b11f5cb 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index ac68b1d..a8e860d 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <spd.h> #include <arch/io.h> -#include <arch/hlt.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index a83bf7e..04e7bd0 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -23,7 +23,6 @@ #include <stdlib.h> #include <spd.h> #include <arch/io.h> -#include <arch/hlt.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 8b74b17..a6958ee 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801bx/i82801bx.h" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a9c71c3..a66467b 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c89e6c..dc7da99 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -32,6 +32,7 @@ #include "option_table.h" #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" @@ -354,7 +355,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index c51ee35..c1a02f4 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <lib.h> #include <spd.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f0ebcbc..350c2de 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -35,6 +35,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -253,7 +254,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1310b33..4596a1a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -35,6 +35,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -253,8 +254,7 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); - while (1) - asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 81642a1..3be4eb3 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index d8e9cd9..416a8fb 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -26,7 +26,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6839332..8b48640 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index ef3f7d2..4d8a6fd 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -26,7 +26,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index f397e37..3c25c08 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index e29423e..2710082 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index be273f3..fb30e49 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index c3a7557..916f0e9 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index ff888bc..e8dbb02 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index ae78990..66a9c9b 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index d4a2d8f..6bbfc1a 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 5c87867..3c5511b 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 4f80550..f4bbc31 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 52c5310..1316d5e 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index af91bde..500416a 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include "drivers/pc80/udelay_io.c" #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 071fa2a..c9ec4f1 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -276,7 +277,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); - while (1) asm("hlt"); + halt(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 82ac56f..531e223 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 5d33bae..9cafc64 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 15362e3..158a45f 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/early_serial.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index bb8d15c..ede49f7 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include "drivers/pc80/udelay_io.c" #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index b3358b5..76e4a5c 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 0c81e8e..10af34d 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20f99cb..8a0d384 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "northbridge/via/cn700/raminit.h" diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 3f2a0c4..f63b6a8 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "northbridge/via/vt8623/raminit.h" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index b00ece1..c9b1e8b 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -30,7 +30,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "northbridge/via/vx800/vx800.h" diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 7b62d86..899c5a6 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 2ede8d8..0de7556 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1d312d7..5e20940 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "northbridge/via/vt8601/raminit.h" diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0b1aeb4..57e5cd0 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f6d58c8..bb2d878 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "northbridge/via/cx700/raminit.h" diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 47ea722..56b1329 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index b9de16c..6283c9c 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include <console/console.h> #include <lib.h> #include "cpu/x86/bist.h" diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index fccb97f..babb994 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -21,6 +21,7 @@ #include <types.h> #include <arch/io.h> +#include <halt.h> #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) @@ -69,5 +70,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Perform system reset through CF9 interface. */ outb(0x02, 0xcf9); /* Set system reset bit. */ outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ - while (1) asm("hlt"); + halt(); } diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 9c694c7..5394002 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -26,6 +26,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <console/console.h> +#include <halt.h> #include <spd.h> #include <types.h> #include <string.h> @@ -1522,7 +1523,7 @@ static void i5000_try_restart(const char *msg) printk(BIOS_INFO, "%s", msg); i5000_dump_error_registers(); outb(0x06, 0xcf9); - for(;;) asm volatile("hlt"); + halt(); } static void i5000_pam_setup(void) @@ -1624,7 +1625,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); /* FSB:FBD mapping changed, needs hard reset */ outb(0x06, 0xcf9); - for(;;) asm volatile("hlt"); + halt(); } return 0; } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f639aef..aaa17e5 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <cbmem.h> +#include <halt.h> #include <string.h> #include "i945.h" @@ -512,7 +513,7 @@ static void i945_setup_dmi_rcrb(void) reg32 |= (3 << 0); DMIBAR32(0x224) = reg32; outb(0x06, 0xcf9); - for (;;) asm("hlt"); /* wait for reset */ + halt(); /* wait for reset */ } } } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..e9b6e3f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -24,6 +24,7 @@ #include <spd.h> #include <string.h> #include <arch/io.h> +#include <halt.h> #include <lib.h> #include "raminit.h" #include "i945.h" @@ -281,7 +282,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Reset required.\n"); outb(0x00, 0xcf9); outb(0x0e, 0xcf9); - for (;;) asm("hlt"); /* Wait for reset! */ + halt(); /* Wait for reset! */ } } @@ -311,7 +312,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Reset required.\n"); outb(0x00, 0xcf9); outb(0x0e, 0xcf9); - for (;;) asm("hlt"); /* Wait for reset! */ + halt(); /* Wait for reset! */ } } diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 74ddb4b..fb82484 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <console/console.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -38,6 +37,7 @@ #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include <arch/cpu.h> +#include <halt.h> #include <spd.h> #include "raminit.h" #include <timestamp.h> @@ -3805,9 +3805,7 @@ void chipset_init(const int s3resume) write_mchbar8(0x2ca8, 0); outb(0x6, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4041,9 +4039,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) "Interrupted RAM init, reset required.\n"); outb(0x6, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #endif } } @@ -4407,9 +4403,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4); write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4510,9 +4504,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) outb(0xe, 0xcf9); #if REAL - while (1) { - asm volatile ("hlt"); - } + halt(); #else printf("CP5\n"); exit(0); @@ -4990,7 +4982,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) /* Failed S3 resume, reset to come up cleanly */ outb(0xe, 0xcf9); - hlt(); + halt(); } #endif } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index d2ae4b0..f6c92db 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> @@ -29,6 +28,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <halt.h> #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" @@ -239,7 +239,7 @@ void sdram_initialize(struct pei_data *pei_data) if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 2ab3e64..c96511e 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/hlt.h> #include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..62de9fa 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -19,13 +19,13 @@ #include <stdint.h> #include <stdlib.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> +#include <halt.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> @@ -161,7 +161,7 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 11f1833..da7b99d 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -23,6 +23,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <halt.h> #include <cpu/intel/microcode/microcode.c> #include <broadwell/rcba.h> #include <broadwell/msr.h> @@ -99,9 +100,7 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); - while (1) { - asm("hlt"); - } + halt(); } static void check_for_clean_reset(void) @@ -115,9 +114,7 @@ static void check_for_clean_reset(void) if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); - while (1) { - asm("hlt"); - } + halt(); } } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..2bdb1ed 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -26,7 +26,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index a5f688e..d4ebc08 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -18,7 +18,6 @@ */ #include <arch/cbfs.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..85a4f47 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -20,7 +20,6 @@ #include <delay.h> #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -28,6 +27,7 @@ #include <cpu/x86/smm.h> #include <spi-generic.h> #include <elog.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include <broadwell/lpc.h> #include <broadwell/nvs.h> @@ -197,7 +197,7 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* * In most sleep states, the code flow of this function ends at diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..234a34f 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -19,13 +19,13 @@ #include <stdint.h> #include <stdlib.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> +#include <halt.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> @@ -161,7 +161,7 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 22024af..6acd5ad 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/exception.h> -#include <arch/hlt.h> #include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index c9d620a..fb45dc0 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -20,8 +20,8 @@ /* Power setup code for EXYNOS5 */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #include "power.h" static void ps_hold_setup(void) @@ -45,7 +45,7 @@ void power_shutdown(void) clrbits_le32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); - hlt(); + halt(); } void power_enable_dp_phy(void) diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index ecaf208..a7e5262 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -20,8 +20,8 @@ /* Power setup code for EXYNOS5 */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #include "dmc.h" #include "power.h" #include "setup.h" @@ -47,7 +47,7 @@ void power_shutdown(void) clrbits_le32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); - hlt(); + halt(); } void power_enable_dp_phy(void) diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 670e1ce..eac0e34 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -194,7 +194,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - hlt(); + halt(); } return -1; } diff --git a/src/southbridge/intel/bd82x6x/early_me_native.c b/src/southbridge/intel/bd82x6x/early_me_native.c index f327aec..15e4087 100644 --- a/src/southbridge/intel/bd82x6x/early_me_native.c +++ b/src/southbridge/intel/bd82x6x/early_me_native.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -184,7 +184,7 @@ int intel_early_me_init_done(u8 status) pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); outb(0x6, 0xcf9); - hlt(); + halt(); } if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) { @@ -266,7 +266,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - hlt(); + halt(); } return -1; } diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 5cd6315..0863f34 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..901e71d 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -28,7 +28,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> @@ -36,6 +35,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> @@ -486,7 +486,7 @@ int mkhi_global_reset(void) /* Send request and wait for response */ if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { /* No response means reset will happen shortly... */ - hlt(); + halt(); } /* If the ME responded it rejected the reset request */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2dc83f7..e25b3b8 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,7 +28,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> @@ -36,6 +35,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> @@ -452,7 +452,7 @@ static int mkhi_global_reset(void) printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { /* No response means reset will happen shortly... */ - hlt(); + halt(); } /* If the ME responded it rejected the reset request */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f886ad4..1b8810f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -20,13 +20,13 @@ */ #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include "pch.h" @@ -474,7 +474,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake diff --git a/src/southbridge/intel/fsp_bd82x6x/early_me.c b/src/southbridge/intel/fsp_bd82x6x/early_me.c index 670e1ce..eac0e34 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_me.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -194,7 +194,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - hlt(); + halt(); } return -1; } diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..5326eb5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -29,7 +29,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> @@ -37,6 +36,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> #ifndef __SMM__ # include <device/device.h> @@ -485,7 +485,7 @@ int mkhi_global_reset(void) /* Send request and wait for response */ if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { /* No response means reset will happen shortly... */ - hlt(); + halt(); } /* If the ME responded it rejected the reset request */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 1c2ab34..d673ac7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -28,7 +28,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> @@ -36,6 +35,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> #ifndef __SMM__ # include <device/device.h> @@ -451,7 +451,7 @@ static int mkhi_global_reset(void) printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { /* No response means reset will happen shortly... */ - hlt(); + halt(); } /* If the ME responded it rejected the reset request */ diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c index fc09712..b5e67d8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ b/src/southbridge/intel/fsp_bd82x6x/reset.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <reset.h> void soft_reset(void) diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index b4fe557..493a98e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -20,13 +20,13 @@ */ #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include "pch.h" @@ -408,7 +408,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c index b6a0f3d..3123514 100644 --- a/src/southbridge/intel/fsp_rangeley/reset.c +++ b/src/southbridge/intel/fsp_rangeley/reset.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <reset.h> void soft_reset(void) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index cccfe15..4959c4d 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -20,12 +20,12 @@ */ #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include "i82801gx.h" @@ -348,7 +348,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..f94b17f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -28,7 +28,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index bc4ca22..b6ca523 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -20,13 +20,13 @@ */ #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include "pch.h" @@ -474,7 +474,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index c8ff913..dfed6de 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -28,7 +28,6 @@ */ #include <arch/acpi.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -38,6 +37,7 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> #include "me.h" #include "pch.h" @@ -563,7 +563,7 @@ static int mkhi_global_reset(void) printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { /* No response means reset will happen shortly... */ - hlt(); + halt(); } /* If the ME responded it rejected the reset request */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 00e4a83..627c64f 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -22,13 +22,13 @@ #include <delay.h> #include <types.h> -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <halt.h> #include <pc80/mc146818rtc.h> #include "pch.h" @@ -199,7 +199,7 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - hlt(); + halt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake

1 0

Patch set updated for coreboot: 2a3f71c Replace hlt() loops with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606 -gerrit commit 2a3f71cd40d23a42b487efa9582215575723bc5e Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:35:36 2014 +0100 Replace hlt() loops with halt() Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/console/die.c | 6 ++---- src/cpu/intel/haswell/romstage.c | 5 ++--- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ++---- src/include/cpu/x86/lapic.h | 6 ++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 6 ++---- src/mainboard/asus/a8v-e_se/romstage.c | 6 ++---- src/mainboard/asus/k8v-x/romstage.c | 6 ++---- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++---- src/mainboard/asus/m2v/romstage.c | 6 ++---- src/mainboard/dmp/vortex86ex/romstage.c | 4 ++-- src/mainboard/google/butterfly/romstage.c | 5 +++-- src/mainboard/google/link/romstage.c | 5 +++-- src/mainboard/google/parrot/romstage.c | 5 +++-- src/mainboard/google/stout/romstage.c | 5 +++-- src/mainboard/intel/cougar_canyon2/romstage.c | 5 ++--- src/mainboard/intel/emeraldlake2/romstage.c | 5 +++-- src/mainboard/kontron/ktqm77/romstage.c | 5 +++-- src/mainboard/samsung/lumpy/romstage.c | 5 +++-- src/mainboard/samsung/stumpy/romstage.c | 5 +++-- src/northbridge/intel/haswell/raminit.c | 6 ++---- src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------ src/northbridge/intel/sandybridge/romstage_native.c | 3 ++- src/soc/intel/baytrail/romstage/raminit.c | 4 ++-- src/soc/intel/broadwell/reset.c | 6 ++---- src/southbridge/intel/lynxpoint/early_me.c | 6 ++---- 25 files changed, 60 insertions(+), 77 deletions(-) diff --git a/src/console/die.c b/src/console/die.c index 395ab75..e6e968a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -20,8 +20,8 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #ifndef __ROMCC__ #define NORETURN __attribute__((noreturn)) @@ -33,7 +33,5 @@ void NORETURN die(const char *msg) { print_emerg(msg); - do { - hlt(); - } while(1); + halt(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2fdf..bd2513f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,6 +25,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <halt.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } /* The cache-as-ram assembly file calls romstage_main() after setting up diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 018924f..61b6bd7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -23,10 +23,10 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <delay.h> +#include <halt.h> #include <lib.h> #include <string.h> #include <console/console.h> -#include <arch/hlt.h> #include <device/device.h> #include <device/path.h> #include <smp/atomic.h> @@ -396,9 +396,7 @@ void stop_this_cpu(void) #endif } - while(1) { - hlt(); - } + halt(); } #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3d5046e..16bc42d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> -#include <arch/hlt.h> +#include <halt.h> #include <smp/node.h> /* See if I need to initialize the local apic */ @@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) static inline __attribute__((always_inline)) void stop_this_cpu(void) { /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + halt(); } #else void stop_this_cpu(void); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..0d55e53 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..3ed2491 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..dab3193 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -69,10 +70,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..42b03c8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -99,10 +100,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..f776351 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,10 +84,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index e7933d5..d43df8d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <halt.h> #include "drivers/pc80/i8254.c" #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" @@ -309,8 +310,7 @@ static void main(unsigned long bist) if (dmp_id != DMP_CPUID_EX) { /* Not DMP Vortex86EX CPU. */ post_code(POST_DMP_ID_ERR); - while (1) - hlt(); + halt(); } disable_watchdog(); set_ex_powerdown_control(); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 80c0742..6cf86ad 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -151,7 +152,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -193,7 +194,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index f90d7e7..f58ab13 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -40,6 +40,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -191,7 +192,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -241,7 +242,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index c25b419..69711d9 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -150,7 +151,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -192,7 +193,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6290e03..e8f2927 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #include <bootmode.h> #if CONFIG_CHROMEOS @@ -196,7 +197,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } @@ -246,7 +247,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9ac70ef..c90ece2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <halt.h> #include <reset.h> #include "superio/smsc/sio1007/chip.h" #include <fsp_util.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } static void pch_enable_lpc(void) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index d50093e..76edf7f 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -203,7 +204,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -249,7 +250,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index bfe7715..6926952 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -37,6 +37,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" static void pch_enable_lpc(void) @@ -190,7 +191,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -237,7 +238,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6595f0d..5b8646a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -40,6 +40,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "option_table.h" #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO @@ -180,7 +181,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -270,7 +271,7 @@ void main(unsigned long bist) if (boot_mode == 2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2c651ae..f842ad2 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -41,6 +41,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" @@ -218,7 +219,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -279,7 +280,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68..197dc0f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6..de6dac7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 902d66d..737cd63 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -29,6 +29,7 @@ #include "sandybridge.h" #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> +#include <halt.h> #include "raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" @@ -40,7 +41,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); - hlt (); + halt (); } timestamp_init(get_initial_timestamp()); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 72d8e51..a51853a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,13 +18,13 @@ */ #include <stddef.h> -#include <arch/hlt.h> #include <arch/io.h> #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <halt.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -38,7 +38,7 @@ static void reset_system(void) { warm_reset(); - while(1) { hlt(); } + halt(); } static void enable_smbus(void) diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index ffd15e7..5117b29 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> +#include <halt.h> #include <reset.h> #include <broadwell/reset.h> @@ -45,7 +45,5 @@ void hard_reset(void) void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..b57ca73 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - while (1) { - hlt(); - } + halt(); } return -1; }

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Patch set updated for coreboot: 1a8aac8 Replace hlt() loops with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606 -gerrit commit 1a8aac80481fae49876e5e05daccf12c1b569e59 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:35:36 2014 +0100 Replace hlt() loops with halt() Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/console/die.c | 6 ++---- src/cpu/intel/haswell/romstage.c | 5 ++--- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ++---- src/include/cpu/x86/lapic.h | 6 ++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 6 ++---- src/mainboard/asus/a8v-e_se/romstage.c | 6 ++---- src/mainboard/asus/k8v-x/romstage.c | 6 ++---- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++---- src/mainboard/asus/m2v/romstage.c | 6 ++---- src/mainboard/dmp/vortex86ex/romstage.c | 4 ++-- src/mainboard/google/butterfly/romstage.c | 5 +++-- src/mainboard/google/link/romstage.c | 5 +++-- src/mainboard/google/parrot/romstage.c | 5 +++-- src/mainboard/google/stout/romstage.c | 5 +++-- src/mainboard/intel/cougar_canyon2/romstage.c | 5 ++--- src/mainboard/intel/emeraldlake2/romstage.c | 5 +++-- src/mainboard/kontron/ktqm77/romstage.c | 5 +++-- src/northbridge/intel/haswell/raminit.c | 6 ++---- src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------ src/northbridge/intel/sandybridge/romstage_native.c | 3 ++- src/soc/intel/baytrail/romstage/raminit.c | 4 ++-- src/soc/intel/broadwell/reset.c | 6 ++---- src/southbridge/intel/lynxpoint/early_me.c | 6 ++---- 23 files changed, 54 insertions(+), 73 deletions(-) diff --git a/src/console/die.c b/src/console/die.c index 395ab75..e6e968a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -20,8 +20,8 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #ifndef __ROMCC__ #define NORETURN __attribute__((noreturn)) @@ -33,7 +33,5 @@ void NORETURN die(const char *msg) { print_emerg(msg); - do { - hlt(); - } while(1); + halt(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2fdf..bd2513f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,6 +25,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <halt.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } /* The cache-as-ram assembly file calls romstage_main() after setting up diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 018924f..61b6bd7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -23,10 +23,10 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <delay.h> +#include <halt.h> #include <lib.h> #include <string.h> #include <console/console.h> -#include <arch/hlt.h> #include <device/device.h> #include <device/path.h> #include <smp/atomic.h> @@ -396,9 +396,7 @@ void stop_this_cpu(void) #endif } - while(1) { - hlt(); - } + halt(); } #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3d5046e..16bc42d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> -#include <arch/hlt.h> +#include <halt.h> #include <smp/node.h> /* See if I need to initialize the local apic */ @@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) static inline __attribute__((always_inline)) void stop_this_cpu(void) { /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + halt(); } #else void stop_this_cpu(void); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..0d55e53 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..3ed2491 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..dab3193 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -69,10 +70,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..42b03c8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -99,10 +100,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..f776351 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,10 +84,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index e7933d5..d43df8d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <halt.h> #include "drivers/pc80/i8254.c" #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" @@ -309,8 +310,7 @@ static void main(unsigned long bist) if (dmp_id != DMP_CPUID_EX) { /* Not DMP Vortex86EX CPU. */ post_code(POST_DMP_ID_ERR); - while (1) - hlt(); + halt(); } disable_watchdog(); set_ex_powerdown_control(); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 80c0742..6cf86ad 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -151,7 +152,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -193,7 +194,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index f90d7e7..f58ab13 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -40,6 +40,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -191,7 +192,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -241,7 +242,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index c25b419..69711d9 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -150,7 +151,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -192,7 +193,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6290e03..e8f2927 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #include <bootmode.h> #if CONFIG_CHROMEOS @@ -196,7 +197,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } @@ -246,7 +247,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9ac70ef..c90ece2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <halt.h> #include <reset.h> #include "superio/smsc/sio1007/chip.h" #include <fsp_util.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } static void pch_enable_lpc(void) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index d50093e..76edf7f 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -38,6 +38,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> @@ -203,7 +204,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -249,7 +250,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index bfe7715..6926952 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -37,6 +37,7 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <halt.h> #include "gpio.h" static void pch_enable_lpc(void) @@ -190,7 +191,7 @@ void main(unsigned long bist) /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); - hlt(); + halt(); } /* Perform some early chipset initialization required @@ -237,7 +238,7 @@ void main(unsigned long bist) if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } northbridge_romstage_finalize(boot_mode==2); diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68..197dc0f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6..de6dac7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 902d66d..737cd63 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -29,6 +29,7 @@ #include "sandybridge.h" #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> +#include <halt.h> #include "raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" @@ -40,7 +41,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); - hlt (); + halt (); } timestamp_init(get_initial_timestamp()); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 72d8e51..a51853a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,13 +18,13 @@ */ #include <stddef.h> -#include <arch/hlt.h> #include <arch/io.h> #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <halt.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -38,7 +38,7 @@ static void reset_system(void) { warm_reset(); - while(1) { hlt(); } + halt(); } static void enable_smbus(void) diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index ffd15e7..5117b29 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> +#include <halt.h> #include <reset.h> #include <broadwell/reset.h> @@ -45,7 +45,5 @@ void hard_reset(void) void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..b57ca73 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - while (1) { - hlt(); - } + halt(); } return -1; }

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Patch set updated for coreboot: e4751af Replace hlt() loops with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606 -gerrit commit e4751afc96a1229b79dc5aea137e9429b4bf67a8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:35:36 2014 +0100 Replace hlt() loops with halt() Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/console/die.c | 6 ++---- src/cpu/intel/haswell/romstage.c | 5 ++--- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ++---- src/include/cpu/x86/lapic.h | 6 ++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 6 ++---- src/mainboard/asus/a8v-e_se/romstage.c | 6 ++---- src/mainboard/asus/k8v-x/romstage.c | 6 ++---- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++---- src/mainboard/asus/m2v/romstage.c | 6 ++---- src/mainboard/dmp/vortex86ex/romstage.c | 4 ++-- src/mainboard/intel/cougar_canyon2/romstage.c | 5 ++--- src/northbridge/intel/haswell/raminit.c | 6 ++---- src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------ src/soc/intel/baytrail/romstage/raminit.c | 4 ++-- src/soc/intel/broadwell/reset.c | 6 ++---- src/southbridge/intel/lynxpoint/early_me.c | 6 ++---- 16 files changed, 34 insertions(+), 60 deletions(-) diff --git a/src/console/die.c b/src/console/die.c index 395ab75..e6e968a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -20,8 +20,8 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #ifndef __ROMCC__ #define NORETURN __attribute__((noreturn)) @@ -33,7 +33,5 @@ void NORETURN die(const char *msg) { print_emerg(msg); - do { - hlt(); - } while(1); + halt(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2fdf..bd2513f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,6 +25,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <halt.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } /* The cache-as-ram assembly file calls romstage_main() after setting up diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 018924f..61b6bd7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -23,10 +23,10 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <delay.h> +#include <halt.h> #include <lib.h> #include <string.h> #include <console/console.h> -#include <arch/hlt.h> #include <device/device.h> #include <device/path.h> #include <smp/atomic.h> @@ -396,9 +396,7 @@ void stop_this_cpu(void) #endif } - while(1) { - hlt(); - } + halt(); } #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3d5046e..16bc42d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> -#include <arch/hlt.h> +#include <halt.h> #include <smp/node.h> /* See if I need to initialize the local apic */ @@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) static inline __attribute__((always_inline)) void stop_this_cpu(void) { /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + halt(); } #else void stop_this_cpu(void); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..0d55e53 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..3ed2491 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..dab3193 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -69,10 +70,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..42b03c8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -99,10 +100,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..f776351 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,10 +84,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index e7933d5..d43df8d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <halt.h> #include "drivers/pc80/i8254.c" #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" @@ -309,8 +310,7 @@ static void main(unsigned long bist) if (dmp_id != DMP_CPUID_EX) { /* Not DMP Vortex86EX CPU. */ post_code(POST_DMP_ID_ERR); - while (1) - hlt(); + halt(); } disable_watchdog(); set_ex_powerdown_control(); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9ac70ef..c90ece2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <halt.h> #include <reset.h> #include "superio/smsc/sio1007/chip.h" #include <fsp_util.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } static void pch_enable_lpc(void) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68..197dc0f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6..de6dac7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 72d8e51..a51853a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,13 +18,13 @@ */ #include <stddef.h> -#include <arch/hlt.h> #include <arch/io.h> #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <halt.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -38,7 +38,7 @@ static void reset_system(void) { warm_reset(); - while(1) { hlt(); } + halt(); } static void enable_smbus(void) diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index ffd15e7..5117b29 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> +#include <halt.h> #include <reset.h> #include <broadwell/reset.h> @@ -45,7 +45,5 @@ void hard_reset(void) void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..b57ca73 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - while (1) { - hlt(); - } + halt(); } return -1; }

1 0

Patch set updated for coreboot: 7b1cbcd Introduce halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7605 -gerrit commit 7b1cbcdb935d4a28460aa275673ce8b75d4701e9 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:00:22 2014 +0100 Introduce halt() It's a portable and generic way to halt the system. Useful when waiting for the platform to reset. Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/include/halt.h | 33 +++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 5 +++++ src/lib/halt.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/src/include/halt.h b/src/include/halt.h new file mode 100644 index 0000000..6b7d753 --- /dev/null +++ b/src/include/halt.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __HALT_H__ +#define __HALT_H__ + +#ifdef __ROMCC__ +#include <lib/halt.c> +#else +/** + * halt the system reliably + */ +void __attribute__((noreturn)) halt(void); +#endif /* __ROMCC__ */ +#endif /* __HALT_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 55e0d6d..9dccee6 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -104,6 +104,11 @@ $(obj)/lib/version.smm.o : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c +bootblock-y += halt.c +romstage-y += halt.c +ramstage-y += halt.c +smm-y += halt.c + ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c diff --git a/src/lib/halt.c b/src/lib/halt.c new file mode 100644 index 0000000..edd5f5e --- /dev/null +++ b/src/lib/halt.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <halt.h> + +void halt(void) { + while (1) { + hlt(); + } +}

1 0

Patch set updated for coreboot: 0d10affb Replace hlt() loops with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606 -gerrit commit 0d10affb15ffc910b221a8302b057bec8800845a Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:35:36 2014 +0100 Replace hlt() loops with halt() Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/console/die.c | 6 ++---- src/cpu/intel/haswell/romstage.c | 5 ++--- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ++---- src/include/cpu/x86/lapic.h | 6 ++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 6 ++---- src/mainboard/asus/a8v-e_se/romstage.c | 6 ++---- src/mainboard/asus/k8v-x/romstage.c | 6 ++---- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++---- src/mainboard/asus/m2v/romstage.c | 6 ++---- src/mainboard/dmp/vortex86ex/romstage.c | 4 ++-- src/mainboard/intel/cougar_canyon2/romstage.c | 5 ++--- src/northbridge/intel/haswell/raminit.c | 6 ++---- src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------ src/soc/intel/baytrail/romstage/raminit.c | 4 ++-- src/soc/intel/broadwell/reset.c | 6 ++---- src/southbridge/intel/lynxpoint/early_me.c | 6 ++---- 16 files changed, 34 insertions(+), 60 deletions(-) diff --git a/src/console/die.c b/src/console/die.c index 395ab75..e6e968a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -20,8 +20,8 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #ifndef __ROMCC__ #define NORETURN __attribute__((noreturn)) @@ -33,7 +33,5 @@ void NORETURN die(const char *msg) { print_emerg(msg); - do { - hlt(); - } while(1); + halt(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2fdf..bd2513f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,6 +25,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <halt.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } /* The cache-as-ram assembly file calls romstage_main() after setting up diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 018924f..61b6bd7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -23,10 +23,10 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <delay.h> +#include <halt.h> #include <lib.h> #include <string.h> #include <console/console.h> -#include <arch/hlt.h> #include <device/device.h> #include <device/path.h> #include <smp/atomic.h> @@ -396,9 +396,7 @@ void stop_this_cpu(void) #endif } - while(1) { - hlt(); - } + halt(); } #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3d5046e..16bc42d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> -#include <arch/hlt.h> +#include <halt.h> #include <smp/node.h> /* See if I need to initialize the local apic */ @@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) static inline __attribute__((always_inline)) void stop_this_cpu(void) { /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + halt(); } #else void stop_this_cpu(void); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..0d55e53 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..3ed2491 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..dab3193 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -69,10 +70,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..42b03c8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -99,10 +100,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..f776351 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,10 +84,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index e7933d5..d43df8d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <halt.h> #include "drivers/pc80/i8254.c" #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" @@ -309,8 +310,7 @@ static void main(unsigned long bist) if (dmp_id != DMP_CPUID_EX) { /* Not DMP Vortex86EX CPU. */ post_code(POST_DMP_ID_ERR); - while (1) - hlt(); + halt(); } disable_watchdog(); set_ex_powerdown_control(); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9ac70ef..c90ece2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <halt.h> #include <reset.h> #include "superio/smsc/sio1007/chip.h" #include <fsp_util.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } static void pch_enable_lpc(void) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68..197dc0f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6..de6dac7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 72d8e51..a51853a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,13 +18,13 @@ */ #include <stddef.h> -#include <arch/hlt.h> #include <arch/io.h> #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <halt.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -38,7 +38,7 @@ static void reset_system(void) { warm_reset(); - while(1) { hlt(); } + halt(); } static void enable_smbus(void) diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index ffd15e7..5117b29 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> +#include <halt.h> #include <reset.h> #include <broadwell/reset.h> @@ -45,7 +45,5 @@ void hard_reset(void) void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..b57ca73 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - while (1) { - hlt(); - } + halt(); } return -1; }

1 0

Patch set updated for coreboot: 442afdf Introduce halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7605 -gerrit commit 442afdf169655aed1e98f7a716a8360b17b5168c Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:00:22 2014 +0100 Introduce halt() It's a portable and generic way to halt the system. Useful when waiting for the platform to reset. Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/include/halt.h | 33 +++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 ++++ src/lib/halt.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/src/include/halt.h b/src/include/halt.h new file mode 100644 index 0000000..6b7d753 --- /dev/null +++ b/src/include/halt.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __HALT_H__ +#define __HALT_H__ + +#ifdef __ROMCC__ +#include <lib/halt.c> +#else +/** + * halt the system reliably + */ +void __attribute__((noreturn)) halt(void); +#endif /* __ROMCC__ */ +#endif /* __HALT_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 55e0d6d..6cb7f11 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -104,6 +104,10 @@ $(obj)/lib/version.smm.o : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c +bootblock-y += halt.c +romstage-y += halt.c +ramstage-y += halt.c + ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c diff --git a/src/lib/halt.c b/src/lib/halt.c new file mode 100644 index 0000000..edd5f5e --- /dev/null +++ b/src/lib/halt.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <halt.h> + +void halt(void) { + while (1) { + hlt(); + } +}

1 0

Patch set updated for coreboot: 6813261 Replace hlt() loops with halt()
by Patrick Georgi 29 Nov '14

29 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606 -gerrit commit 6813261f302655f8b33f9fc9a178ad717d41bb68 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 28 22:35:36 2014 +0100 Replace hlt() loops with halt() Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/console/die.c | 6 ++---- src/cpu/intel/haswell/romstage.c | 5 ++--- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ++---- src/include/cpu/x86/lapic.h | 6 ++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 6 ++---- src/mainboard/asus/a8v-e_se/romstage.c | 6 ++---- src/mainboard/asus/k8v-x/romstage.c | 6 ++---- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++---- src/mainboard/asus/m2v/romstage.c | 6 ++---- src/mainboard/dmp/vortex86ex/romstage.c | 4 ++-- src/mainboard/intel/cougar_canyon2/romstage.c | 5 ++--- src/northbridge/intel/haswell/raminit.c | 6 ++---- src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------ src/soc/intel/baytrail/romstage/raminit.c | 4 ++-- src/soc/intel/broadwell/reset.c | 6 ++---- src/southbridge/intel/lynxpoint/early_me.c | 6 ++---- 16 files changed, 34 insertions(+), 60 deletions(-) diff --git a/src/console/die.c b/src/console/die.c index 395ab75..e6e968a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -20,8 +20,8 @@ */ #include <arch/io.h> -#include <arch/hlt.h> #include <console/console.h> +#include <halt.h> #ifndef __ROMCC__ #define NORETURN __attribute__((noreturn)) @@ -33,7 +33,5 @@ void NORETURN die(const char *msg) { print_emerg(msg); - do { - hlt(); - } while(1); + halt(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2fdf..bd2513f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,6 +25,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <halt.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } /* The cache-as-ram assembly file calls romstage_main() after setting up diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 018924f..61b6bd7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -23,10 +23,10 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <delay.h> +#include <halt.h> #include <lib.h> #include <string.h> #include <console/console.h> -#include <arch/hlt.h> #include <device/device.h> #include <device/path.h> #include <smp/atomic.h> @@ -396,9 +396,7 @@ void stop_this_cpu(void) #endif } - while(1) { - hlt(); - } + halt(); } #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3d5046e..16bc42d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> -#include <arch/hlt.h> +#include <halt.h> #include <smp/node.h> /* See if I need to initialize the local apic */ @@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) static inline __attribute__((always_inline)) void stop_this_cpu(void) { /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + halt(); } #else void stop_this_cpu(void); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..0d55e53 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..3ed2491 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -71,10 +72,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..dab3193 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "cpu/x86/lapic.h" @@ -69,10 +70,7 @@ void soft_reset(void) tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } #include "southbridge/via/k8t890/early_car.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..42b03c8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -99,10 +100,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..f776351 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <halt.h> #include "northbridge/amd/amdk8/raminit.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,10 +84,7 @@ void soft_reset(void) /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); - while (1) { - /* daisy daisy ... */ - hlt(); - } + halt(); } unsigned int get_sbdn(unsigned bus) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index e7933d5..d43df8d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <halt.h> #include "drivers/pc80/i8254.c" #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" @@ -309,8 +310,7 @@ static void main(unsigned long bist) if (dmp_id != DMP_CPUID_EX) { /* Not DMP Vortex86EX CPU. */ post_code(POST_DMP_ID_ERR); - while (1) - hlt(); + halt(); } disable_watchdog(); set_ex_powerdown_control(); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9ac70ef..c90ece2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <halt.h> #include <reset.h> #include "superio/smsc/sio1007/chip.h" #include <fsp_util.h> @@ -49,9 +50,7 @@ static inline void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } static void pch_enable_lpc(void) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68..197dc0f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6..de6dac7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 72d8e51..a51853a 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,13 +18,13 @@ */ #include <stddef.h> -#include <arch/hlt.h> #include <arch/io.h> #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <halt.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -38,7 +38,7 @@ static void reset_system(void) { warm_reset(); - while(1) { hlt(); } + halt(); } static void enable_smbus(void) diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index ffd15e7..5117b29 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> +#include <halt.h> #include <reset.h> #include <broadwell/reset.h> @@ -45,7 +45,5 @@ void hard_reset(void) void reset_system(void) { hard_reset(); - while (1) { - hlt(); - } + halt(); } diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..b57ca73 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ -#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> +#include <halt.h> #include <string.h> #include "me.h" #include "pch.h" @@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - while (1) { - hlt(); - } + halt(); } return -1; }

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coreboot-gerrit November 2014