Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4808
-gerrit
commit 4f1bd3df63b94dacde38552ca6a1cfb53e5978ad
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jan 25 16:38:43 2014 +0100
src/console/Kconfig: Use 128 KB CBMEM console buffer for higher log levels
With console log level BIOS_SPEW and debug level set in the payload
like SeaBIOS the CBMEM console buffer is too small and some lines
from the payload console are lost.
Therefore double the buffer size if the log level is BIOS_DEBUG or
BIOS_SPEW.
Kconfig seems to take the first `default` statement that matches, so
the line with the if statement has to be specified first to become
effective.
Change-Id: I464fb846515c2bc17cf7eea1d138f1808489b4e6
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/console/Kconfig | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 40903c1..74067fd 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -297,10 +297,12 @@ config CONSOLE_CBMEM_BUFFER_SIZE
depends on CONSOLE_CBMEM
hex "Room allocated for console output in CBMEM"
default 0x10000
+ default 0x20000 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
help
- Space allocated for console output storage in CBMEM. The default
- value (64K or 0x10000 bytes) is large enough to accommodate
- even the BIOS_SPEW level.
+ Space allocated for console output storage in CBMEM.
+
+ The default value is 64K or 0x10000 bytes and for console log
+ level BIOS_DEBUG or BIOS_SPEW it is 128K or 0x20000 bytes.
config CONSOLE_CAR_BUFFER_SIZE
depends on CONSOLE_CBMEM
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4805
-gerrit
commit 658ec620fc2d8d87a18afd3b7e958c6474b0e4c0
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jan 25 15:55:28 2014 +0100
src/cpu: Fix spelling of MTTR to MTRR
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/cpu/intel/haswell/cache_as_ram.inc | 12 ++++++------
src/cpu/intel/haswell/haswell.h | 16 ++++++++--------
src/cpu/intel/haswell/romstage.c | 20 ++++++++++----------
src/cpu/x86/mtrr/earlymtrr.c | 2 +-
src/cpu/x86/mtrr/mtrr.c | 6 +++---
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 2d1e86f..36d5654 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -185,7 +185,7 @@ before_romstage:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
- * for setting up MTTRs. */
+ * for setting up MTRRs. */
movl %eax, %ebx
post_code(0x2f)
@@ -249,23 +249,23 @@ before_romstage:
/* Setup stack as indicated by return value from ramstage_main(). */
movl %ebx, %esp
- /* Get number of MTTRs. */
+ /* Get number of MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
1:
testl %ebx, %ebx
jz 1f
- /* Low 32 bits of MTTR base. */
+ /* Low 32 bits of MTRR base. */
popl %eax
- /* Upper 32 bits of MTTR base. */
+ /* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
inc %ecx
- /* Low 32 bits of MTTR mask. */
+ /* Low 32 bits of MTRR mask. */
popl %eax
- /* Upper 32 bits of MTTR mask. */
+ /* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 9ed00af..dcd5dc7 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -175,14 +175,14 @@ void romstage_common(const struct romstage_params *params);
* torn down. The following values are pushed onto the stack to setup the
* MTRRs:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
* ...
*/
void * asmlinkage romstage_main(unsigned long bist);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index edb2e80..40a396d 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -108,18 +108,18 @@ static void *setup_romstage_stack_after_car(void)
* of physical address bits. */
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- /* The order for each MTTR is value then base with upper 32-bits of
+ /* The order for each MTRR is value then base with upper 32-bits of
* each value coming before the lower 32-bits. The reasoning for
* this ordering is to create a stack layout like the following:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
*/
/* Cache the ROM as WP just below 4GiB. */
@@ -158,7 +158,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Save the number of MTTRs to setup. Return the stack location
+ /* Save the number of MTRRs to setup. Return the stack location
* pointing to the number of MTRRs. */
slot = stack_push(slot, num_mtrrs);
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 36f94cd..0471a9e 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -30,7 +30,7 @@ static void cache_ramstage(void)
const int addr_det = 0;
-/* the fixed and variable MTTRs are power-up with random values,
+/* the fixed and variable MTRRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safety.
*/
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index dd404a8..dbedf0f 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -454,7 +454,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state,
if (var_state->mtrr_index >= bios_mtrrs)
printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
if (var_state->mtrr_index >= total_mtrrs) {
- printk(BIOS_ERR, "ERROR: Not enough MTTRs available!\n");
+ printk(BIOS_ERR, "ERROR: Not enough MTRRs available!\n");
return;
}
@@ -670,7 +670,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
struct var_mtrr_state var_state;
/* The default MTRR cacheability type is determined by calculating
- * the number of MTTRs required for each MTTR type as if it was the
+ * the number of MTRRs required for each MTRR type as if it was the
* default. */
var_state.addr_space = addr_space;
var_state.above4gb = above4gb;
@@ -776,7 +776,7 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type,
calc_var_mtrrs_without_hole(&var_state, r);
}
- /* Clear all remaining variable MTTRs. */
+ /* Clear all remaining variable MTRRs. */
for (i = var_state.mtrr_index; i < total_mtrrs; i++)
clear_var_mtrr(i);
}
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4807
-gerrit
commit 30610d75b1f01c314229e815920d7d49f1df88e6
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Jan 25 09:40:54 2014 -0600
fintek/f81865f: Deprecate the C inclusion of early_serial.c
Including "early_serial.c" directly in romstage.c rather than
compiling and linking it is a remnant of ROMCC. Modernize this by
declaring "early_serial.c" as a Makefile.inc object, and no longer
use it by direct inclusion.
Change-Id: I40a6646fedaad5371983bfc6e6e990c4932ec9bd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/amd/persimmon/romstage.c | 2 +-
src/mainboard/amd/south_station/romstage.c | 2 +-
src/mainboard/via/epia-m850/Makefile.inc | 22 +----------
src/mainboard/via/epia-m850/romstage.c | 4 +-
src/superio/fintek/f81865f/Makefile.inc | 1 +
src/superio/fintek/f81865f/early_serial.c | 48 +++++++++++++++++++++++
src/superio/fintek/f81865f/f81865f.h | 2 +
src/superio/fintek/f81865f/f81865f_early_serial.c | 47 ----------------------
8 files changed, 56 insertions(+), 72 deletions(-)
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 98c64ed..e082f60 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -31,7 +31,7 @@
#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include <superio/fintek/f81865f/f81865f.h>
#include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 20c973c..5614f88 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -32,7 +32,7 @@
#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include <superio/fintek/f81865f/f81865f.h>
#include "cpu/x86/lapic.h"
#include <sb_cimx.h>
#include "SBPLATFORM.h"
diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc
index 9c6d31f..e9a0b69 100644
--- a/src/mainboard/via/epia-m850/Makefile.inc
+++ b/src/mainboard/via/epia-m850/Makefile.inc
@@ -1,21 +1 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
-##
-## This program is free software: you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation, either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program. If not, see <http://www.gnu.org/licenses/>.
-##
-
-#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c
-
+# Nothing interesting here yet
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 262bee7..1114cf4 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -33,11 +33,11 @@
#include <string.h>
#include <timestamp.h>
#include <console/cbmem_console.h>
+#include <superio/fintek/f81865f/f81865f.h>
#include "northbridge/via/vx900/early_vx900.h"
#include "northbridge/via/vx900/raminit.h"
-/* FIXME: This is the only .c include we couldn't get rid of */
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+
#define SERIAL_DEV PNP_DEV(0x4e, 0x10)
diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc
index 1700f7c..8afb286 100644
--- a/src/superio/fintek/f81865f/Makefile.inc
+++ b/src/superio/fintek/f81865f/Makefile.inc
@@ -18,4 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c
diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c
new file mode 100644
index 0000000..29b5f9d
--- /dev/null
+++ b/src/superio/fintek/f81865f/early_serial.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include "f81865f.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+void f81865f_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h
index 0c36571..7269b59 100644
--- a/src/superio/fintek/f81865f/f81865f.h
+++ b/src/superio/fintek/f81865f/f81865f.h
@@ -35,4 +35,6 @@
#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */
#define F81865F_PME 0x0a /* Power Management Events (PME) */
+void f81865f_enable_serial(device_t dev, u16 iobase);
+
#endif
diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c
deleted file mode 100644
index 2989b5f..0000000
--- a/src/superio/fintek/f81865f/f81865f_early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */
-
-#include <arch/io.h>
-#include "f81865f.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f81865f_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4805
-gerrit
commit 1b9ca1a3848f2be768007b0bb9560b426bdb4637
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jan 25 15:55:28 2014 +0100
src/cpu: Fix typo MTTR to MTRR
It is *M*emory *T*ype *R*ange *R*egister.
$ git grep -l MTTR src/cpu/{intel,x86}/ | xargs sed -i 's/MTTR/MTRR/g'
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/cpu/intel/haswell/cache_as_ram.inc | 12 ++++++------
src/cpu/intel/haswell/haswell.h | 16 ++++++++--------
src/cpu/intel/haswell/romstage.c | 20 ++++++++++----------
src/cpu/x86/mtrr/earlymtrr.c | 2 +-
src/cpu/x86/mtrr/mtrr.c | 6 +++---
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 2d1e86f..36d5654 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -185,7 +185,7 @@ before_romstage:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
- * for setting up MTTRs. */
+ * for setting up MTRRs. */
movl %eax, %ebx
post_code(0x2f)
@@ -249,23 +249,23 @@ before_romstage:
/* Setup stack as indicated by return value from ramstage_main(). */
movl %ebx, %esp
- /* Get number of MTTRs. */
+ /* Get number of MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
1:
testl %ebx, %ebx
jz 1f
- /* Low 32 bits of MTTR base. */
+ /* Low 32 bits of MTRR base. */
popl %eax
- /* Upper 32 bits of MTTR base. */
+ /* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
inc %ecx
- /* Low 32 bits of MTTR mask. */
+ /* Low 32 bits of MTRR mask. */
popl %eax
- /* Upper 32 bits of MTTR mask. */
+ /* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 9ed00af..dcd5dc7 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -175,14 +175,14 @@ void romstage_common(const struct romstage_params *params);
* torn down. The following values are pushed onto the stack to setup the
* MTRRs:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
* ...
*/
void * asmlinkage romstage_main(unsigned long bist);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index edb2e80..40a396d 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -108,18 +108,18 @@ static void *setup_romstage_stack_after_car(void)
* of physical address bits. */
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- /* The order for each MTTR is value then base with upper 32-bits of
+ /* The order for each MTRR is value then base with upper 32-bits of
* each value coming before the lower 32-bits. The reasoning for
* this ordering is to create a stack layout like the following:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
*/
/* Cache the ROM as WP just below 4GiB. */
@@ -158,7 +158,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Save the number of MTTRs to setup. Return the stack location
+ /* Save the number of MTRRs to setup. Return the stack location
* pointing to the number of MTRRs. */
slot = stack_push(slot, num_mtrrs);
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 36f94cd..0471a9e 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -30,7 +30,7 @@ static void cache_ramstage(void)
const int addr_det = 0;
-/* the fixed and variable MTTRs are power-up with random values,
+/* the fixed and variable MTRRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safety.
*/
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index dd404a8..dbedf0f 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -454,7 +454,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state,
if (var_state->mtrr_index >= bios_mtrrs)
printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
if (var_state->mtrr_index >= total_mtrrs) {
- printk(BIOS_ERR, "ERROR: Not enough MTTRs available!\n");
+ printk(BIOS_ERR, "ERROR: Not enough MTRRs available!\n");
return;
}
@@ -670,7 +670,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
struct var_mtrr_state var_state;
/* The default MTRR cacheability type is determined by calculating
- * the number of MTTRs required for each MTTR type as if it was the
+ * the number of MTRRs required for each MTRR type as if it was the
* default. */
var_state.addr_space = addr_space;
var_state.above4gb = above4gb;
@@ -776,7 +776,7 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type,
calc_var_mtrrs_without_hole(&var_state, r);
}
- /* Clear all remaining variable MTTRs. */
+ /* Clear all remaining variable MTRRs. */
for (i = var_state.mtrr_index; i < total_mtrrs; i++)
clear_var_mtrr(i);
}
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4803
-gerrit
commit 076843076b9d6fd2e8c3869d8515c6442f8230d5
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 14:26:46 2014 +0100
lenovo/x60: Provide missing default for touchpad
Change-Id: Ib162151c61e77745995ff543c2eb4f8d5e6f5d40
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x60/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 0185e94..8cb3b96 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -8,6 +8,7 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
+touchpad=Enable
volume=0x3
tft_brightness=0xff
first_battery=Primary
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4794
-gerrit
commit 81d32962a2b0735704256b76ffc899ede7aa287b
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 04:03:35 2014 +0100
lenovo/x60: Move non-raminit config to checksummed area
Some non-raminit config was erroneously put to non-checksummed
non-restored area. Put it to right place.
Change-Id: If907bd771a37cb7b7310e3a8533e409b8c42b4fe
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x60/cmos.layout | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index c0cb680..0d6060f 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -93,10 +93,24 @@ entries
# coreboot config options: bootloader
416 512 s 0 boot_devices
-928 8 h 0 boot_default
-936 1 e 8 cmos_defaults_loaded
-937 1 e 1 lpt
-#938 46 r 0 unused
+928 8 h 0 boot_default
+936 1 e 8 cmos_defaults_loaded
+937 1 e 1 lpt
+938 1 e 9 first_battery
+939 1 e 1 bluetooth
+940 1 e 1 wwan
+941 1 e 1 wlan
+942 1 e 1 trackpoint
+943 1 e 1 fn_ctrl_swap
+
+944 8 h 0 volume
+952 8 h 0 tft_brightness
+960 1 e 1 power_management_beeps
+961 1 e 1 low_battery_beep
+962 1 e 1 sticky_fn
+963 1 e 1 touchpad
+
+#964 20 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -109,17 +123,6 @@ entries
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
-1064 8 h 0 volume
-1072 8 h 0 tft_brightness
-1080 1 e 9 first_battery
-1081 1 e 1 bluetooth
-1082 1 e 1 wwan
-1083 1 e 1 wlan
-1084 1 e 1 trackpoint
-1085 1 e 1 fn_ctrl_swap
-1086 1 e 1 sticky_fn
-1087 1 e 1 power_management_beeps
-1088 1 e 1 low_battery_beep
# -----------------------------------------------------------------
enumerations