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New patch to review for coreboot: d04fa86 Jetway NF81-T56N-LF: Bump size of ROM found on board.
by Edward O'Callaghan
26 Jan '14
26 Jan '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4811
-gerrit commit d04fa865d740066dc2e386894263041468715688 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 26 11:45:30 2014 +1100 Jetway NF81-T56N-LF: Bump size of ROM found on board. Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/platform_cfg.h | 8 ++++++-- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 0578e27..25ebb21 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -26,11 +26,13 @@ * @def BIOS_SIZE_2M * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M + * @def BIOS_SIZE_16M */ #define BIOS_SIZE_1M 0 #define BIOS_SIZE_2M 1 #define BIOS_SIZE_4M 3 #define BIOS_SIZE_8M 7 +#define BIOS_SIZE_16M 15 /* In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -45,8 +47,10 @@ #define BIOS_SIZE BIOS_SIZE_4M #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 #define BIOS_SIZE BIOS_SIZE_8M +#elif CONFIG_COREBOOT_ROMSIZE_KB_16484 == 1 + #define BIOS_SIZE BIOS_SIZE_16M #endif -#endif +#endif /* BIOS_SIZE */ /** * @def SPREAD_SPECTRUM @@ -270,4 +274,4 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1 -#endif +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index a8ea3d6..c4bc288 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -27,11 +27,13 @@ * @def BIOS_SIZE_2M * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M + * @def BIOS_SIZE_16M */ #define BIOS_SIZE_1M 0 #define BIOS_SIZE_2M 1 #define BIOS_SIZE_4M 3 #define BIOS_SIZE_8M 7 +#define BIOS_SIZE_16M 15 /* In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -46,8 +48,10 @@ #define BIOS_SIZE BIOS_SIZE_4M #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 #define BIOS_SIZE BIOS_SIZE_8M +#elif CONFIG_COREBOOT_ROMSIZE_KB_16484 == 1 + #define BIOS_SIZE BIOS_SIZE_16M #endif -#endif +#endif /* BIOS_SIZE */ /** * @def SPREAD_SPECTRUM @@ -273,4 +277,4 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1 -#endif +#endif /* _PLATFORM_CFG_H_ */
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Patch set updated for coreboot: 39c29f6 util/superiotool: Add initial support for Fintek F71869AD.
by Edward O'Callaghan
26 Jan '14
26 Jan '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4802
-gerrit commit 39c29f61dc96554fb06cc34d0bc9c8d1e34ae442 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 26 00:19:58 2014 +1100 util/superiotool: Add initial support for Fintek F71869AD. See gerrit comment for Fintek F71869AD data-sheet. Change-Id: Ia2ce8214d8b419d0ca0186e6f6b2241097b0847b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/superiotool/README | 2 +- util/superiotool/fintek.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/util/superiotool/README b/util/superiotool/README index dfa6c1c..a7eb3db 100644 --- a/util/superiotool/README +++ b/util/superiotool/README @@ -93,6 +93,7 @@ Bingxun Shi <bingxunshi(a)gmail.com> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> David Bartley <dtbartle(a)csclub.uwaterloo.ca> David Hendricks <david.hendricks(a)gmail.com> +Edward O'Callaghan <eocallaghan(a)alterapraxis.com> François-Regis Vuillemin <coreboot(a)miradou.com> Frieder Ferlemann <Frieder.Ferlemann(a)web.de> Idwer Vollering <idwer_v(a)hotmail.com> @@ -113,4 +114,3 @@ Ulf Jordan <jordan(a)chalmers.se> Urja Rannikko <urjaman(a)gmail.com> Uwe Hermann <uwe(a)hermann-uwe.de> Ward Vandewege <ward(a)gnu.org> - diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 6ba962a..a86e4d0 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -3,6 +3,7 @@ * * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,6 +77,47 @@ static const struct superio_registers reg_table[] = { {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, {EOT}}}, + {0x0710, "F71869AD", { /* XXX: verify correct product ID?? */ + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, + 0x2b,0x2c,0x2d,EOT}, + {0x06,0x01,0x19,0x34,0x00,0x00,MISC,0x00,0x00,0x00, + 0x00,0x00,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}}, + {0x6, "GPIO", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3, + 0x90,0x91,0x92,0x93,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff, + NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00, + 0x00,0x3f,NANA,0x00,EOT}}, + {0x7, "BSEL", + {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfe,0xff,EOT}, + {0x00,0x00,0x00,NANA,NANA,0x06,0x1c,0x1f,0x86,0x00,0x00,0x00,0x00,EOT}}, + {EOT}}}, {0x2307, "F71889", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL,
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Patch set updated for coreboot: b7f6ea6 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
by Edward O'Callaghan
26 Jan '14
26 Jan '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4801
-gerrit commit b7f6ea6cc0c6a367e055d579a4a50c3d2558ae05 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 25 21:46:10 2014 +1100 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support. Step 2: change the Persimmon code to adapt it to the new board's hardware. The NF81-T56N-LF is a IPC form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) APU - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (1.5 or 1.35V)? - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0/1.1 ports - 5x SATA3 6Gb/s, 1x mSATA socket - 6-Channel HD Audio (via VIA VT1705)?? - PCI and ISA (via ITE IT8888)?? - NEC uPD78F0532 microcontroller on I2C ("SEMA")?? - 2x RJ45 GbE (via Realtek RTL8111E x2) - Fintek F71869AD Super I/O - PS/2 KB/MS port - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver) - GPIO header - CIR header - 1x MXIC MX25L1606E (SO8, soldered) 16 MB SPI flash (BIOS)
http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5…
Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/Kconfig | 3 +++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 18 ++++++++++-------- src/mainboard/jetway/nf81-t56n-lf/board_info.txt | 5 +++-- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 14 ++++++++------ src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 3 +++ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 6 +++--- 6 files changed, 30 insertions(+), 19 deletions(-) diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 7e6e29d..e19b42e 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D bool "J7F4K1G5D" config BOARD_JETWAY_PA78VM5 bool "PA78VM5 (Fam10)" +config BOARD_JETWAY_NF81-T56N-LF + bool "NF81-T56N-LF" endchoice @@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig" source "src/mainboard/jetway/j7f4k1g2e/Kconfig" source "src/mainboard/jetway/j7f4k1g5d/Kconfig" source "src/mainboard/jetway/pa78vm5/Kconfig" +source "src/mainboard/jetway/nf81-t56n-lf/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index febd8dd..c4efb7f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,7 +18,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_AMD_PERSIMMON +if BOARD_JETWAY_NF81-T56N-LF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME +# Disable S3 for now. Leave here for now (WIP) +# select HAVE_ACPI_RESUME select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_16484 select GFXUMA config MAINBOARD_DIR string - default amd/persimmon + default jetway/nf81-t56n-lf config APIC_ID_OFFSET hex @@ -48,7 +50,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "NF81-T56N-LF" config HW_MEM_HOLE_SIZEK hex @@ -101,7 +103,7 @@ config VGA_BIOS config VGA_BIOS_ID string - default "1002,9802" + default "1002,9806" # FUSION_G_T56N config SB800_AHCI_ROM bool @@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD bool default n -endif # BOARD_AMD_PERSIMMON +endif # BOARD_JETWAY_NF81-T56N-LF diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt index 85cb19a..86e37a9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt +++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt @@ -1,5 +1,6 @@ -Board name: DBFT1-00-EVAL-KT (Persimmon) -Category: eval +Board URL:
http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5…
+Category: IPC Board +ROM package: SOIC8 ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 8b1acd5..4f6006a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -29,6 +30,7 @@ chip northbridge/amd/agesa/family14/root_complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 1.1 on end # Internal Audio P2P bridge 0x1314 device pci 4.0 on end # PCIE P2P bridge on-board NIC device pci 5.0 off end # PCIE P2P bridge device pci 6.0 on end # PCIE P2P bridge PCIe slot @@ -53,7 +55,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f + chip superio/fintek/f71869ad device pnp 4e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -76,17 +78,17 @@ chip northbridge/amd/agesa/family14/root_complex io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + end # f71869ad end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB + device pci 14.5 on end # OHCI FS/LS USB (0x4399) device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA + device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 + device pci 16.0 on end # OHCI USB 10-13 (0x4397) + device pci 16.2 on end # EHCI USB 10-13 (0x4396) register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index 0578e27..a8ea3d6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -227,6 +228,7 @@ */ #define GEC_CONFIG 0 +/* XXX: Fix this for sound to work! */ static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ @@ -244,6 +246,7 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; +/* XXX: Fix this for sound to work! */ static const CODECTBLLIST codec_tablelist[] = { {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 98c64ed..f2b9406 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -45,7 +45,7 @@ void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, F71869AD_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -70,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }
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New patch to review for coreboot: bfb6f0f YOU SHALL NOT MERGE!
by Alexandru Gagniuc
26 Jan '14
26 Jan '14
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4810
-gerrit commit bfb6f0f224ab2f8dd91c20c3e636692a044c59e2 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 24 19:49:07 2014 -0600 YOU SHALL NOT MERGE! , _,- (\ _,-',' \\ ,-" ,' \\ ,' ,' \\ _:.----__.-."-._,-._ \\ .-".:--`:::::.:.:' ) `-. \\ `. ::L .::::::'`-._ ( ) : \\ ":::::::' `-. `-_ ) ,' \\.._/_`:::,' `. . `-: :" _ "\"" `-_ . ` `. "\\"":--\ `-.__ ` . `. \\':: \ _-"__`--.__ ` . `. _,--..- \\ :: \_-":)( ""-._ ` `.-'' \\`:`-":::/ \\ . . `-. : :\\:::::::' \\ ` . `. : :\\:':':' . \\ `, : : : \\ . \\ . `. : ,- __`:\\ . \\ . ` ,' ,: : ,-' _,---"" : \\ ' \\ . :-" ,' ,-"" : \\: . : \\ ` ' ,' / ' : : \ . \\ . _,' ,-' : . ' : :` `,-' ,--' : : : ,'-._,' ,-' _: : :8: ,--' :dd`-._,'-._.__-""' ,' ,----' _.----' __..--"" "" cbfstool: add preliminary partitioning suport Based on Proposal 2 of my user page Change-Id: I6770a9f8a459b4f204f5a75b98897a502af3ac66 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/Makefile.inc | 1 + util/cbfstool/cbfs.h | 15 ++++++++++- util/cbfstool/cbfs_image.c | 36 +++++++++++++++++++++++++++ util/cbfstool/cbfs_image.h | 2 ++ util/cbfstool/cbfs_partition.c | 56 ++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/cbfs_partition.h | 20 +++++++++++++++ util/cbfstool/cbfstool.c | 2 ++ 7 files changed, 131 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index fc120f3..c5d284c 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -3,6 +3,7 @@ cbfsobj += cbfstool.o cbfsobj += common.o cbfsobj += compress.o cbfsobj += cbfs_image.o +cbfsobj += cbfs_partition.o cbfsobj += cbfs-mkstage.o cbfsobj += cbfs-mkpayload.o cbfsobj += fit.o diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 35d0670..423e903 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -35,13 +35,26 @@ struct cbfs_header { uint32_t align; uint32_t offset; uint32_t architecture; /* Version 2 */ - uint32_t pad[1]; + uint32_t ptable_offset; } __attribute__ ((packed)); #define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF #define CBFS_ARCHITECTURE_X86 0x00000001 #define CBFS_ARCHITECTURE_ARMV7 0x00000010 +#define CBFS_PARTITION_MAGIC 0x43425054 /* "CBPT" in ASCII */ +#define CBFS_PARTITION_NAME_LEN 32 +#define CBFS_PARTITION_ENTRY_LEN 0x30 +#define CBFS_PARTITION_ENTRY_ALIGN 0x10 + +struct cbfs_partition { + uint32_t magic; + uint32_t offset; + uint32_t size; + uint32_t flags; + char name[32]; +}; /* Don't fucking pack this. If you need this packed, you have a bug */ + #define CBFS_FILE_MAGIC "LARCHIVE" struct cbfs_file { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 401654e..66cf32f 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -25,6 +25,7 @@ #include "common.h" #include "cbfs_image.h" +#include "cbfs_partition.h" /* The file name align is not defined in CBFS spec -- only a preference by * (old) cbfstool. */ @@ -145,10 +146,12 @@ int cbfs_image_create(struct cbfs_image *image, struct buffer *bootblock, int32_t bootblock_offset, int32_t header_offset, + int32_t ptable_offset, int32_t entries_offset) { struct cbfs_header *header; struct cbfs_file *entry; + struct cbfs_partition part; uint32_t cbfs_len; size_t entry_header_len; @@ -159,6 +162,8 @@ int cbfs_image_create(struct cbfs_image *image, if (buffer_create(&image->buffer, size, "(new)") != 0) return -1; + if ((image->ptable = malloc(sizeof(part) * 11)) == NULL) + return -1; image->header = NULL; memset(image->buffer.data, CBFS_CONTENT_DEFAULT_VALUE, size); @@ -229,6 +234,33 @@ int cbfs_image_create(struct cbfs_image *image, if (header_offset > entries_offset && header_offset < cbfs_len) cbfs_len = header_offset; cbfs_len -= entries_offset + align + entry_header_len; + + /* + * Now find space for the partition table. + * Pre-allocate 10 entries for now. This should be sufficient for most + * use-cases, and makes sure we don't have to reduce the final entry. + * FIXME: Only works for bootblock on top. We really should listen to + * the wisdom of the caller and put this where requested. + */ + ptable_offset = header_offset - cbfs_ptable_calc_size(10); + /* Align down */ + ptable_offset &= ~(CBFS_PARTITION_ENTRY_ALIGN - 1); + cbfs_len -= (bootblock_offset - ptable_offset); + if (IS_TOP_ALIGNED_ADDRESS(header_offset)) + header_offset += (int32_t) size; + header->ptable_offset = ntohl(ptable_offset); + + LOG("pizdatable offset 0x%x\n", ptable_offset); + + /* No, don't use ntohl shit here */ + cbfs_partition_entry_init(&image->ptable[0], + "coreboot", entries_offset, cbfs_len, 0); + /* Terminate ptable list */ + image->ptable[1].magic = 0xFFFFFFFF; + + cbfs_ptable_serialize(image->buffer.data + ptable_offset, + image->ptable); + cbfs_create_empty_entry(image, entry, cbfs_len, ""); LOG("Created CBFS image (capacity = %d bytes)\n", cbfs_len); return 0; @@ -247,6 +279,7 @@ int cbfs_image_from_file(struct cbfs_image *image, const char *filename) cbfs_image_delete(image); return -1; } + image->ptable = NULL; cbfs_fix_legacy_size(image); return 0; @@ -261,7 +294,10 @@ int cbfs_image_write_file(struct cbfs_image *image, const char *filename) int cbfs_image_delete(struct cbfs_image *image) { buffer_delete(&image->buffer); + if (image->ptable) + free(image->ptable); image->header = NULL; + image->ptable = NULL; return 0; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 7ad418a..847ee5d 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -29,6 +29,7 @@ struct cbfs_image { struct buffer buffer; struct cbfs_header *header; + struct cbfs_partition *ptable; }; /* Creates an empty CBFS image by given size, and description to its content @@ -43,6 +44,7 @@ int cbfs_image_create(struct cbfs_image *image, struct buffer *bootblock, int32_t bootblock_offset, int32_t header_offset, + int32_t ptable_offset, int32_t entries_offset); /* Loads a CBFS image from file. Returns 0 on success, otherwise non-zero. */ diff --git a/util/cbfstool/cbfs_partition.c b/util/cbfstool/cbfs_partition.c new file mode 100644 index 0000000..9315c94 --- /dev/null +++ b/util/cbfstool/cbfs_partition.c @@ -0,0 +1,56 @@ +/* + * Manipulators for CBFS partitions + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "cbfs_partition.h" +#include "endian_stream.h" +#include "../../payloads/external/GRUB2/grub2/grub-core/lib/libgcrypt-grub/src/types.h" + +#include <string.h> + +size_t cbfs_ptable_calc_size(size_t num_entries) +{ + /* The last 4 bytes are the table terminator */ + return CBFS_PARTITION_ENTRY_LEN * num_entries + 4; +} + +void cbfs_partition_entry_init(struct cbfs_partition *part, const char *name, + uint32_t offset, uint32_t size, uint32_t fags) +{ + part->magic = CBFS_PARTITION_MAGIC; + part->offset = offset; + part->size = size; + part->flags = fags; + strncpy(part->name, name, CBFS_PARTITION_NAME_LEN); +} + +void cbfs_partition_serialize(void *dest, const struct cbfs_partition *part) +{ + h_to_be32(part->magic, dest + 0); + h_to_be32(part->offset, dest + 4); + h_to_be32(part->size, dest + 8); + h_to_be32(part->flags, dest + 12); + memset(dest, 0xff, CBFS_PARTITION_NAME_LEN); + strncpy(dest + 16, part->name, CBFS_PARTITION_NAME_LEN); +} + +void cbfs_partition_deserialize(struct cbfs_partition *part, const void *src) +{ + part->magic = be32_to_h(src + 0); + part->offset = be32_to_h(src + 4); + part->size = be32_to_h(src + 8); + part->flags = be32_to_h(src + 12); + strncpy(part->name, src + 16, CBFS_PARTITION_NAME_LEN); +} + +void cbfs_ptable_serialize(void *dest, const struct cbfs_partition *part) +{ + while (part->magic == CBFS_PARTITION_MAGIC) { + cbfs_partition_serialize(dest, part); + part++; + dest += 16; + } +} diff --git a/util/cbfstool/cbfs_partition.h b/util/cbfstool/cbfs_partition.h new file mode 100644 index 0000000..b6d6cf4 --- /dev/null +++ b/util/cbfstool/cbfs_partition.h @@ -0,0 +1,20 @@ +/* + * Prototypes for manipulating for CBFS partitions + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CBFS_PARTITION_H +#define __CBFS_PARTITION_H + +#include "cbfs.h" +#include <stddef.h> + +void cbfs_partition_entry_init(struct cbfs_partition *part, const char *name, + uint32_t offset, uint32_t size, uint32_t flags); +void cbfs_partition_serialize(void *dest, const struct cbfs_partition *part); +void cbfs_partition_deserialize(struct cbfs_partition *part, const void *src); +size_t cbfs_ptable_calc_size(size_t num_entries); +void cbfs_ptable_serialize(void *dest, const struct cbfs_partition *part); +#endif /* __CBFS_PARTITION_H */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 34002a9..0040a98 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -55,6 +55,7 @@ static struct param { uint32_t pagesize; uint32_t offset; uint32_t top_aligned; + uint32_t ptable_offset; int fit_empty_entries; comp_algo algo; /* for linux payloads */ @@ -373,6 +374,7 @@ static int cbfs_create(void) &bootblock, param.baseaddress, param.headeroffset, + param.ptable_offset, param.offset) != 0) { ERROR("Failed to create %s.\n", param.cbfs_name); return 1;
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New patch to review for coreboot: e15d0d4 board_status.sh: Add lspci and lsusb output to status.
by Vladimir Serbinenko
25 Jan '14
25 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4809
-gerrit commit e15d0d451702596d89633f80205abf942498fd59 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 25 22:22:15 2014 +0100 board_status.sh: Add lspci and lsusb output to status. Change-Id: I08fd86e72cec4622dcd2ddae55f9a60c3eb19eaa Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/board_status.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 735932b..70b37fd 100644 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -173,6 +173,9 @@ cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" cmd_nonfatal $REMOTE "cbmem -t" "${tmpdir}/${results}/coreboot_timestamps.txt" cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt" +cmd_nonfatal $REMOTE "lspci -vvnnxxx" "${tmpdir}/${results}/lspci.txt" +cmd_nonfatal $REMOTE "lsusb" "${tmpdir}/${results}/lsusb.txt" +cmd_nonfatal $REMOTE "lsusb -t" "${tmpdir}/${results}/lsusb_tree.txt" # # Finish up.
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Patch set updated for coreboot: 3bfea76 pcengines/alix6: Make clone declaration in line with other clones.
by Vladimir Serbinenko
25 Jan '14
25 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4756
-gerrit commit 3bfea7600f5da05b10e4c197a74627766ca1322d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Jan 20 03:03:38 2014 +0100 pcengines/alix6: Make clone declaration in line with other clones. Change-Id: I4e56f6b37314bff569728b732b4115fb940f70dd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/pcengines/Kconfig | 1 + src/mainboard/pcengines/alix2d/Kconfig | 7 +++++-- src/mainboard/pcengines/alix2d/board_info.txt | 1 - src/mainboard/pcengines/alix6/Kconfig | 10 ++++++++++ src/mainboard/pcengines/alix6/board_info.txt | 5 +++++ 5 files changed, 21 insertions(+), 3 deletions(-) diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index e967267..197d7d1 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -14,6 +14,7 @@ endchoice source "src/mainboard/pcengines/alix1c/Kconfig" source "src/mainboard/pcengines/alix2d/Kconfig" +source "src/mainboard/pcengines/alix6/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 2343d70..318b476 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -16,10 +16,13 @@ config MAINBOARD_DIR string default pcengines/alix2d +if BOARD_PCENGINES_ALIX2D + config MAINBOARD_PART_NUMBER string - default "ALIX.2D" if BOARD_PCENGINES_ALIX2D - default "ALIX.6" if BOARD_PCENGINES_ALIX6 + default "ALIX.2D" + +endif config IRQ_SLOT_COUNT int diff --git a/src/mainboard/pcengines/alix2d/board_info.txt b/src/mainboard/pcengines/alix2d/board_info.txt index d603aaa..0b63050 100644 --- a/src/mainboard/pcengines/alix2d/board_info.txt +++ b/src/mainboard/pcengines/alix2d/board_info.txt @@ -1,4 +1,3 @@ -Board name: ALIX.2D Category: half Board URL:
http://pcengines.ch/alix2d0.htm
Flashrom support: y diff --git a/src/mainboard/pcengines/alix6/Kconfig b/src/mainboard/pcengines/alix6/Kconfig new file mode 100644 index 0000000..4329f19 --- /dev/null +++ b/src/mainboard/pcengines/alix6/Kconfig @@ -0,0 +1,10 @@ +if BOARD_PCENGINES_ALIX6 + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "ALIX.6" + +endif diff --git a/src/mainboard/pcengines/alix6/board_info.txt b/src/mainboard/pcengines/alix6/board_info.txt new file mode 100644 index 0000000..db8bbb2 --- /dev/null +++ b/src/mainboard/pcengines/alix6/board_info.txt @@ -0,0 +1,5 @@ +Category: half +Board URL:
http://pcengines.ch/alix6f2.htm
+Flashrom support: y +Clone of: pcengines/alix2d +
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Patch set updated for coreboot: 04f51bb adlink/lippert: Add Adlink names for devices with both names.
by Vladimir Serbinenko
25 Jan '14
25 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4744
-gerrit commit 04f51bb31a8ee99672c769ebecbb1926fef6d066 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 05:34:14 2014 +0100 adlink/lippert: Add Adlink names for devices with both names. Change-Id: I6a3f089309a2610986545e4e45e35569ea2772ed Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/adlink/Kconfig | 13 +++++++++++++ src/mainboard/adlink/cexpress-gfr/Kconfig | 10 ++++++++++ src/mainboard/adlink/cexpress-gfr/board_info.txt | 8 ++++++++ src/mainboard/adlink/coremodule2-gf/Kconfig | 10 ++++++++++ src/mainboard/adlink/coremodule2-gf/board_info.txt | 7 +++++++ src/mainboard/lippert/Kconfig | 9 +++++++-- src/mainboard/lippert/frontrunner-af/Kconfig | 6 +++++- src/mainboard/lippert/toucan-af/Kconfig | 6 +++++- 8 files changed, 65 insertions(+), 4 deletions(-) diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig index f71d6a9..635a763 100644 --- a/src/mainboard/adlink/Kconfig +++ b/src/mainboard/adlink/Kconfig @@ -3,8 +3,21 @@ if VENDOR_ADLINK comment "see under vendor LiPPERT" # any further boards will then be ADLINK +choice + prompt "Mainboard model" + +config BOARD_ADLINK_COREMODULE2_GF + bool "CoreModule2-GF aka LiPPPERT FrontRunner-AF" +config BOARD_ADLINK_CEXPRESS_GFR + bool "cExpress-GFR (+W83627DHG SIO) aka LiPPERT Toucan-AF" + +endchoice + config MAINBOARD_VENDOR string default "ADLINK" +source "src/mainboard/adlink/cexpress-gfr/Kconfig" +source "src/mainboard/adlink/coremodule2-gf/Kconfig" + endif # VENDOR_ADLINK diff --git a/src/mainboard/adlink/cexpress-gfr/Kconfig b/src/mainboard/adlink/cexpress-gfr/Kconfig new file mode 100644 index 0000000..ad670d1 --- /dev/null +++ b/src/mainboard/adlink/cexpress-gfr/Kconfig @@ -0,0 +1,10 @@ +if BOARD_ADLINK_CEXPRESS_GFR + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "cExpress-GFR" + +endif diff --git a/src/mainboard/adlink/cexpress-gfr/board_info.txt b/src/mainboard/adlink/cexpress-gfr/board_info.txt new file mode 100644 index 0000000..7776aaa --- /dev/null +++ b/src/mainboard/adlink/cexpress-gfr/board_info.txt @@ -0,0 +1,8 @@ +Board name: cExpress-GFR (+W83627DHG SIO) +Category: half +Board URL:
http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132
+ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/toucan-af diff --git a/src/mainboard/adlink/coremodule2-gf/Kconfig b/src/mainboard/adlink/coremodule2-gf/Kconfig new file mode 100644 index 0000000..8513062 --- /dev/null +++ b/src/mainboard/adlink/coremodule2-gf/Kconfig @@ -0,0 +1,10 @@ +if BOARD_ADLINK_COREMODULE2_GF + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "CoreModule2-GF" + +endif diff --git a/src/mainboard/adlink/coremodule2-gf/board_info.txt b/src/mainboard/adlink/coremodule2-gf/board_info.txt new file mode 100644 index 0000000..6bf07f8 --- /dev/null +++ b/src/mainboard/adlink/coremodule2-gf/board_info.txt @@ -0,0 +1,7 @@ +Board URL:
http://www.adlinktech.com/PD/web/PD_detail.php?pid=1283
+Category: half +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/frontrunner-af diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 5d69aae..afb2370 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -23,15 +23,20 @@ config BOARD_LIPPERT_TOUCAN_AF endchoice source "src/mainboard/lippert/frontrunner/Kconfig" -source "src/mainboard/lippert/frontrunner-af/Kconfig" source "src/mainboard/lippert/hurricane-lx/Kconfig" source "src/mainboard/lippert/literunner-lx/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" -source "src/mainboard/lippert/toucan-af/Kconfig" config MAINBOARD_VENDOR string default "LiPPERT" endif # VENDOR_LIPPERT + +if VENDOR_LIPPERT || VENDOR_ADLINK + +source "src/mainboard/lippert/frontrunner-af/Kconfig" +source "src/mainboard/lippert/toucan-af/Kconfig" + +endif diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index a0dbaf9..c4e540f 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_LIPPERT_FRONTRUNNER_AF +if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_ADLINK_COREMODULE2_GF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -50,10 +50,14 @@ config APIC_ID_OFFSET hex default 0x0 +if BOARD_LIPPERT_FRONTRUNNER_AF + config MAINBOARD_PART_NUMBER string default "FrontRunner-AF" +endif + config HW_MEM_HOLE_SIZEK hex default 0x200000 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 904c7c8..6acc43a 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_LIPPERT_TOUCAN_AF +if BOARD_LIPPERT_TOUCAN_AF || BOARD_ADLINK_CEXPRESS_GFR config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -52,10 +52,14 @@ config APIC_ID_OFFSET hex default 0x0 +if BOARD_LIPPERT_TOUCAN_AF + config MAINBOARD_PART_NUMBER string default "Toucan-AF" +endif + config HW_MEM_HOLE_SIZEK hex default 0x200000
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Patch set updated for coreboot: 447b267 smbios: Remove leading whitespaces in CPU name.
by Vladimir Serbinenko
25 Jan '14
25 Jan '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4750
-gerrit commit 447b26786de4ee5c98e65cb75fe02dd7f1bcad6d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 15:33:00 2014 +0100 smbios: Remove leading whitespaces in CPU name. Change-Id: I7d20936e59271157f05948dae514150d5dee4c87 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/smbios.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..b9373d4 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -99,6 +99,7 @@ static int smbios_processor_name(char *start) { char tmp[49] = "Unknown Processor Name"; u32 *_tmp = (u32 *)tmp; + char *ptr; struct cpuid_result res; int i; @@ -115,7 +116,10 @@ static int smbios_processor_name(char *start) tmp[48] = 0; } } - return smbios_add_string(start, tmp); + + for (ptr = tmp; *ptr == ' '; ptr++); + + return smbios_add_string(start, ptr); } static int smbios_write_type0(unsigned long *current, int handle)
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Patch set updated for coreboot: 15bb56b cbfstool: Add portable endian conversion helpers
by Alexandru Gagniuc
25 Jan '14
25 Jan '14
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4792
-gerrit commit 15bb56b2a795f15c719b0cfd5dcfed755b72efbe Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 24 16:33:50 2014 -0600 cbfstool: Add portable endian conversion helpers These helpers rely on the idea that external data is a stream with a known structure, and that the internal representation of data on the host is irrelevant. When properly used, these helpers eliminate the need to rely on the packed nature of structs. This only adds the helpers. Changing the code to perform proper serialization and deserialization of data will be implemented in the future. Change-Id: I697399193846ed741cda4801211b13f6c1e35742 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/endian_stream.h | 112 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/util/cbfstool/endian_stream.h b/util/cbfstool/endian_stream.h new file mode 100644 index 0000000..41a29bf --- /dev/null +++ b/util/cbfstool/endian_stream.h @@ -0,0 +1,112 @@ +/* + * Endian conversion helpers + * + * These helpers are based on the idea that outside data is a stream of well + * defined structure (including byte order), and that no assumptions are made + * about the internal representation of data on the host. For example, there is + * no notion of byte order, structure packing on the host. + * + * They allow the proper serialization and deserialization of data from host + * structs to data streams without relying on the notion of byte swaps. + * + * To enforce this philosophy, these endian conversion helpers always treat host + * data as standard integers types, and external data as streams identified by + * a pointer. + * + * So rather than extracting a structure in the following incorrect way: + * memcpy(host_struct, src, size); + * host_struct->member1 = ntoh(host_struct->member) + * host_struct->member2 = ntohl(host_struct->member2) + * + * These helpers make the process more portable and less compiler-dependent: + * host_struct->member1 = be16_to_h(src + 0); + * host_struct->member2 = be32_to_h(src + 2); + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CBFSTOOL_ENDIAN_STREAM_H +#define __CBFSTOOL_ENDIAN_STREAM_H + +inline static uint8_t le8_to_h(const void *src) +{ + const uint8_t *b = src; + return b[0]; +}; + +inline static uint16_t le16_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[1] << 8) | (b[0] << 0)); +}; + +inline static uint32_t le32_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); +}; + +inline static void h_to_le8(uint8_t val8, void *dest) +{ + uint8_t *b = dest; + b[0] = val8; +}; + +inline static void h_to_le16(uint16_t val16, void *dest) +{ + uint8_t *b = dest; + b[0] = (val16 >> 0) & 0xff; + b[1] = (val16 >> 8) & 0xff; +}; + +inline static void h_to_le32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 0) & 0xff; + b[1] = (val32 >> 8) & 0xff; + b[2] = (val32 >> 16) & 0xff; + b[3] = (val32 >> 24) & 0xff; +}; + +inline static uint8_t be8_to_h(const void *src) +{ + const uint8_t *b = src; + return b[0]; +}; + +inline static uint16_t be16_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[1] << 0) | (b[0] << 16)); +}; + +inline static uint32_t be32_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[3] << 0) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24)); +}; + +inline static void h_to_be8(uint8_t val8, void *dest) +{ + uint8_t *b = dest; + b[0] = val8; +}; + +inline static void h_to_be16(uint16_t val16, void *dest) +{ + uint8_t *b = dest; + b[0] = (val16 >> 8) & 0xff; + b[1] = (val16 >> 0) & 0xff; +}; + +inline static void h_to_be32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 24) & 0xff; + b[1] = (val32 >> 16) & 0xff; + b[2] = (val32 >> 8) & 0xff; + b[3] = (val32 >> 0) & 0xff; +}; + +#endif /* __CBFSTOOL_ENDIAN_STREAM_H */
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Patch set updated for coreboot: cfb831f cbfstool: Add portable endian conversion helpers
by Alexandru Gagniuc
25 Jan '14
25 Jan '14
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4792
-gerrit commit cfb831fd2f3d776212979591f6cb31dcb8306aae Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 24 16:33:50 2014 -0600 cbfstool: Add portable endian conversion helpers These helpers rely on the idea that external data is a stream with a known structure, and that the internal representation of data on the host is irrelevant. When properly used, these helpers eliminate the need to rely on the packed nature of structs. This only adds the helpers. Changing the code to perform proper serialization and deserialization of data will be implemented in the future. Change-Id: I697399193846ed741cda4801211b13f6c1e35742 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/endian_stream.h | 112 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/util/cbfstool/endian_stream.h b/util/cbfstool/endian_stream.h new file mode 100644 index 0000000..3e21389 --- /dev/null +++ b/util/cbfstool/endian_stream.h @@ -0,0 +1,112 @@ +/* + * Endian conversion helpers + * + * These helpers are based on the idea that outside data is a stream of well + * defined structure (including byte order), and that no assumptions are made + * about the internal representation of data on the host. For example, there is + * no notion of byte order, structure packing on the host. + * + * They allow the proper serialization and deserialization of data from host + * structs to data streams without relying on the notion of byte swaps. + * + * To enforce this philosophy, these endian conversion helpers always treat host + * data as standard integers types, and external data as streams identified by + * a pointer. + * + * So rather than extracting a structure in the following incorrect way: + * memcpy(host_struct, src, size); + * host_struct->member1 = ntoh(host_struct->member) + * host_struct->member2 = ntohl(host_struct->member2) + * + * These helpers make the process more portable and less compiler-dependent: + * host_struct->member1 = be16_to_h(src + 0); + * host_struct->member2 = be32_to_h(src + 2); + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CBFSTOOL_ENDIAN_STREAM_H +#define __CBFSTOOL_ENDIAN_STREAM_H + +inline static uint8_t le8_to_h(const void *src) +{ + uint8_t *b = src; + return b[0]; +}; + +inline static uint16_t le16_to_h(const void *src) +{ + uint8_t *b = src; + return ((b[1] << 8) | (b[0] << 0)); +}; + +inline static uint32_t le32_to_h(const void *src) +{ + uint8_t *b = src; + return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); +}; + +inline static void h_to_le8(uint8_t val8, void *dest) +{ + uint8_t *b = dest; + b[0] = val8; +}; + +inline static void h_to_le16(uint16_t val16, void *dest) +{ + uint8_t *b = dest; + b[0] = (val16 >> 0) & 0xff; + b[1] = (val16 >> 8) & 0xff; +}; + +inline static void h_to_le32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 0) & 0xff; + b[1] = (val32 >> 8) & 0xff; + b[2] = (val32 >> 16) & 0xff; + b[3] = (val32 >> 24) & 0xff; +}; + +inline static uint8_t be8_to_h(const void *src) +{ + uint8_t *b = src; + return b[0]; +}; + +inline static uint16_t be16_to_h(const void *src) +{ + uint8_t *b = src; + return ((b[1] << 0) | (b[0] << 16)); +}; + +inline static uint32_t be32_to_h(const void *src) +{ + uint8_t *b = src; + return ((b[3] << 0) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24)); +}; + +inline static void h_to_be8(uint8_t val8, void *dest) +{ + uint8_t *b = dest; + b[0] = val8; +}; + +inline static void h_to_be16(uint16_t val16, void *dest) +{ + uint8_t *b = dest; + b[0] = (val16 >> 8) & 0xff; + b[1] = (val16 >> 0) & 0xff; +}; + +inline static void h_to_be32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 24) & 0xff; + b[1] = (val32 >> 16) & 0xff; + b[2] = (val32 >> 8) & 0xff; + b[3] = (val32 >> 0) & 0xff; +}; + +#endif /* __CBFSTOOL_ENDIAN_STREAM_H */
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