coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: e29584c usbdebug: Use separate data toggle for each pipe
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit e29584c1410e27db86df6fb4b5dcf5c1c00d6f68 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:50:38 2013 +0300 usbdebug: Use separate data toggle for each pipe USB defines a mechanism to detect certain cases of lost handshakes using an alternating data sequence number, referred to as data toggling. This patch fixes each pipe to have its own tracking of the data toggle state. Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3865 for details. -gerrit

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Patch merged into coreboot/master: 75d0062 usbdebug: Reference endpoints by pipes in calls
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit 75d006232a010db24e740340a9e8271b1a75e9bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:34:01 2013 +0300 usbdebug: Reference endpoints by pipes in calls Add allocation for endpoint0 as a pipe for control messages. Endpoint number was already stored in the pipe object, place devnum there too, although all pipes will use same devnum==127. Change-Id: I299d139bdd8083af8b04a694e8e41435ec026a25 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3864 for details. -gerrit

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Patch merged into coreboot/master: 545b30d intel usbdebug: Add choice of EHCI controller
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit 545b30d151276324cfd04b1d053d2a8c8d7cf7fd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 13 13:51:14 2013 +0300 intel usbdebug: Add choice of EHCI controller Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3440 for details. -gerrit

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Patch merged into coreboot/master: 8101aa6 usbdebug: Support choice of EHCI controller
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit 8101aa6bb02c586cd0d1ab2cf99148329319aaf9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 15 16:27:06 2013 +0300 usbdebug: Support choice of EHCI controller Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3438 for details. -gerrit

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Patch merged into coreboot/master: 2410010 usbdebug: Change debug port scanning
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit 24100100181bd770ce0f1181a1770a0808790cde Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 12 20:40:37 2013 +0300 usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3872 for details. -gerrit

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Patch merged into coreboot/master: f7381f8 kontron/ktqm77: Allow disabling onboard NICs
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit f7381f8cd1cf4307dcccd5728fc11afce3610439 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Aug 15 14:57:09 2013 +0200 kontron/ktqm77: Allow disabling onboard NICs Two new nvram variables control disabling the two non-ME NICs on the mainboard. This is implemented by disabling their PCIe bridge. Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/3870 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3870 for details. -gerrit

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Patch merged into coreboot/master: ab6d27e lenovo/x60/romstage.c: Collect timestamps in romstage
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit ab6d27e8f83db2791bc2b633a02f12a3076a4e5f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 2 09:54:17 2013 +0200 lenovo/x60/romstage.c: Collect timestamps in romstage Collect early timestamps in Lenovo X60’s romstage. Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3587 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3587 for details. -gerrit

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Patch set updated for coreboot: 1a470af lenovo/x60/romstage.c: Collect timestamps in romstage
by Ronald G. Minnich 29 Aug '13

29 Aug '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3587 -gerrit commit 1a470afe5954217627b694c2ae08b85c0bbc8a69 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 2 09:54:17 2013 +0200 lenovo/x60/romstage.c: Collect timestamps in romstage Collect early timestamps in Lenovo X60’s romstage. Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/romstage.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 222b999..4d0eac7 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -218,6 +219,20 @@ void main(unsigned long bist) int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + if (bist == 0) enable_lapic(); @@ -281,7 +296,13 @@ void main(unsigned long bist) dump_spd_registers(); #endif +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif sdram_initialize(boot_mode, spd_addrmap); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -340,6 +361,14 @@ void main(unsigned long bist) } #endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit();

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Patch set updated for coreboot: 25118d0 lenovo/x60/romstage.c: Collect timestamps in romstage
by Stefan Reinauer 29 Aug '13

29 Aug '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3587 -gerrit commit 25118d00372256e50ed750bbcf68b847b0d054e7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 2 09:54:17 2013 +0200 lenovo/x60/romstage.c: Collect timestamps in romstage Collect early timestamps in Lenovo X60’s romstage like the Lenovo T60 does (»lenovo/t60: Collect timestamps in romstage« (44c392f8) [1]). Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. [1] http://review.coreboot.org/3499 Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/romstage.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 222b999..4d0eac7 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -218,6 +219,20 @@ void main(unsigned long bist) int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + if (bist == 0) enable_lapic(); @@ -281,7 +296,13 @@ void main(unsigned long bist) dump_spd_registers(); #endif +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif sdram_initialize(boot_mode, spd_addrmap); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -340,6 +361,14 @@ void main(unsigned long bist) } #endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit();

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Patch merged into coreboot/master: 3c46ca3 Sandybridge/Ivybridge: Unify and fix Kconfig defaults
by gerrit＠coreboot.org 29 Aug '13

29 Aug '13

the following patch was just integrated into master: commit 3c46ca33a1c878beee839beb658fd93e8d3312a7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 13:00:03 2013 -0700 Sandybridge/Ivybridge: Unify and fix Kconfig defaults Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3830 for details. -gerrit

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coreboot-gerrit August 2013