coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 9127fe9 NOTFORMERGE: Preliminary support for new superio IT8728F.
by Damien Zammit 25 Jun '13

25 Jun '13

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3532 -gerrit commit 9127fe99158a4db51eaab6cb6d68e786a51bfe98 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Jun 26 06:25:39 2013 +1000 NOTFORMERGE: Preliminary support for new superio IT8728F. Cloned from IT8718F and verified against the datasheet for the new model. So far untested on hardware, not sure how to obtain valid IRQ settings. Change-Id: I82e23e2fe5f9651c4b7b5195b4ccee6d2d852fbe Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/superio/ite/Kconfig | 2 + src/superio/ite/Makefile.inc | 1 + src/superio/ite/it8728f/Makefile.inc | 22 +++++++ src/superio/ite/it8728f/chip.h | 33 +++++++++++ src/superio/ite/it8728f/early_serial.c | 105 +++++++++++++++++++++++++++++++++ src/superio/ite/it8728f/it8728.h | 40 +++++++++++++ src/superio/ite/it8728f/superio.c | 77 ++++++++++++++++++++++++ 7 files changed, 280 insertions(+) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index e1970e8..0cf112f 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -38,5 +38,7 @@ config SUPERIO_ITE_IT8718F bool config SUPERIO_ITE_IT8721F bool +config SUPERIO_ITE_IT8728F + bool config SUPERIO_ITE_IT8772F bool diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index ce595b8..8610eea 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -25,4 +25,5 @@ subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f subdirs-y += it8721f +subdirs-y += it8728f subdirs-y += it8772f diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc new file mode 100644 index 0000000..0989eee --- /dev/null +++ b/src/superio/ite/it8728f/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c + diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h new file mode 100644 index 0000000..8013531 --- /dev/null +++ b/src/superio/ite/it8728f/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_CHIP_H +#define SUPERIO_ITE_IT8728F_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct superio_ite_it8728f_config { + + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c new file mode 100644 index 0000000..43c431a --- /dev/null +++ b/src/superio/ite/it8728f/early_serial.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "it8728f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8728F_CONFIG_REG_CHIPVERS 0x22 /* Chip version */ +#define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ + +static void it8728f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8728F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8728f_enter_conf(void) +{ + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8728f_exit_conf(void) +{ + it8728f_sio_write(0x00, IT8728F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz default). */ +void it8728f_24mhz_clkin(void) +{ + it8728f_enter_conf(); + it8728f_sio_write(0x00, IT8728F_CONFIG_REG_CLOCKSEL, 0x1); + it8728f_exit_conf(); +} + +/* + * GIGABYTE uses a special Super I/O register to protect its Dual BIOS + * mechanism. It lives in the GPIO LDN. However, register 0xEF is not + * mentioned in the IT8728F datasheet so just hardcode it to 0x7E for now. + * (This is what the IT8718F does too). + */ +void it8728f_disable_reboot(void) +{ + it8728f_enter_conf(); + it8728f_sio_write(IT8728F_GPIO, 0xEF, 0x7E); + it8728f_exit_conf(); +} + +/* Enable the serial port(s). */ +void it8728f_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8728f_enter_conf(); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8728f_sio_write(IT8728F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8728f_sio_write(IT8728F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Clear software suspend mode (clear bit 0). TODO: Needed? */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ + + /* (3) Exit the configuration state (MB PnP mode). */ + it8728f_exit_conf(); +} diff --git a/src/superio/ite/it8728f/it8728.h b/src/superio/ite/it8728f/it8728.h new file mode 100644 index 0000000..c669a8c --- /dev/null +++ b/src/superio/ite/it8728f/it8728.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_IT8728F_H +#define SUPERIO_ITE_IT8728F_IT8728F_H + +#define IT8728F_FDC 0x00 /* Floppy */ +#define IT8728F_SP1 0x01 /* Com1 */ +#define IT8728F_SP2 0x02 /* Com2 */ +#define IT8728F_PP 0x03 /* Parallel port */ +#define IT8728F_EC 0x04 /* Environment controller */ +#define IT8728F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8728F_KBCM 0x06 /* PS/2 mouse */ +#define IT8728F_GPIO 0x07 /* GPIO */ +#define IT8728F_IR 0x0a /* Consumer IR */ + +#if defined(__PRE_RAM__) +void it8728f_24mhz_clkin(void); +void it8728f_disable_reboot(void); +void it8728f_enable_serial(device_t dev, u16 iobase); +#endif + +#endif diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c new file mode 100644 index 0000000..116e78a --- /dev/null +++ b/src/superio/ite/it8728f/superio.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "it8728f.h" + +static void init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8728F_FDC: /* TODO. */ + break; + case IT8728F_PP: /* TODO. */ + break; + case IT8728F_EC: /* TODO. */ + break; + case IT8728F_KBCK: + pc_keyboard_init(&conf->keyboard); + break; + case IT8728F_KBCM: /* TODO. */ + break; + case IT8728F_IR: /* TODO. */ + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +/* TODO: FDC, PP, EC, KBCM, IR. */ +static struct pnp_info pnp_dev_info[] = { +//??? { &ops, IT8728F_SP1, PNP_IO0 | PNP_IRQ0, {0x03f8, 0}, }, +//??? { &ops, IT8728F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x02f8, 0}, }, +//??? { &ops, IT8728F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8718f_ops = { + CHIP_NAME("ITE IT8728F Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: 77c6187 ktqm77: redesign cmos.layout slightly
by Patrick Georgi 25 Jun '13

25 Jun '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3531 -gerrit commit 77c6187ac6f8053e15c2065035437eea587fb67a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jun 25 11:14:03 2013 +0200 ktqm77: redesign cmos.layout slightly BIOS write protects 8 bytes of CMOS, which nvramtool can't cope with. This makes initial installation harder, so just mark those as reserved to work around the issue. Change-Id: I210861dff8572e226a0f250556a3b811671ea8f2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/kontron/ktqm77/cmos.layout | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 295ecd3..a110956 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -88,7 +88,8 @@ entries #411 5 r 0 unused # coreboot config options: bootloader -416 424 s 0 boot_devices +448 64 r 0 write_protected_by_bios +512 328 s 0 boot_devices 840 8 h 0 boot_default 848 1 e 9 cmos_defaults_loaded #849 7 r 0 unused

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Patch set updated for coreboot: 6db30b9 Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code.
by Andrew Wu 25 Jun '13

25 Jun '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3529 -gerrit commit 6db30b9c83b4291b3738d349842f4473e9366a1b Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Jun 25 15:16:03 2013 +0800 Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code. 6021 is Vortex86DX northbridge PCI device ID, not for Vortex86EX. Change-Id: I9bea799c9033adbcfacc8ad47052280a32f9ee59 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/northbridge/dmp/vortex86ex/northbridge.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index e3be6c3..f2344e8 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -47,12 +47,6 @@ static struct device_operations northbridge_operations = { .init = northbridge_init }; -static const struct pci_driver northbridge_driver_6021 __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_RDC, - .device = 0x6021, /* DX CPU N/B ID */ -}; - static const struct pci_driver northbridge_driver_6025 __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_RDC,

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Patch set updated for coreboot: 760f4b2 SeaBIOS: Use coreboot video BIOS settings to set seabios settings
by Bruce Griffith 25 Jun '13

25 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3528 -gerrit commit 760f4b27802bf29d34c50f93320711c9c82132c9 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Fri Jun 14 16:12:12 2013 -0600 SeaBIOS: Use coreboot video BIOS settings to set seabios settings SeaBIOS needs to know what coreboot did with option ROMs to figure out what remains to be loaded and configured. With existing Kconfig and Makefile code, the load path is assumed even though there are coreboot settings that change the processing. Change the SeaBIOS payload Makefile.inc file to set OPTIONROMS_DEPLOYED to match the VBIOS setting in coreboot. This requires a corresponding change in the arch Makefile.inc to pass the OPTIONROMS_DEPLOYED setting to SeaBIOS make. One limitation of this implementation is that SeaBIOS make assumes that coreboot either set up all option ROMs, or none of them. So if SeaBIOS is used, then PCI_ROM_RUN and VGA_ROM_RUN should both be set or both be unset in coreboot. This change does not check for the condition where only one of the two is set. Change-Id: I13a0b608869b0f980dfb369ffbfbac11b953fe13 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- payloads/external/SeaBIOS/Makefile.inc | 5 +++++ src/arch/x86/Makefile.inc | 2 ++ 2 files changed, 7 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 022e012..a057d4c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -25,6 +25,11 @@ config: checkout echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config +ifneq (,$(filter y,$(CONFIG_PCI_ROM_RUN) $(CONFIG_VGA_ROM_RUN))) + echo "CONFIG_OPTIONROMS_DEPLOYED=y" >> $(OUT)/seabios/.config +else + echo "# CONFIG_OPTIONROMS_DEPLOYED is not set" >> $(OUT)/seabios/.config +endif echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7f1b7b2..28b0ae9 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -408,6 +408,8 @@ seabios: OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_VGA_ROM_RUN=$(CONFIG_VGA_ROM_RUN) \ + CONFIG_PCI_ROM_RUN=$(CONFIG_PCI_ROM_RUN) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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Patch set updated for coreboot: 140cf77 H8QGI / H8SCM / Dinar: Eliminate compiler warnings from build
by Bruce Griffith 25 Jun '13

25 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3527 -gerrit commit 140cf77d187198f1523560f75dc2109793e7e6cc Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jun 24 23:47:29 2013 -0600 H8QGI / H8SCM / Dinar: Eliminate compiler warnings from build Fix a bunch of compiler-generated warning messages. These fixes are mainly copied into AMD Family 15 server boards from similar code in AMD Family 15tn (Trinity) boards. Change-Id: Ic97e906c26c3b91eccd435413908a654294e50b6 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/dinar/sb700_cfg.c | 5 ++++- src/mainboard/amd/dinar/sb700_cfg.h | 6 +++++- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 1 + src/mainboard/supermicro/h8qgi/mptable.c | 4 +++- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 5 ++++- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 6 +++++- src/mainboard/supermicro/h8scm/agesawrapper.c | 12 +++++++++--- src/mainboard/supermicro/h8scm/get_bus_conf.c | 1 + src/mainboard/supermicro/h8scm/mptable.c | 4 +++- src/mainboard/supermicro/h8scm/sb700_cfg.c | 5 ++++- src/mainboard/supermicro/h8scm/sb700_cfg.h | 6 +++++- 11 files changed, 44 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 94e4b40..c9a0949 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 371c7ce..32ac4bd 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /** diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 7682eec..079cafbd 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -23,6 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> +#include <cpu/amd/amdfam15.h> #include "agesawrapper.h" #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 2c112ce..c23b523 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -49,7 +49,9 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); + dword = bus_isa; + mptable_write_buses(mc, NULL, (int*)&dword); + bus_isa = dword; /* * AGESA v5 Apply apic enumeration rules diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c index 54c139a..ff2334f 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.c +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index a3e5a38..4a51ecd 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /** diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 729b669..27e5f46 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -736,9 +736,9 @@ static void agesa_warning(EVENT_PARAMS *event) case HT_EVENT_OPT_REQUIRED_CAP_RETRY: printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %x Link %x Depth %x\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_OPT_REQUIRED_CAP_GEN3: @@ -763,6 +763,8 @@ static void agesa_warning(EVENT_PARAMS *event) (unsigned int)event->DataParam2, (unsigned int)event->DataParam3, (unsigned int)event->DataParam4); + break; + default: break; } @@ -984,6 +986,8 @@ static void agesa_error(EVENT_PARAMS *event) (unsigned int)event->DataParam2, (unsigned int)event->DataParam3, (unsigned int)event->DataParam4); + break; + default: break; } @@ -1022,6 +1026,8 @@ static void agesa_critical(EVENT_PARAMS *event) (unsigned int)event->DataParam2, (unsigned int)event->DataParam3, (unsigned int)event->DataParam4); + break; + default: break; } diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 3dc8471..b529b16 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -23,6 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> +#include <cpu/amd/amdfam15.h> #include "agesawrapper.h" #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 2c112ce..c23b523 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -49,7 +49,9 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); + dword = bus_isa; + mptable_write_buses(mc, NULL, (int*)&dword); + bus_isa = dword; /* * AGESA v5 Apply apic enumeration rules diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.c b/src/mainboard/supermicro/h8scm/sb700_cfg.c index 12169e6..c03a501 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.c +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index eca355f..11d48c2 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /**

1 0

Patch set updated for coreboot: bc9c573 AGESA: Eliminate compiler warnings in AMD F15 AGESA and CIMX wrappers
by Bruce Griffith 25 Jun '13

25 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3526 -gerrit commit bc9c573f40261535e5c2c72f01aec2b1a61233ba Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Fri Jun 21 00:52:54 2013 -0600 AGESA: Eliminate compiler warnings in AMD F15 AGESA and CIMX wrappers The change is mostly type casts to eliminate compile time warnings. Ultimately, this is in preparation for turning on warnings as errors for AMD Family 15 server parts. Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 5 +---- src/southbridge/amd/cimx/sb700/late.c | 2 +- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6134830..4d9cc3c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1060,7 +1060,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); for (j = 0; j <= siblings; j++ ) { - extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + // extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 lapicid_start = 0; /* diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 1ceff80..e7a9ca9 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -32,10 +32,7 @@ // AGESA Types and Definitions // // -#ifndef NULL - #define NULL 0 -#endif - +#include <stddef.h> #define LAST_ENTRY 0xFFFFFFFF #define IOCF8 0xCF8 diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index ede9fb3..b259a7b 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -254,7 +254,7 @@ static void sb700_enable(device_t dev) /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS)); #elif (CONFIG_APIC_ID_OFFSET > 0) /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ setup_ioapic(ioapic_base, 0);

1 0

Patch set updated for coreboot: 3f875c6 AGESA: Eliminate compiler warnings in AMD F15 vendorcode
by Bruce Griffith 25 Jun '13

25 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3525 -gerrit commit 3f875c699bfb2be7af25bcd311343978d1cb2d52 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Fri Jun 21 00:37:09 2013 -0600 AGESA: Eliminate compiler warnings in AMD F15 vendorcode The change is mostly type casts to eliminate compile time warnings Ultimately, this is in preparation for turning on warnings as errors for AMD Family 15 server parts. Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- .../amd/agesa/f15/Include/OptionIdsInstall.h | 12 +- .../amd/agesa/f15/Legacy/Proc/Dispatcher.c | 6 +- .../amd/agesa/f15/Legacy/Proc/hobTransfer.c | 12 +- src/vendorcode/amd/agesa/f15/Lib/amdlib.c | 9 +- src/vendorcode/amd/agesa/f15/Porting.h | 2 +- .../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c | 4 +- .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c | 14 +- .../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c | 4 +- .../amd/agesa/f15/Proc/CPU/cpuPostInit.c | 2 +- .../amd/agesa/f15/Proc/CPU/cpuRegisters.h | 192 +++++++++++---------- .../amd/agesa/f15/Proc/CPU/heapManager.c | 40 ++--- .../amd/agesa/f15/Proc/Common/AmdInitReset.c | 2 +- .../amd/agesa/f15/Proc/Common/S3RestoreState.c | 2 +- .../amd/agesa/f15/Proc/Common/S3SaveState.c | 12 +- .../amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c | 10 +- .../amd/agesa/f15/Proc/Mem/Main/mmflow.c | 2 +- 17 files changed, 170 insertions(+), 157 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h index 16cd68c..a2c0034 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h @@ -74,9 +74,9 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE #if (AGESA_ENTRY_INIT_POST == TRUE) #include <mu.h> CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} + { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} }; #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) #include <mru.h> @@ -94,9 +94,9 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE #endif #else CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"} + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"} }; #endif diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c index 7ad4bb9..ae25a49 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c @@ -105,7 +105,7 @@ AmdAgesaDispatcher ( // 2. Try next dispatcher if possible, and we have not already got status back if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher; + ModuleEntry = (MODULE_ENTRY) (mCpuModuleID.NextBlock->ModuleDispatcher); if (ModuleEntry != NULL) { Status = (*ModuleEntry) (ConfigPtr); } @@ -117,10 +117,10 @@ AmdAgesaDispatcher ( ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; ImageEnd = ImageStart + 4; // Locate/test image base that matches this component - AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, (CHAR8 *) AGESA_ID); + AltImagePtr = LibAmdLocateImage ((VOID *) /* (UINT64) */ImageStart, (VOID *) /* (UINT64) */ImageEnd, 4096, (CHAR8 *) AGESA_ID); if (AltImagePtr != NULL) { //Invoke alternative Image - ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress); + ImageEntry = (IMAGE_ENTRY) (/* (UINT64) */ AltImagePtr + AltImagePtr->EntryPointAddress); Status = (*ImageEntry) (ConfigPtr); } } diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c index f4482ed..b2accb2 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c @@ -209,12 +209,12 @@ CopyHeapToTempRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr; HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress; + BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress; HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); @@ -308,8 +308,8 @@ CopyHeapToMainRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr; + BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr; HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); @@ -367,7 +367,7 @@ CopyHeapToMainRamAtPost ( HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; } // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { + if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) { // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); @@ -376,7 +376,7 @@ CopyHeapToMainRamAtPost ( HeapRamVariableMtrr--) { LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && + if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { break; } diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c index ca268ee..e51a971 100644 --- a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c @@ -285,6 +285,7 @@ LibAmdReadCpuReg ( break; default: *Value = -1; + break; } } VOID @@ -313,7 +314,7 @@ LibAmdWriteCpuReg ( __writedr (7, Value); break; default: - ; + break; } } VOID @@ -503,6 +504,7 @@ LibAmdIoRead ( break; default: ASSERT (FALSE); + break; } } @@ -540,6 +542,7 @@ LibAmdIoWrite ( break; default: ASSERT (FALSE); + break; } } @@ -640,6 +643,7 @@ LibAmdMemRead ( break; default: ASSERT (FALSE); + break; } } @@ -678,6 +682,7 @@ LibAmdMemWrite ( break; default: ASSERT (FALSE); + break; } } /*---------------------------------------------------------------------------------------*/ @@ -1293,6 +1298,7 @@ LibAmdGetDataFromPtr ( break; default: IDS_ERROR_TRAP; + break; } } @@ -1333,6 +1339,7 @@ LibAmdAccessWidth ( default: Width = 0; IDS_ERROR_TRAP; + break; } return Width; } diff --git a/src/vendorcode/amd/agesa/f15/Porting.h b/src/vendorcode/amd/agesa/f15/Porting.h index 4cd8d1c..776cddc 100644 --- a/src/vendorcode/amd/agesa/f15/Porting.h +++ b/src/vendorcode/amd/agesa/f15/Porting.h @@ -233,7 +233,7 @@ typedef signed char INT8; typedef signed short INT16; typedef signed int INT32; - typedef signed char CHAR8; + typedef char CHAR8; typedef unsigned char UINT8; typedef unsigned short UINT16; typedef unsigned int UINT32; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c index 2f7a061..afcea1d 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c @@ -806,7 +806,7 @@ F15OrEarlySamplesLoadMicrocode ( // Load microcode patch into CPU GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64)(intptr_t) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; // Check if this CPU is OR-B0, expected fix in OR-B1 if ((LogicalId.Revision & AMD_F15_OR_B0) != 0) { diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c index 207d444..c055f5b 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c @@ -216,7 +216,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask; - StartAddress = (UINT64) DeviceList; + StartAddress = (UINT64)(intptr_t)DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; @@ -280,7 +280,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64) OrMask; + EndAddress = (UINT64)(intptr_t)OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); } diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c index bded7e7..f6d452e 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c @@ -68,11 +68,11 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------------------- */ /* ApFlags bits */ -#define AP_TASK_HAS_INPUT 0x00000001 -#define AP_TASK_HAS_OUTPUT 0x00000002 -#define AP_RETURN_PARAMS 0x00000004 -#define AP_END_AT_HLT 0x00000008 -#define AP_PASS_EARLY_PARAMS 0x00000010 +#define AP_TASK_HAS_INPUT 0x00000001ul +#define AP_TASK_HAS_OUTPUT 0x00000002ul +#define AP_RETURN_PARAMS 0x00000004ul +#define AP_END_AT_HLT 0x00000008ul +#define AP_PASS_EARLY_PARAMS 0x00000010ul #define XFER_ELEMENT_SIZE sizeof (UINT32) @@ -813,7 +813,7 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } - HandlerOffset = (UINT64) NmiHandler; + HandlerOffset = (UINT64) (UINTN) NmiHandler; NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); @@ -822,7 +822,7 @@ ApUtilSetupIdtForHlt ( NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); NmiIdtDescPtr->Rsvd64 = 0; IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2); + IdtInfo.Base = (UINT64) (UINTN) NmiIdtDescPtr - (DescSize * 2); IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader); SetIdtr (&IdtInfo , StdHeader); } diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c index 69d198b..d76a372 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c @@ -80,6 +80,7 @@ typedef union { *---------------------------------------------------------------------------------------- */ BOOLEAN +STATIC LoadMicrocode ( IN MICROCODE_PATCH *MicrocodePatchPtr, IN OUT AMD_CONFIG_PARAMS *StdHeader @@ -174,6 +175,7 @@ LoadMicrocodePatch ( * */ BOOLEAN +STATIC LoadMicrocode ( IN MICROCODE_PATCH *MicrocodePatchPtr, IN OUT AMD_CONFIG_PARAMS *StdHeader @@ -183,7 +185,7 @@ LoadMicrocode ( PATCH_LOADER PatchLoaderMsr; // Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64) (UINTN) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c index 901eb80..466e0c4 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c @@ -206,7 +206,7 @@ GetPstateGatherDataAddressAtPost ( AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - *Ptr = (UINT64 *)(AddressValue); + *Ptr = (UINT64 *)(intptr_t)(AddressValue); return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h index e81ded3..e0959fc 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h @@ -129,10 +129,10 @@ #define BIT63 0x8000000000000000ull /// CPUID related registers -#define AMD_CPUID_FMF 0x80000001 // Family Model Features information -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID -#define AMD_CPUID_TLB_L1Cache 0x80000005 -#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006 +#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID +#define AMD_CPUID_TLB_L1Cache 0x80000005ul +#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul #define CPUID_ASSOCIATIVITY_2_WAY 0x02 #define CPUID_ASSOCIATIVITY_4_WAY 0x04 #define CPUID_ASSOCIATIVITY_8_WAY 0x06 @@ -142,10 +142,10 @@ #define CPUID_ASSOCIATIVITY_64_WAY 0x0C #define CPUID_ASSOCIATIVITY_96_WAY 0x0D #define CPUID_ASSOCIATIVITY_128_WAY 0x0E -#define AMD_CPUID_APM 0x80000007 +#define AMD_CPUID_APM 0x80000007ul #define LOCAL_APIC_ID 24 #define LOGICAL_PROCESSOR_COUNT 16 -#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008 // Address Size, Physical Core Count +#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count /// CPU Logical ID Transfer typedef struct { @@ -161,20 +161,20 @@ typedef struct { // MSRs // ------------------------ -#define MCG_CTL_P 0x00000100 // bit 8 for MCG_CTL_P under MSRR -#define MSR_MCG_CAP 0x00000179 -#define MSR_MC0_CTL 0x00000400 +#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR +#define MSR_MCG_CAP 0x00000179ul +#define MSR_MC0_CTL 0x00000400ul -#define MSR_APIC_BAR 0x0000001B -#define MSR_PATCH_LEVEL 0x0000008B +#define MSR_APIC_BAR 0x0000001Bul +#define MSR_PATCH_LEVEL 0x0000008Bul -#define CPUID_LONG_MODE_ADDR 0x80000008 -#define AMD_CPUID_FMF 0x80000001 +#define CPUID_LONG_MODE_ADDR 0x80000008ul +#define AMD_CPUID_FMF 0x80000001ul -#define MSR_EXTENDED_FEATURE_EN 0xC0000080 -#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408 -#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409 -#define MSR_PATCH_LOADER 0xC0010020 +#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul +#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul +#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul +#define MSR_PATCH_LOADER 0xC0010020ul /// Patch Loader Register typedef struct { @@ -182,49 +182,49 @@ typedef struct { UINT64 SBZ:32; ///< Should be zero } PATCH_LOADER_MSR; -#define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared -#define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared -#define MSR_MC0_CTL_MASK 0xC0010044 // MC0 Control Mask -#define MSR_MC1_CTL_MASK 0xC0010045 // MC1 Control Mask -#define MSR_MC2_CTL_MASK 0xC0010046 // MC2 Control Mask -#define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask - -#define MSR_CPUID_FEATS 0xC0011004 // CPUID Features -#define MSR_CPUID_EXT_FEATS 0xC0011005 // CPUID Extended Features -#define MSR_HWCR 0xC0010015 -#define MSR_NB_CFG 0xC001001F // NB Config -#define ENABLE_CF8_EXT_CFG 0x00004000 // [46] -#define INIT_APIC_CPUID_LO 0x00400000 // [54] -#define MSR_LS_CFG 0xC0011020 -#define MSR_IC_CFG 0xC0011021 // ICache Config - F15 Shared -#define MSR_DC_CFG 0xC0011022 -#define MSR_ME_CFG 0xC0011029 -#define MSR_BU_CFG 0xC0011023 -#define MSR_CU_CFG 0xC0011023 // F15 Shared -#define MSR_DE_CFG 0xC0011029 // F15 Shared -#define MSR_BU_CFG2 0xC001102A -#define MSR_CU_CFG2 0xC001102A // F15 Shared -#define MSR_BU_CFG3 0xC001102B -#define MSR_CU_CFG3 0xC001102B // F15 Shared -#define MSR_LS_CFG2 0xC001102D -#define MSR_IBS_OP_DATA3 0xC0011037 -#define MSR_C001_1070 0xC0011070 // F15 Shared - - -#define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register -#define MSR_CPUID_NAME_STRING1 0xC0010031 -#define MSR_CPUID_NAME_STRING2 0XC0010032 -#define MSR_CPUID_NAME_STRING3 0xC0010033 -#define MSR_CPUID_NAME_STRING4 0xC0010034 -#define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register -#define MSR_MMIO_Cfg_Base 0xC0010058 // MMIO Configuration Base Address Register -#define MSR_BIST 0xC0010060 // BIST Results register -#define MSR_OSVW_ID_Length 0xC0010140 -#define MSR_OSVW_Status 0xC0010141 -#define MSR_PERF_CONTROL3 0xC0010003 // Perfromance control register number 3 -#define MSR_PERF_COUNTER3 0xC0010007 // Performance counter register number 3 -#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFF // Mask of the Performance control Reserve bits -#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2 // Configure the controller to capture the +#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared +#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared +#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask +#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask +#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask +#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask + +#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features +#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features +#define MSR_HWCR 0xC0010015ul +#define MSR_NB_CFG 0xC001001Ful // NB Config +#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46] +#define INIT_APIC_CPUID_LO 0x00400000ul // [54] +#define MSR_LS_CFG 0xC0011020ul +#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared +#define MSR_DC_CFG 0xC0011022ul +#define MSR_ME_CFG 0xC0011029ul +#define MSR_BU_CFG 0xC0011023ul +#define MSR_CU_CFG 0xC0011023ul // F15 Shared +#define MSR_DE_CFG 0xC0011029ul // F15 Shared +#define MSR_BU_CFG2 0xC001102Aul +#define MSR_CU_CFG2 0xC001102Aul // F15 Shared +#define MSR_BU_CFG3 0xC001102Bul +#define MSR_CU_CFG3 0xC001102Bul // F15 Shared +#define MSR_LS_CFG2 0xC001102Dul +#define MSR_IBS_OP_DATA3 0xC0011037ul +#define MSR_C001_1070 0xC0011070ul // F15 Shared + + +#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register +#define MSR_CPUID_NAME_STRING1 0xC0010031ul +#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING3 0xC0010033ul +#define MSR_CPUID_NAME_STRING4 0xC0010034ul +#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register +#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register +#define MSR_BIST 0xC0010060ul // BIST Results register +#define MSR_OSVW_ID_Length 0xC0010140ul +#define MSR_OSVW_Status 0xC0010141ul +#define MSR_PERF_CONTROL3 0xC0010003ul // Perfromance control register number 3 +#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3 +#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits +#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ull // Configure the controller to capture the // CAR Corruption // FUNC_0 registers // ---------------- @@ -243,26 +243,26 @@ typedef struct { #define HT_INIT_BIOS_RST_DET_2 BIT10 #define HT_INIT_BIOS_RST_DET BIT9 | BIT10 #define HT_TRANS_CTRL 0x68 -#define HT_TRANS_CTRL_CPU1_EN 0x00000020 // [5] = CPU1 Enable +#define HT_TRANS_CTRL_CPU1_EN 0x00000020ul // [5] = CPU1 Enable #define HT_LINK_CONTROL_0 0x84 #define HT_LINK_FREQ_0 0x88 // Link HT Frequency #define EXTENDED_NODE_ID 0x160 #define ECS_HT_TRANS_CTRL 0x168 -#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001 // [0] = CPU2 Enable -#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002 // [1] = CPU3 Enable -#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004 // [2] = CPU4 Enable -#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008 // [3] = CPU5 Enable +#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001ul // [0] = CPU2 Enable +#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002ul // [1] = CPU3 Enable +#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004ul // [2] = CPU4 Enable +#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008ul // [3] = CPU5 Enable #define CORE_CTRL 0x1DC -#define CORE_CTRL_CORE1_EN 0x00000002 -#define CORE_CTRL_CORE2_EN 0x00000004 -#define CORE_CTRL_CORE3_EN 0x00000008 -#define CORE_CTRL_CORE4_EN 0x00000010 -#define CORE_CTRL_CORE5_EN 0x00000020 -#define CORE_CTRL_CORE6_EN 0x00000040 -#define CORE_CTRL_CORE7_EN 0x00000080 -#define CORE_CTRL_CORE8_EN 0x00000100 -#define CORE_CTRL_CORE9_EN 0x00000200 +#define CORE_CTRL_CORE1_EN 0x00000002ul +#define CORE_CTRL_CORE2_EN 0x00000004ul +#define CORE_CTRL_CORE3_EN 0x00000008ul +#define CORE_CTRL_CORE4_EN 0x00000010ul +#define CORE_CTRL_CORE5_EN 0x00000020ul +#define CORE_CTRL_CORE6_EN 0x00000040ul +#define CORE_CTRL_CORE7_EN 0x00000080ul +#define CORE_CTRL_CORE8_EN 0x00000100ul +#define CORE_CTRL_CORE9_EN 0x00000200ul // FUNC_3 registers // ---------------- @@ -284,11 +284,11 @@ typedef struct { #define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 #define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 -#define HTPHY_OFFSET_MASK 0xE00001FF -#define HTPHY_WRITE_CMD 0x40000000 -#define HTPHY_IS_COMPLETE_MASK 0x80000000 -#define HTPHY_DIRECT_MAP 0x20000000 -#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFF +#define HTPHY_OFFSET_MASK 0xE00001FFul +#define HTPHY_WRITE_CMD 0x40000000ul +#define HTPHY_IS_COMPLETE_MASK 0x80000000ul +#define HTPHY_DIRECT_MAP 0x20000000ul +#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFFul // FUNC_5 registers // ---------------- @@ -338,10 +338,12 @@ typedef struct { #define KM_SOCKET_C2012 5 #define SOCKET_IGNORE 0xF -#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000 -#define APIC_EXT_BRDCST_MASK 0x000E0000 -#define APIC_ENABLE_BIT 0x00000800 -#define LOCAL_APIC_ADDR 0xFEE00000 +#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull +#define APIC_EXT_BRDCST_MASK 0x000E0000ul +#define APIC_ENABLE_BIT 0x00000800ul +#ifndef LOCAL_APIC_ADDR +#define LOCAL_APIC_ADDR 0xFEE00000ul +#endif #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 @@ -357,20 +359,20 @@ typedef struct { * Default definitions *------------------------- */ -#define DOWNCORE_MASK_SINGLE 0xFFFFFFFE -#define DOWNCORE_MASK_DUAL 0xFFFFFFFC -#define DOWNCORE_MASK_TRI 0xFFFFFFF8 -#define DOWNCORE_MASK_FOUR 0xFFFFFFF0 -#define DOWNCORE_MASK_FIVE 0xFFFFFFE0 -#define DOWNCORE_MASK_SIX 0xFFFFFFC0 -#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFA -#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEA -#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAA +#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul +#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul +#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul +#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul +#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul +#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul +#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul +#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul +#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul #define DELIVERY_STATUS BIT13 -#define REMOTE_READ_STAT_MASK 0x00030000 -#define REMOTE_DELIVERY_PENDING 0x00010000 -#define REMOTE_DELIVERY_DONE 0x00020000 +#define REMOTE_READ_STAT_MASK 0x00030000ul +#define REMOTE_DELIVERY_PENDING 0x00010000ul +#define REMOTE_DELIVERY_DONE 0x00020000ul /* * -------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c index a02a6a2..f42c35d 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c @@ -156,13 +156,13 @@ HeapManagerInit ( GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr; + HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; // Check whether the heap manager is already initialized LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { + if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { // This is not a bug, there are multiple premem basic entry points, // and each will call heap init to make sure create struct will succeed. @@ -178,7 +178,7 @@ HeapManagerInit ( } // Set variable MTRR base and mask - MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); + MsrData = ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; MsrData |= 0x06; @@ -320,20 +320,20 @@ HeapAllocateBuffer ( AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL; // Get base address - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; } // Allocate @@ -465,20 +465,20 @@ HeapDeallocateBuffer ( ASSERT (StdHeader != NULL); HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; } OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -594,20 +594,20 @@ HeapLocateBuffer ( ASSERT (StdHeader != NULL); HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; } OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); @@ -698,29 +698,29 @@ HeapGetBaseAddress ( // Firstly, we try to see if heap is in cache BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { // Secondly, we try to see if heap is in temp memory BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // Thirdly, we try to see if heap in main memory // by locating with external buffer manager (IBV) AgesaBuffer.StdHeader = *StdHeader; AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) BaseAddress; + BaseAddress = (UINT64) (UINTN) AgesaBuffer.BufferPointer; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // No valid heap signature ever found, return a NULL pointer - BaseAddress = 0; + BaseAddress = (UINT64) (UINTN) NULL; } } else { // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = 0; + BaseAddress = (UINT64) (UINTN) NULL; } } } @@ -762,7 +762,7 @@ DeleteFreeSpaceNode ( BUFFER_NODE *PreviousFreeSpaceNode; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -821,7 +821,7 @@ InsertFreeSpaceNode ( BUFFER_NODE *PreviousFreeSpaceNode; BUFFER_NODE *InsertedFreeSpaceNode; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c index 7a2d1a1..7013f67 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c @@ -157,7 +157,7 @@ AmdInitReset ( IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString); AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); ASSERT (ResetParams != NULL); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c index 7b9a17d..5f00ec5 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c @@ -166,7 +166,7 @@ S3RestoreStateFromTable ( PCI_ADDR PciAddress; UINTN Index; S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore: Address: 0x%08x\n", (intptr_t)((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { switch (*(UINT16 *) S3SaveTableRecordPtr) { case SAVE_STATE_IO_WRITE_OPCODE: diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c index 4f93379..e4bd926 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c @@ -269,7 +269,7 @@ S3SaveStateSaveWriteOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); IDS_HDT_CONSOLE (S3_TRACE, "\n"); ); @@ -334,7 +334,7 @@ S3SaveStateSaveReadWriteOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -410,7 +410,7 @@ S3SaveStateSavePollOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -482,7 +482,7 @@ S3SaveStateSaveInfoOp ( SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->Length = InformationLength; S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", (CHAR8 *)Information); ); LibAmdMemCopy ( (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), @@ -598,6 +598,7 @@ S3SaveDebugOpcodeString ( return (CHAR8*)"DISPATCH"; default: IDS_ERROR_TRAP; + break; } return (CHAR8*)"!!! Unrecognize opcode !!!"; } @@ -640,10 +641,11 @@ S3SaveDebugPrintHexArray ( break; case AccessWidth64: case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index))[1], ((UINT32*)((UINT64*)Array + Index))[0]); break; default: IDS_ERROR_TRAP; + break; } if (Index < (Count - 1)) { IDS_HDT_CONSOLE (S3_TRACE, ", "); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c index e1218d4..3465825 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c @@ -263,30 +263,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINTN) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c index 3129450..f202cf1 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c @@ -378,7 +378,7 @@ MemSPDDataProcess ( AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (intptr_t)SpdParam.Buffer); } else { DimmSPDPtr->DimmPresent = FALSE; }

1 0

Patch set updated for coreboot: 7470a92 libpayload: Make lpgcc wrapper usable for in-tree builds
by Patrick Georgi 25 Jun '13

25 Jun '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3530 -gerrit commit 7470a92753d91074ed9ba43dcd51d0e7a78a06c0 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 21 14:33:25 2013 +0100 libpayload: Make lpgcc wrapper usable for in-tree builds Teach lpgcc to look in the in-coreboot tree directory structure, too. Change-Id: I3809456d072ce2f91542b0edb3fd39f536298cc2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/bin/lp.functions | 4 +- payloads/libpayload/bin/lpgcc | 71 ++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 25 deletions(-) diff --git a/payloads/libpayload/bin/lp.functions b/payloads/libpayload/bin/lp.functions index 21b6e91..31f005d 100644 --- a/payloads/libpayload/bin/lp.functions +++ b/payloads/libpayload/bin/lp.functions @@ -49,11 +49,13 @@ fi if [ -f $BASE/../lib/libpayload.a ]; then _LIBDIR=$BASE/../lib +elif [ -f $BASE/../build/libpayload.a ]; then + _LIBDIR=$BASE/../build else _LIBDIR=$LIBPAYLOAD_PREFIX/lib fi -if [ -d $BASE/../include/ ]; then +if [ -d $BASE/../include ]; then _INCDIR=$BASE/../include else _INCDIR=$LIBPAYLOAD_PREFIX/include diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 06b9021..f0b2417 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -59,9 +59,42 @@ BASE=`dirname $0` . $BASE/lp.functions # include libpayload config -. $BASE/../libpayload.config +if [ -f $BASE/../libpayload.config ]; then + . $BASE/../libpayload.config +elif [ -f $BASE/../.config ]; then + . $BASE/../.config +else + echo "Can't find config" + exit 1 +fi + +if [ "$CONFIG_ARCH_ARMV7" = "y" ]; then + _ARCHINCDIR=$_INCDIR/armv7 + _ARCHLIBDIR=$_LIBDIR/armv7 + _ARCHEXTRA="" + _ARCH=armv7 +fi + +if [ "$CONFIG_ARCH_POWERPC" = "y" ]; then + _ARCHINCDIR=$_INCDIR/powerpc + _ARCHLIBDIR=$_LIBDIR/powerpc + _ARCHEXTRA="" + _ARCH=powerpc +fi + +if [ "$CONFIG_ARCH_X86" = "y" ]; then + _ARCHINCDIR=$_INCDIR/x86 + _ARCHLIBDIR=$_LIBDIR/x86 + _ARCHEXTRA="-m32 " + _ARCH=x86 +fi -_LDSCRIPT="-Wl,-T,$_LIBDIR/libpayload.ldscript" +if [ -f $_LIBDIR/libpayload.ldscript ]; then + _LDDIR=$_LIBDIR +elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then + _LDDIR=$BASE/../arch/$_ARCH +fi +_LDSCRIPT="-Wl,-T,$_LDDIR/libpayload.ldscript" trygccoption() { $DEFAULT_CC $1 -S -xc /dev/null -o /dev/null &> /dev/null @@ -107,25 +140,7 @@ while [ $# -gt 0 ]; do shift done -if [ "$CONFIG_ARCH_ARMV7" = "y" ]; then - _ARCHINCDIR=$_INCDIR/armv7 - _ARCHLIBDIR=$_LIBDIR/armv7 - _ARCHEXTRA="" -fi - -if [ "$CONFIG_ARCH_POWERPC" = "y" ]; then - _ARCHINCDIR=$_INCDIR/powerpc - _ARCHLIBDIR=$_LIBDIR/powerpc - _ARCHEXTRA="" -fi - -if [ "$CONFIG_ARCH_X86" = "y" ]; then - _ARCHINCDIR=$_INCDIR/x86 - _ARCHLIBDIR=$_LIBDIR/x86 - _ARCHEXTRA="-m32 " -fi - -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" # Check for the -fno-stack-protector silliness @@ -134,7 +149,7 @@ trygccoption -fno-stack-protector _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib $_LDSCRIPT -static" +_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then @@ -144,8 +159,16 @@ if [ $DOLINK -eq 0 ]; then $DEFAULT_CC $_CFLAGS $CMDLINE else _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` + if [ -f $_ARCHLIBDIR/head.o ]; then + HEAD_O=$_ARCHLIBDIR/head.o + elif [ -f $BASE/../build/head.o ]; then + HEAD_O=$BASE/../build/head.o + else + echo "Could not find head.o" + exit 1 + fi if [ $DEBUGME -eq 1 ]; then - echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE -lpayload $_LIBGCC" + echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $HEAD_O $CMDLINE -lpayload $_LIBGCC" fi # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it @@ -153,5 +176,5 @@ else # header to be placed below 0x2000 in the resulting image. See: # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format… - $DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE -lpayload $_LIBGCC + $DEFAULT_CC $_CFLAGS $_LDFLAGS $HEAD_O $CMDLINE -lpayload $_LIBGCC fi

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Patch merged into coreboot/master: 99fd30e sandybridge: Make inclusion of me.bin optional
by gerrit＠coreboot.org 25 Jun '13

25 Jun '13

the following patch was just integrated into master: commit 99fd30e486146d6ad83cec5a56be8268cf0a645a Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jun 19 15:57:34 2013 +0200 sandybridge: Make inclusion of me.bin optional Current build configuration always wants to include an Intel Management Engine firmware (me.bin) on Sandy Bridge systems. However, we can have a working coreboot without it, as long as the factory delivered ME firmware is kept untouched in the flash ROM. So let the user decide if a ME firmware will be included in the build. Change-Id: I9a1cc29d4940ba22355eb9e653606e436f07e04c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3522 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3522 for details. -gerrit

1 0

New patch to review for coreboot: 2e9d0b3 libpayload: Make lpgcc wrapper usable for in-tree builds
by Patrick Georgi 25 Jun '13

25 Jun '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3530 -gerrit commit 2e9d0b340b671cabd2684d95b2edfa5d6cb1bebf Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 21 14:33:25 2013 +0100 libpayload: Make lpgcc wrapper usable for in-tree builds Teach lpgcc to look in the in-coreboot tree directory structure, too. Change-Id: I3809456d072ce2f91542b0edb3fd39f536298cc2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/bin/lp.functions | 4 +- payloads/libpayload/bin/lpgcc | 71 ++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 25 deletions(-) diff --git a/payloads/libpayload/bin/lp.functions b/payloads/libpayload/bin/lp.functions index 21b6e91..31f005d 100644 --- a/payloads/libpayload/bin/lp.functions +++ b/payloads/libpayload/bin/lp.functions @@ -49,11 +49,13 @@ fi if [ -f $BASE/../lib/libpayload.a ]; then _LIBDIR=$BASE/../lib +elif [ -f $BASE/../build/libpayload.a ]; then + _LIBDIR=$BASE/../build else _LIBDIR=$LIBPAYLOAD_PREFIX/lib fi -if [ -d $BASE/../include/ ]; then +if [ -d $BASE/../include ]; then _INCDIR=$BASE/../include else _INCDIR=$LIBPAYLOAD_PREFIX/include diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 06b9021..f0b2417 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -59,9 +59,42 @@ BASE=`dirname $0` . $BASE/lp.functions # include libpayload config -. $BASE/../libpayload.config +if [ -f $BASE/../libpayload.config ]; then + . $BASE/../libpayload.config +elif [ -f $BASE/../.config ]; then + . $BASE/../.config +else + echo "Can't find config" + exit 1 +fi + +if [ "$CONFIG_ARCH_ARMV7" = "y" ]; then + _ARCHINCDIR=$_INCDIR/armv7 + _ARCHLIBDIR=$_LIBDIR/armv7 + _ARCHEXTRA="" + _ARCH=armv7 +fi + +if [ "$CONFIG_ARCH_POWERPC" = "y" ]; then + _ARCHINCDIR=$_INCDIR/powerpc + _ARCHLIBDIR=$_LIBDIR/powerpc + _ARCHEXTRA="" + _ARCH=powerpc +fi + +if [ "$CONFIG_ARCH_X86" = "y" ]; then + _ARCHINCDIR=$_INCDIR/x86 + _ARCHLIBDIR=$_LIBDIR/x86 + _ARCHEXTRA="-m32 " + _ARCH=x86 +fi -_LDSCRIPT="-Wl,-T,$_LIBDIR/libpayload.ldscript" +if [ -f $_LIBDIR/libpayload.ldscript ]; then + _LDDIR=$_LIBDIR +elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then + _LDDIR=$BASE/../arch/$_ARCH +fi +_LDSCRIPT="-Wl,-T,$_LDDIR/libpayload.ldscript" trygccoption() { $DEFAULT_CC $1 -S -xc /dev/null -o /dev/null &> /dev/null @@ -107,25 +140,7 @@ while [ $# -gt 0 ]; do shift done -if [ "$CONFIG_ARCH_ARMV7" = "y" ]; then - _ARCHINCDIR=$_INCDIR/armv7 - _ARCHLIBDIR=$_LIBDIR/armv7 - _ARCHEXTRA="" -fi - -if [ "$CONFIG_ARCH_POWERPC" = "y" ]; then - _ARCHINCDIR=$_INCDIR/powerpc - _ARCHLIBDIR=$_LIBDIR/powerpc - _ARCHEXTRA="" -fi - -if [ "$CONFIG_ARCH_X86" = "y" ]; then - _ARCHINCDIR=$_INCDIR/x86 - _ARCHLIBDIR=$_LIBDIR/x86 - _ARCHEXTRA="-m32 " -fi - -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" # Check for the -fno-stack-protector silliness @@ -134,7 +149,7 @@ trygccoption -fno-stack-protector _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib $_LDSCRIPT -static" +_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then @@ -144,8 +159,16 @@ if [ $DOLINK -eq 0 ]; then $DEFAULT_CC $_CFLAGS $CMDLINE else _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` + if [ -f $_ARCHLIBDIR/head.o ]; then + HEAD_O=$_ARCHLIBDIR/head.o + elif [ -f $BASE/../build/head.o ]; then + HEAD_O=$BASE/../build/head.o + else + echo "Could not find head.o" + exit 1 + fi if [ $DEBUGME -eq 1 ]; then - echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE -lpayload $_LIBGCC" + echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $HEAD_O $CMDLINE -lpayload $_LIBGCC" fi # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it @@ -153,5 +176,5 @@ else # header to be placed below 0x2000 in the resulting image. See: # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format… - $DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE -lpayload $_LIBGCC + $DEFAULT_CC $_CFLAGS $_LDFLAGS $HEAD_O $CMDLINE -lpayload $_LIBGCC fi

1 0

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coreboot-gerrit June 2013