Change in flashrom[master]: chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support

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Edward O'Callaghan (Code Review)

2 Nov 2020 2 Nov '20

4:58 a.m.

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support ......................................................................

chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support

BUG=none BRANCH=none TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/47090/1

diff --git a/chipset_enable.c b/chipset_enable.c index a0ac6c1..c664918 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1839,6 +1839,9 @@ {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e41, B_FS, OK, "Intel", "Desktop Full", enable_flash_pch6}, + {0x8086, 0x1e42, B_FS, OK, "Intel", "Mobile Full", enable_flash_pch6}, + {0x8086, 0x1e43, B_FS, OK, "Intel", "Mobile SFF", enable_flash_pch6}, {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7},

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Angel Pons (Code Review)

2 Nov 2 Nov

9:24 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch6 pid=0x1e4{1,2,3} support ......................................................................

Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/c/flashrom/+/47090/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/flashrom/+/47090/1//COMMIT_MSG@7 PS1, Line 7: pid did (Device ID)

https://review.coreboot.org/c/flashrom/+/47090/1/chipset_enable.c File chipset_enable.c:

https://review.coreboot.org/c/flashrom/+/47090/1/chipset_enable.c@1842 PS1, Line 1842: OK These should be `DEP` like the other PCHs are

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 02 Nov 2020 09:24:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

13 Nov 13 Nov

8:10 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

Hello build bot (Jenkins), Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/47090

to look at the new patch set (#2).

Change subject: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support ......................................................................

chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

BUG=none BRANCH=none TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/47090/2

Edward O'Callaghan (Code Review)

8:11 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support ......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/flashrom/+/47090/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/flashrom/+/47090/1//COMMIT_MSG@7 PS1, Line 7: pid

...

did (Device ID)

Done

https://review.coreboot.org/c/flashrom/+/47090/1/chipset_enable.c File chipset_enable.c:

https://review.coreboot.org/c/flashrom/+/47090/1/chipset_enable.c@1842 PS1, Line 1842: OK

...

These should be `DEP` like the other PCHs are

Done

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 13 Nov 2020 08:11:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Sam McNally (Code Review)

8:36 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support ......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c File chipset_enable.c:

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c@1841 PS2, Line 1841: enable_flash_pch6 enable_flash_pch7

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c@1841 PS2, Line 1841: Desktop Full It would be nice to use "Desktop Sample", "Mobile Sample" and "SFF Sample" to match coreboot: https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/bd82x...

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 13 Nov 2020 08:36:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

8:40 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

Hello Sam McNally, build bot (Jenkins), Stefan Reinauer, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/47090

to look at the new patch set (#3).

Change subject: chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support ......................................................................

chipset_enable.c: Add Intel pch6 did=0x1e4{1,2,3} support

Modified to be pch7 over pch6 as per-coreboot and review comments.

BUG=none BRANCH=none TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/47090/3

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Edward O'Callaghan (Code Review)

8:42 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Hello Sam McNally, build bot (Jenkins), Stefan Reinauer, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/47090

to look at the new patch set (#4).

Change subject: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support ......................................................................

chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Modified to be pch7 over pch6 as per-coreboot and review comments.

BUG=none BRANCH=none TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/47090/4

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Sam McNally (Code Review)

8:48 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support ......................................................................

Patch Set 4: Code-Review+2

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 13 Nov 2020 08:48:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

11:45 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support ......................................................................

Patch Set 4: Code-Review+2

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 13 Nov 2020 11:45:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

14 Nov 14 Nov

3:26 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c File chipset_enable.c:

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c@1841 PS2, Line 1841: enable_flash_pch6

...

enable_flash_pch7

Done

https://review.coreboot.org/c/flashrom/+/47090/2/chipset_enable.c@1841 PS2, Line 1841: Desktop Full

...

It would be nice to use "Desktop Sample", "Mobile Sample" and "SFF Sample" to match coreboot: […]

Done

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sat, 14 Nov 2020 03:26:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sam McNally sammc@google.com Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

3:27 a.m.

New subject: Change in flashrom[master]: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/47090 )

Change subject: chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support ......................................................................

chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support

Modified to be pch7 over pch6 as per-coreboot and review comments.

BUG=none BRANCH=none TEST=none

Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Reviewed-by: Sam McNally sammc@google.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-)

Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Sam McNally: Looks good to me, approved

diff --git a/chipset_enable.c b/chipset_enable.c index 4273478..04ff9d8 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1838,6 +1838,9 @@ {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e41, B_FS, DEP, "Intel", "Desktop Sample", enable_flash_pch7}, + {0x8086, 0x1e42, B_FS, DEP, "Intel", "Mobile Sample", enable_flash_pch7}, + {0x8086, 0x1e43, B_FS, DEP, "Intel", "SFF Sample", enable_flash_pch7}, {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7},

-- To view, visit https://review.coreboot.org/c/flashrom/+/47090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Gerrit-Change-Number: 47090 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

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Angel Pons (Code Review)
Edward O'Callaghan (Code Review)
Sam McNally (Code Review)