Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47089 )
Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support ......................................................................
chipset_enable.c: Add MCP61 pid=0x03e2 support
BUG=none BRANCH=none TEST=none
Change-Id: Id1cb8b77b80c6291886238f91ffb7bf75e5750b3 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/47089/1
diff --git a/chipset_enable.c b/chipset_enable.c index 4273478..a0ac6c1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1774,6 +1774,7 @@ {0x10de, 0x0367, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ {0x10de, 0x03e0, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e1, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e2, B_LS, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e3, B_LS, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x0440, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, {0x10de, 0x0441, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47089 )
Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG@8 PS1, Line 8: Where does the ID come from?
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47089 )
Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG@8 PS1, Line 8:
Where does the ID come from?
According to https://envytools.readthedocs.io/en/latest/hw/pciid.html this is the memory controller PCI ID, not the LPC PCI ID like for all other devices in this list. Is this done on purpose?
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47089 )
Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG@8 PS1, Line 8:
According to https://envytools.readthedocs.io/en/latest/hw/pciid. […]
After much investigation,
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+...
Edward O'Callaghan has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/47089 )
Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support ......................................................................
Abandoned
turns out this was later removed upstream
-
Angel Pons (Code Review) -
Edward O'Callaghan (Code Review)
-
Stefan Reinauer (Code Review)