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Change subject: doc: Release notes for version 1.4.0
......................................................................
Patch Set 2:
(7 comments)
Patchset:
PS2:
Peter thank you so much, your suggestions made this doc so much better!
File doc/release_notes/v_1_4.rst:
https://review.coreboot.org/c/flashrom/+/83359/comment/5e00a6fc_fc30bc69?us… :
PS1, Line 5: Release notes for flashrom version 1.4.0.
> It seems nice to include a little intro paragraph here, acknowledging contributors and providing a l […]
This is a great idea! How could I forgot :(
I added a paragraph, with few changes: 400+ and 70+ instead of exact numbers, to count all possible fixed in rc.
Also I am not entirely sure how to count months: 1.3 got out in Feb 2023, but it was made based on a branch which diverged in early Nov 2022. And during those 3.5 months active development continued, but except of few small fixed, not included in 1.3.
There is no easy way to say this in short, so I settled on "in the 18 months since version 1.3.0 was branched" which seems close enough to reality.
We won't have this problem again :)
https://review.coreboot.org/c/flashrom/+/83359/comment/99353e55_8aad7e3a?us… :
PS1, Line 10: Fix AMD programmer (sb600spi.c) for Promontory and chips >16MB size
> I see this is the title of the issue, but starting a known issue with "Fix" seems confusing. […]
This is great summary!
https://review.coreboot.org/c/flashrom/+/83359/comment/faa02cde_16857b71?us… :
PS1, Line 29:
: * Calibration loop is not used anymore, except for DOS
: * Removed unconditional 1 second delay for SPI chips
: * Lower the sleep vs delay threshold to 0.1 seconds
: * Tree-wide refactorings around programmer_delay and internal_delay
> This is technically all true, but I think it should be rearranged to highlight the parts that users […]
Done
https://review.coreboot.org/c/flashrom/+/83359/comment/338bfa18_ff346891?us… :
PS1, Line 38: Note: the migration process is half way.
> Should this mention that the wiki is deprecated and will go away eventually, but information from th […]
Yes good idea I added this info.
https://review.coreboot.org/c/flashrom/+/83359/comment/e3fa4d80_6eab39ce?us… :
PS1, Line 46: Our current two build systems, meson and make, are on par
: ---------------------------------------------------------
:
: Both build systems support the same platforms and both are documented (however, unit tests only supported with meson).
:
: **This is the last release with two build systems. With the next release, make and Makefile will no longer be supported, and we will have one build system: meson.**
> As with the delay section, I think this should highlight things that might affect users (or in this […]
Done
https://review.coreboot.org/c/flashrom/+/83359/comment/fd834aee_88534a40?us… :
PS1, Line 292: Download
> I think this should be at the top, right after the intro paragraph.
Done
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Hello Alexander Goncharov, Nikolai Artemiev, Peter Marheine, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: doc: Release notes for version 1.4.0
......................................................................
doc: Release notes for version 1.4.0
Change-Id: Ie5597f1c3ae9289e424f54c2d313fef8efbdf1a0
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/release_notes/index.rst
A doc/release_notes/v_1_4.rst
2 files changed, 314 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/83359/2
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Change subject: flashchips: Add support for MXIC MX25U25645G
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/UUDQ…
I am leaving the comment unresolved, so that not to accidentally submit before the tag.
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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 10:
(1 comment)
File ch347_spi.c:
https://review.coreboot.org/c/flashrom/+/82776/comment/8cfca522_10cbade0?us… :
PS7, Line 365: 30MHz
> What is the CH347T device revision that can reproduce this phenomenon?
I'd have to do a bit of digging as I don't know of a quick way to find this. I don't remember seeing a way to retrieve this from WCH's example applications, but I think there was a call in the API for their library that can retrieve this. In any case, I bought mine in September 2022, and I think the CH347T was still fairly new at the time.
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Change subject: flashchips: Add support for MXIC MX25U25645G
......................................................................
Patch Set 1:
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82777/comment/33955534_cb946108?us… :
PS1, Line 11104: 512B
> Datasheet says `8K-bit secured OTP` so I think this is 1024B
Done
https://review.coreboot.org/c/flashrom/+/82777/comment/0ef98192_3c43b37f?us… :
PS1, Line 11111: {
: .eraseblocks = { {4 * 1024, 8192} },
: .block_erase = SPI_BLOCK_ERASE_21,
: },
> I don't see it in datasheet (I mean: 21h, 5Ch, DCh)? I see there is: […]
Please refer to the figure-55 to figure-57 which describe 21h, 5Ch, DCh command, thanks.
https://review.coreboot.org/c/flashrom/+/82777/comment/f86d2919_27e4670d?us… :
PS1, Line 11137: /* TODO: security register */
> You can remove TODO, you added security register bits below
Done
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Change subject: doc: Release notes for version 1.4.0
......................................................................
Patch Set 1:
(6 comments)
File doc/release_notes/v_1_4.rst:
https://review.coreboot.org/c/flashrom/+/83359/comment/530d7d58_89a90541?us… :
PS1, Line 5: Release notes for flashrom version 1.4.0.
It seems nice to include a little intro paragraph here, acknowledging contributors and providing a little bit of context.
> This document describes the major changes in flashrom version 1.4.0, from 438 patches contributed by 73 authors in the 6 months since version 1.3.0.
(I used `git shortlog -s -n v1.3.0..v1.4.0-rc1` to count authors, and `git log --oneline v1.3.0..v1.4.0-rc1` to count commits.)
https://review.coreboot.org/c/flashrom/+/83359/comment/2e6720aa_b5ca7e10?us… :
PS1, Line 10: Fix AMD programmer (sb600spi.c) for Promontory and chips >16MB size
I see this is the title of the issue, but starting a known issue with "Fix" seems confusing.
Probably this should be phrased more like:
> AMD-based PCs with FCH are unable to read flash contents for internal (BIOS flash) chips larger than 16 MB, and attempting to do so may crash the system. Systems with AMD "Promontory" IO extenders (mostly "Zen" desktop platforms) are not currently supported.
https://review.coreboot.org/c/flashrom/+/83359/comment/41d3063c_0b9be174?us… :
PS1, Line 29:
: * Calibration loop is not used anymore, except for DOS
: * Removed unconditional 1 second delay for SPI chips
: * Lower the sleep vs delay threshold to 0.1 seconds
: * Tree-wide refactorings around programmer_delay and internal_delay
This is technically all true, but I think it should be rearranged to highlight the parts that users might need to be aware of.
```suggestion
* Flashrom now sleeps more aggressively when a delay is required, rather than
polling in a loop. This should reduce power consumption significantly, but
may require more time to complete operations on systems experiencing high
CPU load.
* An unconditional 1-second delay was removed for SPI flashes. This is not
believed to be needed for any SPI flashes, but may be needed for some old
parallel flashes (where it remains in used).
* Cycle-counting busy loops are now only used on DOS builds of flashrom. All
other platforms use OS timers for timed delays, which are expected to be
more accurate.
* Tree-wide refactorings around programmer_delay and internal_delay
```
https://review.coreboot.org/c/flashrom/+/83359/comment/f2237443_b2aaff81?us… :
PS1, Line 38: Note: the migration process is half way.
Should this mention that the wiki is deprecated and will go away eventually, but information from the wiki is being migrated?
https://review.coreboot.org/c/flashrom/+/83359/comment/db7ef4a8_e67bea8d?us… :
PS1, Line 46: Our current two build systems, meson and make, are on par
: ---------------------------------------------------------
:
: Both build systems support the same platforms and both are documented (however, unit tests only supported with meson).
:
: **This is the last release with two build systems. With the next release, make and Makefile will no longer be supported, and we will have one build system: meson.**
As with the delay section, I think this should highlight things that might affect users (or in this case, distributors).
```suggestion
Makefile scheduled for removal
------------------------------
**Future versions of flashrom will drop support for building via Makefile**: Meson will become the only supported build system.
The Makefile and meson build systems are currently at feature parity, except automated testing is supported only with meson. To reduce the maintenance burden, we plan to remove the Makefile after this release.
```
https://review.coreboot.org/c/flashrom/+/83359/comment/e1316fd6_f821d319?us… :
PS1, Line 292: Download
I think this should be at the top, right after the intro paragraph.
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Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
I downloaded the patch to try generate locally and see how it looks. It looks good :) I only have one comment.
File doc/contrib_howtos/how_to_add_new_chip.rst:
https://review.coreboot.org/c/flashrom/+/82908/comment/27e5e9c5_15c8bfda?us… :
PS1, Line 120: This
> Done […]
Yes, .rst to .html converting ignores new lines. Empty line will create a new paragraph.
File doc/contrib_howtos/how_to_add_new_chip.rst:
https://review.coreboot.org/c/flashrom/+/82908/comment/1900b6a3_dbc11a2f?us… :
PS2, Line 108: Some of the feature bits have more detailed docs, see below.
Add new line (empty line) before #108
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Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Acknowledged
I am leaving this comment unresolved, so that the patch won't be accidentally submitted before the tag.
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Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
Thanks
PS3:
> Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July. […]
Acknowledged
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