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Change subject: flashchips: Add Support for XMC XM25QU512C/XM25QU512D
......................................................................
Patch Set 4:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83243/comment/70f440b4_016647ac?us… :
PS2, Line 22490: 64*1024
> Please add spaces around `*`
Done
https://review.coreboot.org/c/flashrom/+/83243/comment/156c1aef_acda62ae?us… :
PS2, Line 22506: .eraseblocks = { {4 * 1024, 16384} },
> Please intend this line like the others
Done
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add Support for XMC XM25QU512C/XM25QU512D
......................................................................
flashchips: Add Support for XMC XM25QU512C/XM25QU512D
Add initial support for the SPI flash chip XM25QU512C/XM25QU512D
Datasheet link: https://www.xmcwh.com/uploads/808/XM25QU512C_V1.6.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I251c66b5d3b4fc94242c2c9d6b7c0f03c1bd7d0b
Signed-off-by: Kan Sun <ssunkkan(a)gmail.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/83243/4
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Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
......................................................................
Patch Set 3:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83242/comment/6aaecbf7_05b64ca8?us… :
PS2, Line 22442: 64*1024
> Please add spaces around `*`: `64 * 1024` […]
Done
https://review.coreboot.org/c/flashrom/+/83242/comment/5f71dc7f_6a6989c5?us… :
PS2, Line 22458: .eraseblocks = { {4 * 1024, 16384} },
> This line needs to be intended like the others
Done
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/83242?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
......................................................................
flashchips: Add Support for XMC XM25QH512C/XM25QH512D
Add initial support for the SPI flash chip XM25QH512C/XM25QH512D
Datasheet link: https://www.xmcwh.com/uploads/803/XM25QH512C_V1.6.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: Ica8ed5eaba2435a9416274b94f633ea40dfeea2f
Signed-off-by: Kan Sun <ssunkkan(a)gmail.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/83242/3
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Change subject: doc: Add doc for in-system programming
......................................................................
doc: Add doc for in-system programming
The page on wiki is here:
https://wiki.flashrom.org/ISP
Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
A doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg
A doc/user_docs/Pomona_5250_soic8.jpg
A doc/user_docs/in_system.rst
M doc/user_docs/index.rst
4 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/83451/1
diff --git a/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg
new file mode 100644
index 0000000..c3db692
--- /dev/null
+++ b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg
Binary files differ
diff --git a/doc/user_docs/Pomona_5250_soic8.jpg b/doc/user_docs/Pomona_5250_soic8.jpg
new file mode 100644
index 0000000..83f8c3e
--- /dev/null
+++ b/doc/user_docs/Pomona_5250_soic8.jpg
Binary files differ
diff --git a/doc/user_docs/in_system.rst b/doc/user_docs/in_system.rst
new file mode 100644
index 0000000..84716d3
--- /dev/null
+++ b/doc/user_docs/in_system.rst
@@ -0,0 +1,45 @@
+=====================
+In-System Programming
+=====================
+
+**In-System Programming** (ISP) sometimes also called **in situ programming** is used to describe
+the procedure of writing a flash chip while it is (already/still) attached to the circuit
+it is to be used with. Of course any normal "BIOS flash" procedure is a kind of ISP
+but when we refer to ISP we usually mean something different: programming a flash chip by external means
+while it is mounted on a motherboard.
+
+This is usually done with SPI chips only. Some mainboards have a special header for this
+(often named "ISP", "ISP1", or "SPI") and there should be no problem with accessing the chip
+then as long as the wires are not too long.
+
+If there is no special header then using a special SO(IC) clip is an easy and reliable way
+to attach an external programmer. They are produced by different vendors (e.g. Pomona, 3M)
+and are available from many distributors (e.g. Distrelec) for 20-50$/€.
+
+Problems
+========
+
+* Check the other potential problems (:doc:`misc_notes`) with other types of programming setups first.
+* The SPI bus is not isolated enough. Often parts of the chipset are powered on partially
+ (by the voltage supplied via the Vcc pin of the flash chip). In that case
+ disconnect Vcc from the programmer and power it with its normal PSU and:
+
+ * Try powering up the board normally and holding it in reset (e.g. use a jumper instead of the reset push button).
+ * Some chipsets (e.g. Intel ICHs/PCHs) have edge triggered resets. In this case holding them in reset will not work.
+ This is especially a problem with Intel chipsets because they contain an EC (named ME by Intel, see :doc:`management_engine`),
+ which uses the flash (r/w!). In this case you can trigger the reset line in short intervals.
+ For example by connecting it to the chip select (CS) line of the SPI bus or a dedicated clock signal from the programmer.
+ This should not be too fast though! Reset lines usually require pulses with a minimum duration.
+ * On some boards, you can try disconnecting the ATX12V header (yellow/black wires only) from the motherboard,
+ or even remove the CPU or RAM - if the programmer supports SPI sniffing, you may be able to verify that the there is no SPI traffic.
+
+Images
+========
+
+Pomona 8-pin SOIC clip with attached jumper wires.
+
+.. image:: Pomona_5250_soic8.jpg
+
+A cheap, but very fragile alternative: DIP socket as clip
+
+.. image:: 1200px-DIP_socket_as_SOIC_clip.jpg
diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst
index 960659e..3ca928a 100644
--- a/doc/user_docs/index.rst
+++ b/doc/user_docs/index.rst
@@ -9,4 +9,5 @@
chromebooks
management_engine
misc_intel
+ in_system
misc_notes
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Change subject: doc: Add page with misc notes and advice
......................................................................
doc: Add page with misc notes and advice
This page is a combination of info from the following pages:
https://wiki.flashrom.org/Common_problemshttps://wiki.flashrom.org/Connectionshttps://wiki.flashrom.org/FAQhttps://wiki.flashrom.org/Random_noteshttps://wiki.flashrom.org/Live_CD
Change-Id: I538f31765576584760524cd8b06cbf5bce191bde
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/user_docs/index.rst
A doc/user_docs/misc_notes.rst
2 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/50/83450/1
diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst
index b61567a..960659e 100644
--- a/doc/user_docs/index.rst
+++ b/doc/user_docs/index.rst
@@ -9,3 +9,4 @@
chromebooks
management_engine
misc_intel
+ misc_notes
diff --git a/doc/user_docs/misc_notes.rst b/doc/user_docs/misc_notes.rst
new file mode 100644
index 0000000..fcb1700
--- /dev/null
+++ b/doc/user_docs/misc_notes.rst
@@ -0,0 +1,149 @@
+=====================
+Misc notes and advice
+=====================
+
+This document contains miscellaneous and unstructured (and mostly, legacy) notes and advice about using flashrom.
+
+Command set tricks for parallel and LPC chips
+=============================================
+
+This is only mentioned in very few datasheets, but it applies to some parallel (and some LPC) chips.
+
+Upper address bits of commands are ignored if they are not mentioned explicitly. If a datasheet specifies the following sequence::
+
+ chip_writeb(0xAA, bios + 0x555);
+ chip_writeb(0x55, bios + 0x2AA);
+ chip_writeb(0x90, bios + 0x555);
+
+then it is quite likely the following sequence will work as well::
+
+ chip_writeb(0xAA, bios + 0x5555);
+ chip_writeb(0x55, bios + 0x2AAA);
+ chip_writeb(0x90, bios + 0x5555);
+
+However, if the chip datasheet specifies addresses like ``0x5555``, you can't shorten them to ``0x555``.
+
+To summarize, replacing short addresses with long addresses usually works, but the other way round usually fails.
+
+flashrom doesn't work on my board, what can I do?
+=================================================
+
+* First of all, check if your chipset, ROM chip, and mainboard are supported
+ (see :doc:`/supported_hw/index`).
+* If your board has a jumper for BIOS flash protection (check the manual), disable it.
+* Should your BIOS menu have a BIOS flash protection option, disable it.
+* If you run flashrom on Linux and see messages about ``/dev/mem``, see next section.
+* If you run flashrom on OpenBSD, you might need to obtain raw access permission by setting
+ ``securelevel = -1`` in ``/etc/rc.securelevel`` and rebooting, or rebooting into single user mode.
+
+What can I do about /dev/mem errors?
+====================================
+
+* If flashrom tells you ``/dev/mem mmap failed: Operation not permitted``:
+
+ * Most common at the time of writing is a Linux kernel option, ``CONFIG_IO_STRICT_DEVMEM``,
+ that prevents even the root user from accessing hardware from user-space if the resource is unknown
+ to the kernel or a conflicting kernel driver reserved it. On Intel systems, this is most often ``lpc_ich``,
+ so ``modprobe -r lpc_ich`` can help. A more invasive solution is to try again after rebooting
+ with ``iomem=relaxed`` in the kernel command line.
+
+ * Some systems with incorrect memory reservations (e.g. E820 map) may have the same problem
+ even with ``CONFIG_STRICT_DEVMEM``. In that case ``iomem=relaxed`` in the kernel command line may help too.
+
+* If it tells you ``/dev/mem mmap failed: Resource temporarily unavailable``:
+
+ * This may be an issue with PAT (e.g. if the memory flashrom tries to map is already mapped
+ in an incompatible mode). Try again after rebooting with nopat in the kernel command line.
+
+* If you see this message ``Can't mmap memory using /dev/mem: Invalid argument``:
+
+ * Your flashrom is very old, better update it. If the issue persists, try the kernel options mentioned above.
+
+* Generally, if your version of flashrom is very old, an update might help.
+ Flashrom has less strict requirements now and works on more systems without having to change the kernel.
+
+Connections
+===========
+
+Using In-System programming requires some means to connect the external programmer to the flash chip.
+
+Note that some external flashers (like the Openmoko debug board) lack a connector,
+so they do requires some soldering to be used. Some other don't. For instance the buspirate has a pin connector on it.
+
+Programmer <-> Removable chip connection
+----------------------------------------
+
+A breadboard can be used to connect Dual in-line 8 pins chips to the programmer, as they they fit well into it.
+
+Programmer <-> Clip connection
+------------------------------
+
+If your programmer has a pin connector, and that you want to avoid soldering, you can use
+**Short** `Jump Wires <https://en.wikipedia.org/wiki/Jump_wire>`_ to connect it to a clip.
+They usually can be found on some electronic shops.
+
+Other issues
+-------------
+
+* Wires length and connection quality: Long wires, and bad connection can create some issues, so avoid them.
+
+ * The maximum wires length is very dependent on your setup, so try to have the shortest wires possible.
+ * If you can't avoid long wires and if you're flash chip is SPI, then lowering the SPI clock could make
+ it work in some cases. Many programmers do support such option (Called spispeed with most of them, or divisor with ft2232_spi).
+
+* When soldering wires, the wire tend to break near the soldering point. To avoid such issue,
+ you have to prevent the wires from bending near the soldering point.
+ To do that `Heat-shrink_tubing <https://en.wikipedia.org/wiki/Heat-shrink_tubing>`_ or similar methods can be used.
+
+Common problems
+===============
+
+The following describes problems commonly found when trying to access flash chips in systems
+that are not designed properly for this job, e.g. ad-hoc setups to flash in-system
+(TODO add a doc for in-system-specific problems).
+
+Symptoms indicating you may have at least one of these are for example inconsistent reads or probing results.
+This happens basically because the analog electrical waveforms representing the digital information
+get too distorted to by interpreted correctly all the time. Depending on the cause different steps can be tried.
+
+* Not all input pins are connected to the correct voltage level/output pin of the programmer.
+ Always connect all input pins of ICs!
+
+* The easiest thing to try is lowering the (SPI) clock frequency if your programmer supports it.
+ That way the waveforms have more time to settle before being sampled by the receiver which might be enough.
+ Depending on the design of the driver and receiver as well as the actual communication path
+ this might not change anything as well.
+
+* Wires are too long. Shortening them to a few cm (i.e. < 20, the lesser the better) might help.
+
+* The impedances of the wires/traces do not match the impedances of the input pins
+ (of either the circuit/chip on the mainboard or the external programmer).
+ Try using shorter wires, adding small (<100 Ohm) series resistors or parallel capacitors (<20pF)
+ as near as possible to the input pins (this includes also the MISO line which ends near the programmer)\
+ and/or ask someone who has experience with high frequency electronics.
+
+* The supply voltage of the flash chip is not stable enough. Try adding a 0.1 µF - 1 µF (ceramic) capacitor
+ between the flash chip's VCC and GND pins as near as possible to the chip.
+
+Live CD
+=========
+
+A Live CD containing flashrom provides a user with a stable work environment to read, write and verify a flash device on any supported hardware.
+
+It can help avoid Linux installation issues, which can be a hassle for some users.
+
+flashrom is already shipped in some of the Live CDs, see below. *Please note, some of these ship very old versions of flashrom*.
+
+* `SystemRescueCd <http://www.sysresccd.org/>`_ has been including flashrom since about version 2.5.1.
+
+* `grml <http://grml.org/>`_
+
+ * Note: You need the full grml ISO, "small" (and "medium") ISOs do not contain flashrom.
+ * Note: Some releases (e.g. 2011.12) did not contain flashrom.
+
+* `Parted Magic <http://partedmagic.com/>`_
+
+* `Hiren's BootCD <http://www.hirensbootcd.org/>`_
+
+ * When you select "Linux based rescue environment (Parted Magic 6.7)" and then "Live with default settings",
+ you have access to a system which has flashrom.
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Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
......................................................................
Patch Set 2:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83242/comment/18257997_60f34749?us… :
PS2, Line 22447: FEATURE_4BA_ENTER_WREN
Same question as in other patch for 512 models, about enter/exit 4-byte
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Change subject: flashchips: Add Support for XMC XM25QU512C/XM25QU512D
......................................................................
Patch Set 2:
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83243/comment/94f8098a_f5eb9657?us… :
PS2, Line 22490: 64*1024
Please add spaces around `*`
https://review.coreboot.org/c/flashrom/+/83243/comment/5fe68caa_61734b15?us… :
PS2, Line 22495: FEATURE_4BA_ENTER_WREN
Does enter/exit 4-byte mode depend on WREN? Or can it be done without WREN?
I did not find in datasheet that it depends on WREN, maybe I missed?
There is another feature bit `FEATURE_4BA_ENTER`, without WREN.
https://review.coreboot.org/c/flashrom/+/83243/comment/fbeba744_482a8f4f?us… :
PS2, Line 22506: .eraseblocks = { {4 * 1024, 16384} },
Please intend this line like the others
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Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
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Patch Set 2:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83242/comment/9343530b_933ac4aa?us… :
PS2, Line 22442: 64*1024
Please add spaces around `*`: `64 * 1024`
This comes from our code style: https://flashrom.org/dev_guide/development_guide.html#coding-style (which mostly follows Linux kernel style).
https://review.coreboot.org/c/flashrom/+/83242/comment/c6537cab_2f046540?us… :
PS2, Line 22458: .eraseblocks = { {4 * 1024, 16384} },
This line needs to be intended like the others
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Change subject: flashchips: Add Support for XMC XM25QU256D
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/UUDQ…
I am leaving the comment unresolved, so that not to accidentally submit before the tag.
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