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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/82626/comment/53b95ded_c4afbc6e?us… :
PS3, Line 10:
Please add test information in commit message.
Specifically, which programmer you are using (if that is internal, then which board was it on).
Also which operations have you tested. From the other comment, if you are testing write-protect, also mention which exactly operations you were testing for wp.
Thank you!
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82626/comment/bd199659_1790d1b1?us… :
PS3, Line 11618: 65536
> we might need to fake this part to show the max capacity is 32MB
I think this kind of custom adjustments should be added to ChromeOS fork (which is I assume what you meant to say, but I just want to be clear).
I fully understand the idea to speed up flashing if you only happen to use half of available capacity. But if this flash has 64MB size, it should be defined like this in the flashchip definition. We have users around the world, and upstream definition should correctly describe the features of the chip model.
https://review.coreboot.org/c/flashrom/+/82626/comment/170295c4_aa379a58?us… :
PS3, Line 11620: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
> In the datasheet, this Flash doesn't support FEATURE_WRSR2, FEATURE_WRSR3.
How many bytes status register has? Perhaps it should be defined with `FEATURE_WRSR_EXT2` and/or `FEATURE_WRSR_EXT3` ?
It depends on whether you can only write the whole status register (all bytes at the same time), or you can write each byte independently.
https://review.coreboot.org/c/flashrom/+/82626/comment/98f8f88d_09500662?us… :
PS3, Line 11648: },
> OK, thank you for providing these backgroud information.
If you plan to add write-protect support (i.e. define reg_bits), you also need to test it , and mark test status accordingly. Current test status TEST_OK_PREW indicates that write-protect is not tested. If you test it successfully, then test status should be updated to TEST_OK_PREWB
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Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Patchset:
PS3:
Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/UUDQ…
I am leaving the comment unresolved, so that not to accidentally submit before the tag.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83242/comment/f7663279_b559f65a?us… :
PS2, Line 22447: FEATURE_4BA_ENTER_WREN
> Same question as in other patch for 512 models, about enter/exit 4-byte
Done
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Change subject: flashchips: Add Support for XMC XM25QU512C/XM25QU512D
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Patchset:
PS4:
Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/UUDQ…
I am leaving the comment unresolved, so that not to accidentally submit before the tag.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83243/comment/967f7302_f4987e50?us… :
PS2, Line 22495: FEATURE_4BA_ENTER_WREN
> Since 256Mb or more requires 4 bytes for addressing, the enter/exit 4-byte address mode operation is […]
Thanks so much for the explanation! I understand now, all good.
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82626/comment/40901888_0b2fa5ff?us… :
PS3, Line 11648: },
> > > please add below details as well […]
OK, thank you for providing these backgroud information.
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82626/comment/fd806f97_3cd9c316?us… :
PS3, Line 11618: 65536
> Yes, the Flash density is 64MB
Not sure if you can access https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/…. We don't plan to use 64MB flash out hence, we might need to fake this part to show the max capacity is 32MB. Flashing 64MB takes significantly higher time.
https://review.coreboot.org/c/flashrom/+/82626/comment/8d4bcdb4_d4459a53?us… :
PS3, Line 11648: },
> > please add below details as well
> >
> > ```
> > .reg_bits =
> > {
> > ...
> > }
> > .decode_range
> > ```
>
> I think user don't have to add this detail if they haven't test the write protection function for this Flash.
this is must for the ChromeOS device hence, asked to specify those details.
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3: Code-Review+1
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82626/comment/daebb496_d01d730b?us… :
PS3, Line 11618: 65536
> I believe this is 64MB SPI flash. […]
Yes, the Flash density is 64MB
https://review.coreboot.org/c/flashrom/+/82626/comment/0801c80f_be67b82a?us… :
PS3, Line 11620: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
> it doesn't support FEATURE_WRSR2, FEATURE_WRSR3?
In the datasheet, this Flash doesn't support FEATURE_WRSR2, FEATURE_WRSR3.
https://review.coreboot.org/c/flashrom/+/82626/comment/c85853d3_a64343e8?us… :
PS3, Line 11648: },
> please add below details as well
>
> ```
> .reg_bits =
> {
> ...
> }
> .decode_range
> ```
I think user don't have to add this detail if they haven't test the write protection function for this Flash.
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Change subject: flashchips: Add Support for XMC XM25QU512C/XM25QU512D
......................................................................
Patch Set 4:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83243/comment/9e08c614_095570c2?us… :
PS2, Line 22495: FEATURE_4BA_ENTER_WREN
> Does enter/exit 4-byte mode depend on WREN? Or can it be done without WREN? […]
Since 256Mb or more requires 4 bytes for addressing, the enter/exit 4-byte address mode operation is required.
XMC has defined enter/exit 4-byte address mode without WREN (06h) command in the SFDP table of 256Mb+ capacity Datasheet.
We don't need to add WREN (06h) command before enter/exit 4-byte address mode, but it's OK to add WREN (06h) command or no WREN (06h) command in front of it, it won't affect.
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Hello Daniel! Since I don't have datasheet I can't do the review, but I thought maybe you can? You h […]
OK, I will review this patch in next week.
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Change subject: doc: Release notes for version 1.4.0
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS1:
> This makes sense, I agree. […]
So now this comment should be:
Submit just before updating VERSION file to 1.4.0
File doc/release_notes/v_1_4.rst:
https://review.coreboot.org/c/flashrom/+/83359/comment/5c12acf2_1014c5b8?us… :
PS1, Line 300: <TODO add link>
> Add link for tarball
non-blocking: will add link and signature after the tag
https://review.coreboot.org/c/flashrom/+/83359/comment/1a121c10_bf6caca9?us… :
PS1, Line 302: <TODO add>
> Add fingerprint
non-blocking: will add fingerprint after the tag
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
> Hi, our Macronix product manager will discuss this issue recently.
Hello Daniel! Since I don't have datasheet I can't do the review, but I thought maybe you can? You have experience adding support for new chip models, and you contributed a bunch already. Maybe you can review this patch?
The way you do it, open the datasheet, open the patch, and verify each field in chip definition one by one. If you spot anything wrong or unclear, add a comment. If everything is correct, then you can respond and vote +1 on this patch. +1 from you would mean you reviewed and approve.
Do you think you could do it? That would be a lot of help! Thank you!
PS3:
> > Yes, I have the datasheet and chip. We were able to flash with this patch. […]
Yes I was asking in the other comment earlier, if it's possible to send datasheet to me (e.g. by email) so that I can do the review. I was waiting for a follow up on that.
However, another thing I thought about after I read your comment.
We have a patch, and Bora is the author, so we need someone else who has datasheet, to do a review. Perhaps you or Daniel could do that? I don't know if you have datasheet before your eyes, but I would assume Daniel can have it.
I see your other comments, and maybe you started reviewing already! Thank you for your help.
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Gerrit-Branch: main
Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c
Gerrit-Change-Number: 82626
Gerrit-PatchSet: 3
Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Comment-Date: Fri, 19 Jul 2024 06:55:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com>
Comment-In-Reply-To: DZ <danielzhang(a)mxic.com.cn>
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>